Advantech PCI-1710 - Manual

Chapter 1 General Information 3 On-board Programmable Counter The PCI-1710/1710HG provides a programmable counter for generat-ing a pacer trigger for the A/D conversion. The counter chip is an82C54 or equivalent, which includes three 16-bit counters on a 10MHz clock. One counter is used as an event ...

Chapter 1 General Information 5 • Maximum data throughput: PCI-1710: 100 kHz PCI-1710HG: (variable, depending on PGIA settling time) PCI-1710HG Gain Speed 0.5, 1 100 kHz 5, 10 35 kHz 50, 100 7 kHz 500, 1000 770 Hz PCI-1710 PCI-1710HG Gain Accuracy Gain Accuracy Remark 0.5, 1 0.01% of FSR ±1 LSB 0.5,...

Chapter 1 General Information 7 Programmable Timer/Counter • Counter chip: 82C54 or equivalent • Counters: 3 channels, 16 bits, 2 channels are permanently configured as programmable pacers; 1 channel is freefor user application • Input, gate: TTL/CMOS compatible • Time base: Channel 1:10 MHz Channel...

10 PCI-1751/1710HG User's Manual 2.1 Initial Inspection Before installing the PCI-1710/1710HG, check the card for visibledamage. We have carefully inspected the card both mechanically andelectrically before shipment. It should be free of marks and in perfectorder upon receipt. As you unpack the PCI-...

Chapter 2 Installation 11 2.3 Installation Instructions The PCI-1710/1710HG can be installed in any PCI slot in thecomputer. However, refer to the computer user's manual to avoid anymistakes and danger before you follow the installation procedurebelow: 1. Turn off your computer and any accessories c...

Chapter 3 Signal Connections 13 3 Signal Connections CHAPTER

1 4 PCI-1710/1710HG User's Manual 3.1 Overview Correct signal connections are one of the most important factors inensuring that your application system is sending and receiving datacorrectly. A good signal connection can avoid much unnecessary andcostly damage to your valuable PC and other hardware ...

Chapter 3 Signal Connections 15 Figure 3-1: I/O connector pin assignments for the PCI-1710/1710 HG card A I 0A I 2A I 4A I 6A I 8 A I 1 0A I 1 2A I 1 4 A I G N D D A 0 _ R E F D A 0 _ O U T A O G N D D I 0D I 2D I 4D I 6D I 8 D I 1 0D I 1 2D I 1 4 D G N D D O 0D O 2D O 4D O 6D O 8 D O 1 0D O 1 2D O ...

1 6 PCI-1710/1710HG User's Manual I/O Connector Signal Descriptions Signal Name Reference Direction Description AI<0…15> AIGND Input Analog Input Channels 0 through 15. Each channel pair, AI<i, i+1> (i = 0, 2, 4...14), can beconfigured as either two single-ended inputs orone differential...

Chapter 3 Signal Connections 17 I/O Connector Signal Descriptions (part II) Signal Name Reference Direction Description DI<0..15> DGND Input Digital Input signals DO<0..15> DGND Output Digital Output signals DGND - - Digital Ground. This pin supplies thereference for the digital signals ...

Chapter 3 Signal Connections 19 3.3 Analog Input Connections The PCI-1710/1710HG card supports either 16 single-ended or 8differential analog inputs. Input channel configuration is selected bysoftware. Selection by software is more convenient than selection bya slide switch on the card. In the past,...

2 0 PCI-1710/1710HG User's Manual Figure 3-2: Single-ended input channel connection Differential Channel Connections The differential input configuration has two signal wires for eachchannel, and the differential input responds only to voltage differenc-es between High and Low inputs. On the PCI-171...

Chapter 3 Signal Connections 21 card. With this connection, the PGIA rejects a common-mode voltageV cm between the signal source and the PCI-1710/1710HG ground, shown as V cm in Figure 3-3. Figure 3-3: Differential input channel connection - ground reference signal source If a floating signal source...

Chapter 3 Signal Connections 23 Figure 3-5: Analog output connections 3.4 Analog Output Connections The PCI-1710/1710HG card provides two D/A output channels,DA0_OUT and DA1_OUT. Users may use the PCI-1710/1710HGinternally provided precision –5V (-10V) reference to generate 0 to +5 V(+10 V) D/A outp...

2 4 PCI-1710/1710HG User's Manual 3.5 Trigger Source Connections Internal Pacer Trigger Connection The PCI-1710/1710HG card includes one 82C54 compatible programma-ble timer/counter chip which provides three 16-bit counters connectedto a 1 MHz clock, designated as Counter 0, Counter 1 and Counter 2....

Chapter 3 Signal Connections 25 3.6 Field Wiring Considerations When you use the PCI-1710/1710HG card to acquire outside data,environmental noise can seriously affect the accuracy of your mea-surements if you don’t provide any protection. The following sugges-tions will be helpful when running signa...

Chapter 4 Register Structure and Format 27 4 Register Structure and Format CHAPTER

Chapter 4 Register Structure and Format 31 Base Address + decimal Write 7 6 5 4 3 2 1 0 Software A/D Trigger 1 0 A/D Channel Range Setting 3 2 S/D B/U G2 G1 G0 MUX Control 5 Stop channel 4 Start channel Control Register 7 6 CNT0 ONE/FH IRQEN GATE EXT PACER SW Clear Interrupt and FIFO 9 clear FIFO 8 ...

Chapter 4 Register Structure and Format 33 4.3 Channel Number and A/D Data — BASE+0 and BASE+1 These two bytes, BASE+0 and BASE+1, hold the result of A/Dconversion data. The 12 bits of data from the A/D conversion arestored in BASE+1 bit 3 to bit 0 and BASE+0 bit 7 to bit 0. BASE+1bit 7 to bit 4 hol...

34 PCI-1710/1710HG User's Manual 4.5 A/D Channel Range Setting — BASE+2 Each A/D channel has its own input range, controlled by a range codestored in the on-board RAM. If you want to change the range codefor a given channel, select the channel as the start channel and the stopchannel in the register...

Chapter 4 Register Structure and Format 35 PCI-1710 Gain Input Range(V) B/U Gain Code G2 G1 G0 1 -5 to +5 0 0 0 0 2 -2.5 to +2.5 0 0 0 1 4 -1.25 to +1.25 0 0 1 0 8 -0.625 to +0.625 0 0 1 1 0.5 -10 to 10 0 1 0 0 N/A 0 1 0 1 N/A 0 1 1 0 N/A 0 1 1 1 1 0 to 10 1 0 0 0 2 0 to 5 1 0 0 1 4 0 to 2.5 1 0 1 0...

36 PCI-1710/1710HG User's Manual PCI-1710HG Gain Input Range(V) B/U Gain Code G2 G1 G0 1 -5 to +5 0 0 0 0 10 -0.5 to +0.5 0 0 0 1 100 -0.05 to +0.05 0 0 1 0 1000 -0.005 to +0.005 0 0 1 1 0.5 -10 to +10 0 1 0 0 5 -1 to +1 0 1 0 1 50 -0.1 to +0.1 0 1 1 0 500 -0.01 to +0.01 0 1 1 1 1 0 to 10 1 0 0 0 10...

Chapter 4 Register Structure and Format 37 4.6 MUX Control—BASE+4 and BASE+5 Table 4.6: The register for multiplexer control CL3 ~ CL0 Start Scan Channel Number CH3 ~ CH0 Stop Scan Channel Number BASE+4 bit 3 to bit 0, CL3 ~ CL0, act as a pointer when you programthe A/D channel setting (see previous...

38 PCI-1710/1710HG User's Manual the stop channel and then repeat. The following examples show thescan sequences of the MUXs (all channels are set as single-ended). Example 1 If the start scan input channel is AI3 and the stop scan input channel is AI7, then the scan sequence is AI3, AI4, AI5,AI6, A...

Chapter 4 Register Structure and Format 39 differential, and AI14 is differential, then the scan sequence is AI11,AI12, AI14, AI11, AI12, AI14, AI11… Warning! Only even channels can be set as differential. An odd channel will become unavailable if its precedingchannel is set as differential. 4.7 Con...

40 PCI-1710/1710HG User's Manual GATE External trigger gate function enable bit Set 1 to enable external trigger gate function, and set 0 to disable. IRQEN Interrupt enable bit Set 1 to enable interrupt, and set 0 to disable. ONE/FH Interrupt source bit Set 0 to interrupt when an A/D conversion occu...

Chapter 4 Register Structure and Format 41 F/H FIFO Half-full flag This bit indicates whether the FIFO is half-full. 1 means that the FIFOis half-full. F/F FIFO Full flag This bit indicates whether the FIFO is full. 1 means that the FIFO isfull. IRQ Interrupt flag This bit indicates the interrupt st...

42 PCI-1710/1710HG User's Manual 4.10 D/A Output Channel 0 — BASE+10 and BASE+11 The write-only registers of BASE+10 and BASE+11 accept data forD/A Channel 0 output. Table 4-10: Registers for D/A channel 0 data DA11 ~ DA0 Digital to Analog data DA0 is the LSB and DA11 is the MSB of the D/A data. 4.1...

Chapter 4 Register Structure and Format 43 4.12 D/A Reference Control — BASE+14 The write-only register of BASE+14 allows users to set the D/Areference source. Table 4-12: Registers for D/A reference control DA0_5/10 The internal reference voltage for the D/A outputchannel 0 This bit controls the in...

46 PCI-1710/1710HG User's Manual 5.1 Introduction Regular calibration checks are important to maintain accuracy in dataacquisition and control applications. We provide two calibrationprograms, ADCAL.EXE and DACAL.EXE, on the PCI-1710/1710HGsoftware CD-ROM. ADCAL.EXE assists you in A/D calibration, a...

Chapter 5 Calibration 47 The following list shows the function of each VR: VR Function VR1 A/D unipolar offset VR2 A/D bipolar offset VR3 A/D full scale (gain) VR4 D/A channel 0 full scale VR5 D/A channel 1 full scale 5.3 A/D Calibration Regular and accurate calibration procedures ensure the maximum...

48 PCI-1710/1710HG User's Manual 5.4 D/A Calibration In a way similar to the ADCAL.EXE program, the DACAL.EXEprogram leads you through the whole D/A calibration procedure. You can either use the on-board -5 V (-10 V) internal referencevoltage or use an external reference. If you use an external refe...

Chapter 5 Calibration 49 5.5 Self A/D Calibration Under many conditions, it is diff icult to f ind a good enough DCvoltage source for A/D calibration. There is a simple method to solvethis problem. First, you should calibrate D/A channel 0, DA0_OUT,with internal reference -5 V, and D/A channel 1, DA...

Appendix A 8524 Counter Chip Functions 51 A 82C54 Counter Chip Functions APPENDIX

52 PCI-1750 User's Manual A.1 The Intel 82C54 The PCI-1710/1710HG uses one Intel 82C54 compatible programma-ble interval timer/counter chip. The popular 82C54 offers threeindependent 16-bit counters, counter 0, counter 1 and counter 2. Eachcounter has a clock input, control gate and an output. You c...

Appendix A 8524 Counter Chip Functions 53 A.2 Counter Read/Write and Control Registers The 82C54 programmable interval timer uses four registers ataddresses BASE + 24(Dec), BASE + 26(Dec), BASE + 28(Dec) andBASE + 30(Dec) for read, write and control of counter functions.Register functions appear bel...

54 PCI-1750 User's Manual RW1 & RW0 Select read/write operation Operation RW1 RW0 Counter latch 0 0 Read/write LSB 0 1 Read/write MSB 1 0 Read/write LSB first, 1 1 then MSB M2, M1 & M0 Select operating mode M2 M1 M0 Mode Description 0 0 0 0 Stop on terminal count 0 0 1 1 Programmable one sho...

Appendix A 8524 Counter Chip Functions 55 becomes: BASE + 30(Dec) 82C54 control, read-back modeBit D7 D6 D5 D4 D3 D2 D1 D0 Value 1 1 CNT STA C2 C1 C0 X CNT = 0 Latch count of selected counter(s). STA = 0 Latch status of selected counter(s). C2, C1 & C0 Select counter for a read-back operation. C...

56 PCI-1750 User's Manual A.3 Counter Operating Modes MODE 0 – Stop on Terminal Count The output will initially be low after you set this mode of operation.After you load the count into the selected count register, the outputwill remain low and the counter will count. When the counter reachesthe ter...

Appendix A 8524 Counter Chip Functions 57 The gate input, when low, will force the output high. When the gateinput goes high, the counter will start from the initial count. You canthus use the gate input to synchronize the counter. With this mode the output will remain high until you load the countr...

58 PCI-1750 User's Manual A.4 Counter Operations Read/Write Operation Before you write the initial count to each counter, you must firstspecify the read/write operation type, operating mode and countertype in the control byte and write the control byte to the controlregister [BASE + 30(Dec)]. Since ...

Appendix A 8524 Counter Chip Functions 59 Counter Latch Operation Users often want to read the value of a counter without disturbing thecount in progress. You do this by latching the count value for thespecific counter then reading the value. The 82C54 supports the counter latch operation in two way...