Yamaha YMF724F - Manual

Yamaha YMF724F

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Table of Contents:

  • Page 2 – YMF724F; LOGOS; of virtual acoustic sound to the XG format.; and indicates GM system level 1 Compliant.
  • Page 3 – PIN CONFIGURATION; 44 Pin LQFP Top View
  • Page 4 – PIN DESCRIPTION
  • Page 6 – TYPE
  • Page 7 – BLOCK DIAGRAM
  • Page 8 – SYSTEM DIAGRAM; MMSystem
  • Page 9 – FUNCTION OVERVIEW
  • Page 10 – read from these registers are all zero.
  • Page 11 – This bit enables DS-1 to response to Memory Space Access.
  • Page 12 – Error on special cycle.
  • Page 13 – 9h: Programming Interface; Multimedia Base Class.
  • Page 15 – this ID to their Vendor ID in the BIOS POST routine.; in the BIOS POST routine.; 4h: Capability Register Pointer; Configuration register, and this register indicates “50h”.
  • Page 16 – This register is hardwired to 05h.; This register is hardwired to 19h.
  • Page 19 – MPU401 mode form default to UART, is returned.
  • Page 20 – 4-45h: Subsystem Vendor ID Write Register
  • Page 22 – includes OPL3 and SB Pro engines.; This bit controls the power state of the ADC and Input Mux in AC-2.
  • Page 23 – register without causing an error.; Master; - Set PSL0 and PSL1 bits to “1”, when DPLL0 bit is set to “1”.
  • Page 24 – This bit enables the Distributed DMA function.
  • Page 25 – 1h: Next Item Pointer; The default value is “0”.
  • Page 26 – When the power state is changed from D3
  • Page 27 – ISA Compatible Device; Basically, these registers are configured by the BIOS.
  • Page 28 – using Intel 430TX chip set is shown below.
  • Page 32 – SB Pro commands are supported.; CMD Support Function; 0h is always transferred.
  • Page 33 – The conversion for each case is described below.
  • Page 35 – from the SCAN DATA register.; This bit stops the internal state of the Sound Blaster block.
  • Page 36 – This is the data port for reading and writing the internal state.; F8h: Interrupt Flag Register
  • Page 38 – DMA Emulation Protocol
  • Page 40 – The IRQs on DS-1 are routed as shown below.; Sound Blaster Pro; ISA IRQ; INTA; can use any of the three protocols.; Digital Audio Interface
  • Page 41 – Hardware Volume Control; the external circuit listed below.; Volume, it is always reflected in the shadow register.
  • Page 42 – ELECTRICAL CHARACTERISTICS; Absolute Maximum Ratings; Recommended Operating Conditions
  • Page 43 – DC Characteristics
  • Page 44 – AC Characteristics
  • Page 45 – PCICLK
  • Page 46 – CMCLK; CMCYC; *12: This characteristic is applicable to CSYNC and CSDO signal.
  • Page 47 – CBCLK
  • Page 48 – ASCLK
  • Page 49 – EXTERNAL DIMENSIONS; The figure in the parenthesis ( ) should be used as a reference.
  • Page 50 – IMPORTANT NOTICE; AGENCY; YAMAHA CORPORATION
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YMF724F

DS-1

YAMAHA CORPORATION

September 21, 1998

Preliminary

OVERVIEW

YMF724F (DS-1) is a high performance audio controller for the PCI Bus. DS-1 consists of two separated

functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block

allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine.

The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without

utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio

provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware

accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.

Legacy Audio block supports OPL3, Sound Blaster Pro, MPU401 UART mode and Joystick function in order

to provide hardware compatibility for numerous PC games on real DOS without any software driver. To

achieve legacy DMAC compatibility on the PCI, DS-1 supports both PC/PCI and Distributed DMA protocols.

DS-1 also supports Serialized IRQ for legacy IRQ compatibility.

DS-1 supports the connection to YAMAHA YMF730 (AC-2) which provides high quality DAC, ADC and

analog mixing. In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF) output, for high-

quality, external audio amplification.

FEATURES

• PCI 2.1 Compliant

• PC’97/PC’98 specification Compliant

• PCI Bus Power Management rev. 1.0 Compliant

(Support D0, D2 and D3 state)

• PCI Bus Master for PCI Audio

True Full Duplex Playback and Capture with

different Sampling Rate

Maximum 64-voice XG capital Wavetable

Synthesizer including GM compatibility

DirectSound Hardware Acceleration

DirectMusic Hardware Acceleration

Downloadable Sound (DLS) level-1

• Legacy Audio compatibility

Genuine OPL3

Hardware Sound Blaster Pro compatibility

MPU401 UART mode MIDI interface

Joystick

• Supports PC/PCI and Distributed DMA for legacy

DMAC (8237) emulation

• Supports Serialized IRQ

• Supports YAMAHA AC-3 device (YMF727 :

AC3F2) interface to enable AC-3 decode

• Supports Consumer IEC958 Output (SPDIF) port

• Supports AC-2 Interface (AC-Link)

• Hardware Volume Control

• EEPROM Interface

• Single Crystal operation (24.576MHz)

• 5V Power supply for I/O. 3.3V Power supply for

Internal core logic

• 144-pin LQFP (YMF724F-V)

The contents of this catalog are target specifications and are subject to change

without prior notice. When using this device, please recheck the specifications.

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Summary

Page 2 - YMF724F; LOGOS; of virtual acoustic sound to the XG format.; and indicates GM system level 1 Compliant.

YMF724F September 21, 1998 -2- LOGOS 1. GM system level 1 GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements and MIDI functions. 2. XG XG is a format about MIDI synthesizer that is proposed by YAMAHA, and keeps the upper compatibility of GM system l...

Page 3 - PIN CONFIGURATION; 44 Pin LQFP Top View

YMF724F September 21, 1998 -3- PIN CONFIGURATION YMF724F-V GP4GP5GP6GP7RXDTXD ROMDO/VOLDW#ROMSK/VOLUP# VDD5VDD3 VSSVSS IRQ5IRQ7IRQ9 IRQ10IRQ11INTA# VSS RST#VDD5PVSS PCICLK GNT#REQ#AD31AD30AD29PVSSAD28AD27AD26PVSSAD25AD24 1 23456789 101112131415161718192021222324252627282930313233343536 1081071061051...

Page 4 - PIN DESCRIPTION

YMF724F September 21, 1998 -4- PIN DESCRIPTION 1. PCI Bus Interface (53-pin) name I/O Type Size function PCICLK I P PCI Clock RST# I P Reset AD[31:0] IO Ptr Address / Data C/BE[3:0]# IO Ptr Command / Byte Enable PAR IO Ptr Parity FRAME# IO Pstr Frame IRDY# IO Pstr Initiator Ready TRDY# IO Pstr Targe...

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