Page 3 - Network Interface; Driver and Receiver; Software Drivers; PIN CONFIGURATION
3 Network Interface • Integrates 10BASE-T TransceiverFunctions:- Driver and Receiver - Link Integrity Test - Receive Polarity Detection andCorrection • Integrates AUI Interface • Implements 10 Mbps ManchesterEncoding/Decoding and Clock Recovery • Automatic Retransmission, Bad PacketRejection, and Tr...
Page 5 - Single chip adapter including:
5 receive are fully independent. It has 6 kbytes ofinternal memory and the MMU managesmemory in 256 byte pages. The memory sizeaccommodates the increase in interrupt latencyresulting from simultaneous LAN and modemoperation as well as the potential forsimultaneous transmit and receive traffice insom...
Page 7 - PIN REQUIREMENTS; FUNCTION
7 PIN REQUIREMENTS FUNCTION ISA PCMCIA NUMBER OF PINS SYSTEM ADDRESS BUS A0-A15 A16A17A18A19 AEN A0-A15 nFWE nFCS nCE1 nREG 21 SYSTEM DATA BUS D0-D15 D0-D15 16 SYSTEM CONTROL BUS RESET BALE nIORD nIOWR nMEMR IOCHRDY nIOCS16 nSBHE INTR0INTR1INTR2INTR3 RESET nWE nIORD nIOWR nOE nWAIT nIOIS16 nCE2 nIRE...
Page 9 - DESCRIPTION OF PIN FUNCTIONS; NAME
9 DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL TYPE DESCRIPTION 113 nROM/ nPCMCIA I/O4 with pullup This pin is sampled at the end of RESET.When this pin is sampled low the SMC91C95is configured for PCMCIA operation and allpin definitions correspond to the PCMCIAmode. For ISA operation this pin i...
Page 18 - Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROM
18 Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROM T P E T X P T P E T X N T P E T X D P T P E T X D N T P E R X P T P E R X N T X P T X N R E C P R E C N C O L P C O L N X T A L 1 X T A L 2 E E D I E E C S E E D O E E S K IO S 0 IO S 1 IO S 2 n E N 1 6 E N E E P A E N B A L E R ...
Page 20 - Figure 3 - SMC91C95 Internal Block Diagram
20 Figure 3 - SMC91C95 Internal Block Diagram MODEM INTERFACE TWISTED PAIRTRANSCEIVER DATA BUS ADDRESS BUS CONTROL BUS INTERFACE ARBITER CSMA/CD ENDEC AUI MMU 10BASE-T RAM MANAGEMENT
Page 21 - FUNCTIONAL DESCRIPTION; Table 1 - Bus Transactions in ISA Mode
21 FUNCTIONAL DESCRIPTION The SMC91C95 consists of an integrated Ethernetcontroller mapped entirely in I/O space, as well assupport for an external Modem controller alsomapped in I/O space. In addition, PCMCIAattribute memory space is decoded to interface anexternal CIS ROM, with configuration regis...
Page 22 - Table 2 - Bus Transactions in PCMCIA Mode
22 Table 2 - Bus Transactions in PCMCIA Mode A0 nCE1 nCE2 D0-D7 D8-D15 8 BIT MODE ((IOis8=1) + (nEN16=1).(16BIT=0)) 0 0 X even byte - 1 0 X odd byte - X 1 X NO CYCLE 16 BIT MODE 0 0 0 even byte odd byte otherwise 0 0 1 even byte - 1 0 1 odd byte X 1 0 - odd byte X 1 1 NO CYCLE 16BIT = CONFIGURATION ...
Page 24 - BUFFER MEMORY; RAM size
24 The internal DMA interface can arbitrate for RAMaccess and request memory from the MMU whennecessary. An encoder/decoder block interfaces theCSMA/CD block on the serial side. The encoderwill do the Manchester encoding of the transmitdata at 10 Mbps, while the decoder will recover thereceive clock...
Page 25 - FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA
25 FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA PAGE = 256 bytes PHYSICAL MEMORY TX PACKET NUMBER RX PACKET NUMBER MMU MMU 2K TX AREA 2K RX AREA 11-BIT LOGICAL ADDRESS POINTER REGISTER RCV BIT RCV VS. TX AREA SELECTION
Page 26 - FIGURE 5 - TRANSMIT QUEUES AND MAPPING; TX FIFO
26 FIGURE 5 - TRANSMIT QUEUES AND MAPPING B A B C STATUS COUNT DATA STATUS COUNT DATA PACKET #A PACKET #B PACKET NUMBER REGISTER TX FIFO TO CSMA LINEAR ADDRESS MMU MAPPING MEMORY CPU SIDE STATUS COUNT DATA PACKET #C TX COMPLETION FIFO FIFO PORTS REGISTER C
Page 27 - FIGURE 6 - RECEIVE QUEUE AND MAPPING
27 FIGURE 6 - RECEIVE QUEUE AND MAPPING D E D E STATUS COUNT DATA STATUS COUNT DATA PACKET #D PACKET #E FIFO PORTS REGISTER RX FIFO FROM CSMA LINEAR ADDRESS MMU MAPPING MEMORY CPU SIDE
Page 28 - FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH
28 FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH B U S I N T E R F A C E A R B IT E R M M U B U F F E R R A M C S M A /C D E N D E C T W IS T E D P A IR T R A N S C E IV E R A U I 1 0 B A S E T D A T A B U S A D D R E S S B U S C O N T R O L E E P R O M E E P R O M W R IT E D A T A R E G...
Page 29 - STATUS WORD
29 PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for theTRANSMIT and RECEIVE areas. The firstword is reserved for the status word, the next word is used to specify the total number ofbytes, and that in turn is followed by the dataarea. The data area holds the packet itself, a...
Page 36 - Internal VS External Attribute Memory Map
36 Internal VS External Attribute Memory Map The Internal VS External EPROM attributememory decodes are shown below. This allowsthe designer to not require an external EPROMdevice if the single or multi-function PCMCIA cardneeds less than 512 bytes of configurationinformation. As can be seen in the ...
Page 37 - HIGH
37 I/O SPACE(ISA and PCMCIA Mode) In ISA mode, the base I/O space is determined bythe IOS0-IOS2 inputs and the EEPROM contents.A4-A15 are compared against the base I/Oaddress for I/O space accesses. In PCMCIA mode nREG (along with nIORD ornIOWR) defines an I/O access regardless of theA4-A15 value. T...
Page 54 - PCMCIA EEPROM to SRAM Memory Map
54 CR ENABLE - Counter Roll over Enable. Whenset it enables the CTR_ROL bit as one of theinterrupts merged into the EPH INT bit. Defaultslow (disabled). TE ENABLE - Transmit Error Enable. When set itenables Transmit Error as one of the interruptsmerged into the EPH INT bit. Defaults low(disabled). T...
Page 57 - COMMAND SEQUENCING
57 110 6) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting apacket just loaded into RAM. The packet number to be enqueued is taken from the PACKETNUMBER REGISTER. 111 7) RESET TX FIFOs - This command will reset both TX FIFOs: the TX FIFO holding the packetnumbers awaiti...
Page 64 - FIGURE 9 - INTERRUPT STRUCTURE
64 FIGURE 9 - INTERRUPT STRUCTURE 5 4 3 2 1 0 5 4 3 2 1 0 IN T E R R U P T S T A T U S R E G IS T E R IN T E R R U P T M A S K R E G IS T E R O E n O E n R D IS T 1 6 D A T A B U S D 0 -7 D 8 -1 5 E D G E D E T E C T O R O N L IN K E R R L E M A S K C T R -R O L C R M A S K T E M A S K T X E N A T X...
Page 69 - THEORY OF OPERATION; MEMORY ARCHITECTURE; Full Duplex mode for diagnostic purposes
69 THEORY OF OPERATION PC Card 5.0 treats the individual functions of amultifunction PCMCIA applicationindependently. Card and Socket Services(C&SS) 5.0 is designed to provide the supportfor determining the function generating theinterrupt and informing relevant drivers. Theregisters for the two...
Page 70 - Behavior in FDSE Mode; collisions in a switched environment.; “Magic Packet” Support
70 2. FDSE (Full Duplex Switched Ethernet). Enabled by FDSE bit in TCR bit. When theSMC91C95 is configured for FDSE, itstransmit and receive paths will operateindependently and some CSMA/CDfunctions are disabled such as CarrierSense. Behavior in FDSE Mode The main 802.3 section affected by FDSE is4....
Page 71 - TYPICAL FLOW OF EVENTS FOR TRANSMIT
71 TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER CSMA/CD SIDE 1 ISSUE ALLOCATE MEMORY FOR TX - NBYTES - the MMU attempts to allocate Nbytes of RAM. 2 WAIT FOR SUCCESSFUL COMPLETIONCODE - Poll until the ALLOC INT bit is set orenable its mask bit and wait for the interrupt.The TX packet number is now...
Page 72 - TYPICAL FLOW OF EVENTS FOR RECEIVE
72 TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER CSMA/CD SIDE 1 ENABLE RECEPTION - By setting the RXENbit. 2 A packet is received with matching address.Memory is requested from MMU. A packetnumber is assigned to it. Additional memory isrequested if more pages are needed. 3 The internal DMA logic gen...
Page 73 - FIGURE 10 - ETHERNET INTERRUPT SERVICE ROUTINE
73 FIGURE 10 - ETHERNET INTERRUPT SERVICE ROUTINE ISR Save Bank Select & Address Ptr Registers Mask 91C94 Interrupts Read Interrupt Register Call TX INTR or TXEMPTY INTR TX INTR? Get Next TX RX INTR? Yes No No Yes Call RXINTR ALLOC INTR? No Yes Write Allocated Pkt # into Packet Number Reg. Write...
Page 77 - FIGURE 14 - TXEMPTY INTR
77 FIGURE 14 - TXEMPTY INTR T X E M P T Y I N T R W r i t e A c k n o w l e d g e R e g . w i t h T X E M P T Y B i t S e t R e a d T X E M P T Y & T X I N T R A c k n o w l e d g e T X I N T R R e - E n a b l e T X E N A R e t u r n t o I S R I s s u e " R e l e a s e " C o m m a n d R ...
Page 78 - FIGURE 15 - DRIVER SEND AND ALLOCATE ROUTINES
78 FIGURE 15 - DRIVER SEND AND ALLOCATE ROUTINES ALLOCATE Issue "Allocate Memory" Command to MMU Read Interrupt Status Register Enqueue Packet Set "Ready for Packet" Flag Return Copy Remaining TX Data Packet into RAM Return Buffers to Upper Layer Write Allocated Packet into Packet # ...
Page 80 - One interrupt per sequence of packets:
80 TX INT bit - Set whenever the TX completionFIFO is not empty. TX EMPTY INT bit - Set whenever the TXFIFO is empty.AUTO RELEASE - When set, successfultransmit packets are not written intocompletion FIFO, and their memory isreleased automatically. 1) One interrupt per packet: enable TX INT, set AUT...
Page 82 - PCMCIA CONFIGURATION REGISTERS DESCRIPTION; For
82 PCMCIA CONFIGURATION REGISTERS DESCRIPTION Ethernet Function (Base Address 8000h) 8000h - Ethernet Configuration Option Register (ECOR) 7 6 5 4 3 2 1 0 SRESET LevIREQ WRATTRI B Enable IREQ Enable Base and Limit Enable Function 0 1 0 0 0 0 0 0 BIT 7 - SRESET: This bit when set will clear allintern...
Page 87 - CURRENT VALUE
87 8024h - Pin Replacement Register (PRR) 7 6 5 4 3 2 1 0 Cready/- Bsy Rready/- Bsy 0 0 0 0 0 0 1 0 Cready/-Bsy: This bit is set to a one when thebit Rready/-Bsy bit changes state from zero(0)to one(1) or one(1) to zero(0) with the source ofthe change of state is a change in the modemready (MRDY) si...
Page 91 - FUNCTIONAL DESCRIPTION OF THE BLOCKS; MEMORY MANAGEMENT UNIT
91 FUNCTIONAL DESCRIPTION OF THE BLOCKS MEMORY MANAGEMENT UNIT The MMU interfaces the on-chip RAM on oneside and the arbiter on the other for addressand data flow purposes. For allocation and de-allocation, it interfaces the arbiter only. The MMU deals with a single ported memoryand is not aware of ...
Page 93 - DMA BLOCK; Its functions include the following:
93 write cycle starts and there is more than twobytes in the write FIFO. The cycle time is defined as the time betweenleading edges of read from the Data Register,or equivalently between trailing edges of writeto the Data Register. For example, in an ISAsystem the cycle time of a 16 bit transfer wil...
Page 94 - PACKET NUMBER FIFOS
94 Packets with bad CRC can be received ifthe RCV_BAD bit in the configurationregister is set. 5) If AUTO_RELEASE is set, a release isissued by the DMA block to the MMU aftera successful transmission (TX_SUCC set),and the TX completion FIFO is clockedtogether with the TX FIFO preventing thepacket nu...
Page 95 - FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS
95 FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS T X F IF O C O M P L E T IO N F IF O R X F IF O C S M A /C D L O G IC A L A D D R E S S P A C K E T # M M U P H Y S IC A L A D D R E S S R A M C P U A D D R E S S C S M A A D D R E S S R X P A C K E T N U M B E R R X F IF O P A C K E T N U...
Page 96 - CSMA BLOCK; a) 16 collisions on same frame (half duplex
96 CSMA BLOCK The CSMA/CD block is first interfaced via itscontrol registers in order to define itsoperational configuration. From then on, theDMA interface between the CSMA/CD blockand memory is used to transfer data to and fromits data path interface. For transmit, the CSMA/CD block will be askedt...
Page 97 - NETWORK INTERFACE; Diagnostic loopback capability.; AUI
97 Only when 16 retries are reached, theCSMA/CD block will clear the TXENA bit, andCPU intervention is required. The DMA will notautomatically restart data transfer in this case,nor will it transmit the next enqueued packetuntil TXENA is set by the CPU. The DMA willmove the packet number in question...
Page 100 - Base Register
100 BOARD SETUP INFORMATION ISA MODE The following parameters are obtained from theEEPROM as board setup information: ETHERNET INDIVIDUAL ADDRESSI/O BASE ADDRESSROM BASE ADDRESS8/16 BIT ADAPTER10BASE-T or AUI INTERFACEINTERRUPT LINE SELECTION All the above mentioned values are read fromthe EEPROM up...
Page 101 - DIAGNOSTIC LEDs; nLINKLED - Reflects the link integrity status.; ARBITRATION CONSIDERATIONS
101 REGISTER are written in the EEPROMlocations defined by the IOS2-0 pins. The three least significant bits of the CONTROLREGISTER (EEPROM SELECT, RELOAD andSTORE) are used to control the EEPROM.Their values are not stored nor loaded from theEEPROM. b) GENERAL PURPOSE REGISTER -EEPROM SELECT bit = ...
Page 103 - FIGURE 17 - 64 X 16 SERIAL EEPROM MAP FOR ISA MODE
103 FIGURE 17 - 64 X 16 SERIAL EEPROM MAP FOR ISA MODE C O N F I G U R AT I O N R E G . B A S E R E G . C O N F I G U R AT I O N R E G . B A S E R E G . C O N F I G U R AT I O N R E G . B A S E R E G . C O N F I G U R AT I O N R E G . B A S E R E G . C O N F I G U R AT I O N R E G . B A S E R E G . ...
Page 104 - OPERATIONAL DESCRIPTION
104 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ...................................................................................... 0 o C to +70 o C Storage Temperature Range ....................................................................................-5...
Page 108 - TIMING DIAGRAMS; FIGURE 18 - PCMCIA MEMORY READ TIMING
108 TIMING DIAGRAMS FIGURE 18 - PCMCIA MEMORY READ TIMING A[5:0], nREG nCE1 nOE D[15:0] DATA VALID t1 t2 t3 t4 t5 t6 0 min 30 max 5 max Parameter Min Typ Max Units t1 Address Access Time 300 ns t2 nREG Access Time 300 ns t3 nCE1 Access Time 300 ns t4 nOE Access Time 150 ns t5 Output Disable Time fro...
Page 109 - FIGURE 19 - PCMCIA MEMORY WRITE TIMING
109 FIGURE 19 - PCMCIA MEMORY WRITE TIMING A[5:0], nREG nCE1 nWE D[15:0 (Din)] 250 min t4 t1 t5 0 min t2 Parameter Min Typ Max Units t1 nWE Pulse Width 150 ns t2 Address/nREG Setup Time to nWE Low 30 ns t3 Address/nREG Setup Time to nWE High 180 ns t4 nCE1 Low to nWE High Setup Time 180 ns t5 Data t...
Page 115 - FIGURE 23 - PCMCIA CONSECUTIVE READ CYCLES; Parameter; valid
115 FIGURE 23 - PCMCIA CONSECUTIVE READ CYCLES nsnsnsnsnsnsnsnsns 35 40 055 185 0 152515 0 Parameter t46t47t48t20t49t50t51t52t53 nIORD Delay tonREG Low to ControlnCE1,nCE2 Setup to ControlCycle Time (No WaitnREG Hold after ControlnCE1,nCE2 Hold after ControlAddress Setup to ControlAddress Hold after...
Page 116 - FIGURE 24 - CONSECUTIVE PCMCIA WRITE CYCLES
116 FIGURE 24 - CONSECUTIVE PCMCIA WRITE CYCLES 5 5 0 15 25 15 185 30 9 t51 t52 t47 t49 t48 t50 t20 t54 t55 valid valid A0-9,A15 nREG nCE1,nCE2 nIOWR D0-15 t47 t48 t49 t50 t51 t52 t20 t54 t55 ns ns ns ns ns ns ns ns ns nREG Low Setup to Control Active nCE1,nCE2 Setup to Control Active nREG Hold afte...
Page 119 - FIGURE 27 - ISA CONSECUTIVE READ CYCLES
119 FIGURE 27 - ISA CONSECUTIVE READ CYCLES B A L E T i e d H i g h V A L I D A D D R E S S V A L I D A D D R E S S V A L I D D A T A O U T V A L I D D A T A O U T t15 t4 t3 t20 t5 t6 Z Z A 0 - 1 5A E N , n S B H E n I O C S 1 6 n I O R D D 0 - 1 5 t3 t4 t5 t6 t15 t20 A d d r e s s , n S B H E , A E...
Page 120 - FIGURE 28 - ISA CONSECUTIVE WRITE CYCLES
120 FIGURE 28 - ISA CONSECUTIVE WRITE CYCLES VALID ADDRESS VALID ADDRESS t15 t4 t3 t20 A0-15AEN, nSBHE nIOCS16 nIOWR D0-15 VALID DATA IN VALID DATA t7 t8 BALE Tied High t3 t4 t7 t8 t15 t20 25 ns ns ns ns ns ns Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactiv...
Page 121 - FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLES
121 FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLES t20 A0-15 AEN,nSBHE nIOCS16 nIOWR D0-D15 VALID ADDRESS VALID ADDRESS nIORD t9 t10 Z Z Z VALID DATA VALID DATA IOCHRDY Z Z Control Active to IOCHRDY Low IOCHRDY Low Pulse Width* Cycle time** Parameter min typ max units 100 185 15 150 ns ns ns t9 t...
Page 122 - FIGURE 30 - DATA REGISTER SPECIAL READ ACCESS
122 FIGURE 30 - DATA REGISTER SPECIAL READ ACCESS A0-15 (ISA)AEN,nSBHE nIOCS16 D0-D15 nIORD VALID DATA VALID ADDRESS IOCHRDY OUT t9 t18 t19 Z Z Parameter min typ max units 15 575 225 ns ns ns t9 t18 t19 Control Active to IOCHRDY Low IOCHRDY Width when Data is Unavailable at Data Register Valid Data ...
Page 123 - FIGURE 31 - DATA REGISTER SPECIAL WRITE ACCESS
123 FIGURE 31 - DATA REGISTER SPECIAL WRITE ACCESS nIOCS16 D0-D15 VALID ADDRESS A0-15 (ISA)AEN,nSBHE nIOWR VALID DATA IN IOCHRDY t18 Z Z Parameter min typ max units 15 425 t9 t18 Control Active to IOCHRDY Low IOCHRDY Width when Data Register is Full IOCHRDY is used instead of meeting t20 and t44. 'N...
Page 124 - FIGURE 33 - EXTERNAL ROM READ ACCESS
124 FIGURE 32 - 8-BIT MODE REGISTER CYCLES FIGURE 33 - EXTERNAL ROM READ ACCESS A0-15(ISA)AEN nIORD D0-7 nIOWR t3 t3 t5 Z VALID DATA OUT Z VALID DATA IN t7 t8 VALID ADDRESS t3t5t7t8 Address, nSBHE, AEN Setup to Control ActivenIORD Low to Valid DataData Setup to nIOWR RisingData Hold after nIOWR Risi...
Page 125 - FIGURE 34 - ISA REGISTER ACCESS WHEN USING BALE
125 FIGURE 34 - ISA REGISTER ACCESS WHEN USING BALE A E N n I O C S 1 6 A0-15,n S B H E n I O R D B A L E n I O W R t4 V A L I D t1 t2 t15 t3 t1 t2 t3 t4 t15 A d d r e s s , n S B H E S e t u p t o B A L E F a l l i n g Address, nSBHE Hold after BALE Falling A d d r e s s , n S B H E , A E N S e t u...
Page 126 - FIGURE 35 - EXTERNAL ROM READ ACCESS USING BALE
126 FIGURE 35 - EXTERNAL ROM READ ACCESS USING BALE A d d r e s s S e t u p t o B A L E F a l l i n g A d d r e s s H o l d a f t e r B A L E F a l l i n g A d d r e s s S e t u p t o C o n t r o l A c t i v e n M E M R D L o w t o n R O M L o w n M E M R D H i g h t o n R O M H i g h n M E M R D A ...
Page 127 - FIGURE 36 - EEPROM READ
127 FIGURE 36 - EEPROM READ EEDI EESK EEDO EECS EESK Falling to EEDO, EECS Changing t21 Parameter min typ max units 100 ns t21 t21 0 9346 is typically the serial EEPROM used.
Page 128 - FIGURE 37 - EEPROM WRITE
128 FIGURE 37 - EEPROM WRITE E E S K E E D O E E D I E E C S E E S K F a l l i n g t o E E D O , E E C S C h a n g i n g t21 P a r a m e t e r m i n typ m a x units 100 n s t21 t21 9346 is typically the serial EEPROM used.
Page 136 - FIGURE 47 - VTQFP PACKAGE OUTLINE
136 0 H d D H e E e b 0 . 0 8 ( 0 . 0 0 3 ) M A 2 A 1 Y c L 1 L 0 . 2 5 G A G E P L A N E S Y M B O L M I L L I M E T E R I N C H M I N . N O M . M A X . M I N . N O M . M A X . 0 . 0 5 0 . 9 5 0 . 1 3 0 . 0 9 1 3 . 9 0 1 3 . 9 0 1 5 . 9 0 1 5 . 9 0 0 . 4 5 0 0 . 1 0 1 . 0 0 0 . 1 8 1 4 . 0 0 1 4 . ...
