LSI Logic 53C875A - Manual

Contents vii Contents Chapter 1 General Description 1.1 New Features in the LSI53C875A 1-3 1.2 Benefits of Ultra SCSI 1-3 1.3 TolerANT ® Technology 1-4 1.4 LSI53C875A Benefits Summary 1-4 1.4.1 SCSI Performance 1-5 1.4.2 PCI Performance 1-6 1.4.3 Integration 1-6 1.4.4 Ease of Use 1-6 1.4.5 Flexibili...

viii Contents 2.2.11 Parity Options 2-24 2.2.12 DMA FIFO 2-27 2.2.13 SCSI Bus Interface 2-32 2.2.14 Select/Reselect During Selection/Reselection 2-33 2.2.15 Synchronous Operation 2-34 2.2.16 Interrupt Handling 2-37 2.2.17 Chained Block Moves 2-44 2.3 Parallel ROM Interface 2-48 2.4 Serial EEPROM Int...

x Contents 6.3 AC Characteristics 6-9 6.4 PCI and External Memory Interface Timing Diagrams 6-11 6.4.1 Target Timing 6-13 6.4.2 Initiator Timing 6-19 6.4.3 External Memory Timing 6-35 6.5 SCSI Timing Diagrams 6-52 6.6 Package Diagrams 6-58 Appendix A Register Summary Appendix B External Memory Inter...

xii Contents B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 MbyteInterface with 150 ns Memory B-3 B.4 512 Kbyte Interface with 150 ns Memory B-4 Tables 2.1 PCI Bus Commands and Encoding Types for theLSI53C875A 2-4 2.2 PCI Cache Mode Alignment 2-12 2.3 Bits Used for Parity Control and Generation 2-25 2...

LSI53C875A PCI to Ultra SCSI Controller 1-1 Chapter 1General Description Chapter 1 is divided into the following sections: • Section 1.1, “New Features in the LSI53C875A” • Section 1.2, “Benefits of Ultra SCSI” • Section 1.3, “TolerANT ® Technology” • Section 1.4, “LSI53C875A Benefits Summary” The L...

1-2 General Description Figure 1.1 Typical LSI53C875A System Application Figure 1.2 Typical LSI53C875A Board Application PCI Bus Interface Controller LSI53C875A PCI to Wide Ultra SCSI Controller PCI Graphic Accelerator PCI Fast Ethernet Memory Controller Memory Fixed Disk, Optical Disk Printer, Tape...

New Features in the LSI53C875A 1-3 1.1 New Features in the LSI53C875A The LSI53C875A is a drop-in replacement for the LSI53C875 PCI toUltra SCSI Controller, with these additional benefits: • Supports 32-bit PCI Interface with 64-bit addressing. • Handles SCSI phase mismatches in SCRIPTS without inte...

1-4 General Description synchronous negotiations for Ultra SCSI rates and to enable the clockquadrupler. Chapter 2, “Functional Description,” contains more information on Ultra SCSI design. 1.3 TolerANT ® Technology The LSI53C875A features TolerANT technology, which includes activenegation on the SC...

LSI53C875A PCI to Ultra SCSI Controller 2-1 Chapter 2Functional Description Chapter 2 is divided into the following sections: • Section 2.1, “PCI Functional Description” • Section 2.2, “SCSI Functional Description” • Section 2.3, “Parallel ROM Interface” • Section 2.4, “Serial EEPROM Interface” • Se...

2-2 Functional Description Figure 2.1 LSI53C875A Block Diagram 2.1 PCI Functional Description The LSI53C875A implements a PCI-to-Wide Ultra SCSI controller. 2.1.1 PCI Addressing There are three physical PCI-defined address spaces: • PCI Configuration space. • I/O space for operating registers. • Mem...

PCI Functional Description 2-3 2.1.1.1 Configuration Space The host processor uses the PCI configuration space to initialize theLSI53C875A through a defined set of configuration space registers. TheConfiguration registers are accessible only by system BIOS during PCIconfiguration cycles. The configu...

2-4 Functional Description 2.1.2.1 Interrupt Acknowledge Command The LSI53C875A does not respond to this command as a slave and itnever generates this command as a master. 2.1.2.2 Special Cycle Command The LSI53C875A does not respond to this command as a slave and itnever generates this command as a...

2-6 Functional Description 2.1.2.10 Memory Read Multiple Command This command is identical to the Memory Read command except that itadditionally indicates that the master may intend to fetch more than onecache line before disconnecting. The LSI53C875A supports PCI MemoryRead Multiple functionality a...

PCI Functional Description 2-7 line. This command is intended for use with bulk sequential data transferswhere the memory system and the requesting master might gain someperformance advantage by reading to a cache line boundary rather thana single memory cycle. The Read Line function in the LSI53C87...

2-10 Functional Description software enabled or disabled to allow the user full flexibility in using thesecommands. 2.1.3.1 Enabling Cache Mode In order to enable the cache logic to issue PCI cache commands(Memory Read Line, Memory Read Multiple, and Memory Write andInvalidate) on any given PCI mast...

PCI Functional Description 2-11 • To issue Memory Read Multiple commands, the Read Multipleenable bit in the DMA Mode (DMODE) register must be set. • To issue Memory Write and Invalidate commands, both the Write andInvalidate enables in the Chip Test Three (CTEST3) register and the PCI configuration...

2-12 Functional Description • Multiple Memory Write and Invalidates. • A single data residual Memory Write to complete the transfer. Table 2.2 describes PCI cache mode alignment. Table 2.2 PCI Cache Mode Alignment Host Memory A 00h B 04h 08h C 0Ch D 10h 14h 18h 1Ch E 20h 24h 28h 2Ch F 30h 34h 38h 3C...

PCI Functional Description 2-13 2.1.3.5 Examples: MR = Memory Read, MRL = Memory Read Line, MRM = Memory ReadMultiple, MW = Memory Write, MWI = Memory Write and Invalidate. Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A...

2-14 Functional Description Read Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: C to E: MRM (21 bytes) D to F: MRM (31 bytes)MR (1 byte) A to H: MRM (31 bytes)MRM (32 bytes)MRM (18 bytes) A to G: MRM (31 bytes)MRM (32 bytes)...

PCI Functional Description 2-15 Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: D to F: MW (15 bytes)MWI (16 bytes)MW (1 byte) A to H: MW (15 bytes)MWI (16 bytes)MWI (16 bytes)MWI (16 bytes)MWI (16 bytes)MW (2 bytes) A to G: MW (15 bytes)MWI (16 bytes)MWI (16 bytes)MWI (16 bytes)MW (...

2-16 Functional Description Write Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: 2.1.3.6 Memory-to-Memory Moves Memory-to-Memory Moves also support PCI cache commands, asdescribed above, with one limitation. Memory Write and Invalidate onMemory-to-Memory Move writes are only supported if...

SCSI Functional Description 2-17 accessed as a register-oriented device. Error recovery and/or diagnosticprocedures use the ability to sample and/or assert any signal on theSCSI bus. In support of SCSI loopback diagnostics, the SCSI core mayperform a self-selection and operate as both an initiator a...

2-18 Functional Description The Phase Mismatch Jump logic powers up disabled and must beenabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, bit 7in the Chip Control 0 (CCNTL0) register). Utilizing the information supplied in the Phase Mismatch Jump Address 1 (PMJAD1) and Phase Mismatch Jum...

SCSI Functional Description 2-19 2.2.3 64-Bit Addressing in SCRIPTS The LSI53C875A has a 32-bit PCI interface which provides 64-bitaddress capability in the initiator mode. DACs can be generated for all SCRIPTS operations. There are sixselector registers which hold the upper Dword of a 64-bit addres...

2-20 Functional Description 2.2.5 Designing an Ultra SCSI System Since Ultra SCSI is based on existing SCSI standards, it can use existingdriver programs as long as the software is able to negotiate for UltraSCSI synchronous transfer rates. Additional software modifications areneeded to take advanta...

SCSI Functional Description 2-21 Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit ( SCSI Test Three (STEST3) , bit 5). Step 4. Set the clock conversion factor using the SCF and CCF fieldsin the SCSI Control Three (SCNTL3) register. Step 5. Set the SCLK Quadrupler Select bit ( SCSI Test...

SCSI Functional Description 2-23 Load and Store instructions, refer to Chapter 5, “SCSI SCRIPTS Instruction Set.” 2.2.9 JTAG Boundary Scan Testing The LSI53C875A includes support for JTAG boundary scan testing inaccordance with the IEEE 1149.1 specification with one exception, whichis explained in t...

2-24 Functional Description 2.2.11 Parity Options The LSI53C875A implements a flexible parity scheme that allows controlof the parity sense, allows parity checking to be turned on or off, and hasthe ability to deliberately send a byte with bad parity over the SCSI busto test parity error recovery pr...

SCSI Functional Description 2-25 Table 2.3 Bits Used for Parity Control and Generation Bit Name Location Description Assert SATN/ onParity Errors SCSI Control Zero(SCNTL0) , Bit 1 Causes the LSI53C875A to automatically assert SATN/when it detects a SCSI parity error while operating as aninitiator. E...

2-26 Functional Description Table 2.4 SCSI Parity Control EPC 1 1. EPC = Enable Parity Checking (bit 3 SCSI Control Zero (SCNTL0) ). ASEP 2 2. ASEP = Assert SCSI Even Parity (bit 2 SCSI Control One (SCNTL1) ). Description 0 0 Does not check for parity errors. Parity is generated when sendingSCSI dat...

SCSI Functional Description 2-27 Figure 2.2 Parity Checking/Generation 2.2.12 DMA FIFO The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO isillustrated in Figure 2.3 . The default DMA FIFO size is 112 bytes to assure compatibility with older products in the LSI53C8XX family. The DMA FI...

2-28 Functional Description Figure 2.3 DMA FIFO Sections The LSI53C875A automatically supports misaligned DMA transfers. A944-byte FIFO allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or128 Dword bursts across the PCI bus interface. 2.2.12.1 Data Paths The data path through the LSI53C875A is d...

SCSI Functional Description 2-29 Figure 2.4 LSI53C875A Host Interface SCSI Data Paths The following steps determine if any bytes remain in the data path whenthe chip halts an operation: Asynchronous SCSI Send – Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test Five (CTEST5) re...

2-30 Functional Description bits of the DBC register from the 10-bit value of the DMA FIFOByte Offset Counter, which consists of bits [1:0] in the CTEST5register and bits [7:0] of the DMA FIFO register. AND the resultwith 0x3FF for a byte count between zero and 944. Step 2. Read bit 5 in the SCSI St...

SCSI Functional Description 2-31 then the least significant byte or the most significant byte in theSODR register is full, respectively. Asynchronous SCSI Receive – Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test Five (CTEST5) register cleared), look at the DMA FIFO (DFIFO) ...

SCSI Functional Description 2-33 Figure 2.5 Regulated Termination for Ultra SCSI 2.2.14 Select/Reselect During Selection/Reselection In multithreaded SCSI I/O environments, it is not uncommon to beselected or reselected while trying to perform selection/reselection. This TERML1TERML2TERML3TERML4TERM...

2-34 Functional Description situation may occur when a SCSI controller (operating in the initiatormode) tries to select a target and is reselected by another. The SelectSCRIPTS instruction has an alternate address to which the SCRIPTS willjump when this situation occurs. The analogous situation for ...

SCSI Functional Description 2-35 Figure 2.6 Determining the Synchronous Transfer Rate SCLK Clock Quadrupler QCLK SCF Divider CCF Divider Synchronous Divider Asynchronous SCSI Logic Divide by 4 SCF2 SCF1 SCF0 SCF Divisor 0 0 1 1 0 1 0 1.5 0 1 1 2 1 0 0 3 0 0 0 3 1 0 1 4 1 1 0 6 1 1 1 8 TP2 TP1 TP0 XF...

2-36 Functional Description 2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0]) The SCF[2:0] bits select the factor by which the frequency of SCLK isdivided before being presented to the synchronous SCSI control logic.The output from this divider controls the rate at which data can ...

SCSI Functional Description 2-37 • Ultra SCSI Enable bit, SCSI Control Three (SCNTL3) register bit 7. Setting this bit enables Ultra SCSI synchronous transfers in systemsthat use the internal SCSI clock quadrupler. • TolerANT Enable bit, SCSI Test Three (STEST3) register bit 7. Active negation must ...

2-38 Functional Description polled when polled interrupts are used. It is also the first register thatshould be read after the IRQ/ pin is asserted in association with ahardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the firstinterrupt serviced. It must be written to one to be clea...

SCSI Functional Description 2-39 conditions caused the DMA-type interrupt, and clears that DMA interruptcondition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generatean interrupt under any circumstances and will not be cleared when read.DMA interrupts flush neither the DMA nor SCSI FIF...

2-40 Functional Description Purpose Timer Expired (GEN), and Handshake-to-Handshake TimerExpired (HTH) interrupts are nonfatal. When operating in the Target mode, CMP, SEL, RSL, Target mode:SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the descriptionfor the Disable Halt on a Parity Error ...

SCSI Functional Description 2-41 Interrupts can be disabled by setting SYNC_IRQD bit 0 in the Interrupt Status One (ISTAT1) register. If an interrupt is already asserted and SYNC_IRQD is then set, the interrupt will remain asserted until serviced. At this point, the IRQ/ pin is blocked for future in...

2-42 Functional Description generates an interrupt, the bit corresponding to the earlier maskednonfatal interrupt is still set. A related situation to interrupt stacking is when two interrupts occursimultaneously. Since stacking does not occur until the SIP or DIP bitsare set, there is a small timin...

SCSI Functional Description 2-43 • If the instruction is a JUMP/CALL WHEN/IF <phase>, the DMA SCRIPTS Pointer (DSP) is updated to the transfer address before halting. • All other instructions may halt before completion. 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an ...

2-44 Functional Description 2.2.17 Chained Block Moves Since the LSI53C875A has the capability to transfer 16-bit wide SCSIdata, a unique situation occurs when dealing with odd bytes. TheChained Move (CHMOV) SCRIPTS instruction along with the Wide SCSISend (WSS) and Wide SCSI Receive (WSR) bits in t...

SCSI Functional Description 2-45 Figure 2.7 Block Move and Chained Block Move Instructions 2.2.17.1 Wide SCSI Send Bit The WSS bit is set whenever the SCSI controller is sending data(Data-Out for initiator or Data-In for target) and the controller detects apartial transfer at the end of a chained Bl...

2-46 Functional Description two bytes are sent out across the bus, regardless of the type of BlockMove instruction (normal or chained). The flag is automatically clearedwhen the “married” word is sent. The flag is alternately cleared throughSCRIPTS or by the microprocessor. Also, the microprocessor ...

SCSI Functional Description 2-47 2.2.17.5 Chained Block Move SCRIPTS Instruction A chained Block Move SCRIPTS instruction is primarily used to transferconsecutive data send or data receive blocks. Using the chained BlockMove instruction facilitates par tial receive transfers and allows correctpartia...

2-48 Functional Description send command, the first byte of the data send command is assumed tobe the high-order byte and is “married” with the low-order byte stored inthe lower byte of the SCSI Output Data Latch (SODL) register before the two bytes are sent across the SCSI bus. For “N” consecutive ...

Parallel ROM Interface 2-49 The LSI53C875A supports a variety of sizes and speeds of expansionROM, using pull-down resistors on the MAD[3:0] pins. The encoding ofpins MAD[3:1] allows the user to define how much external memory isavailable to the LSI53C875A. Table 2.6 shows the memory space associate...

2-50 Functional Description 2.4 Serial EEPROM Interface The LSI53C875A implements an interface that allows attachment of aserial EEPROM device to the GPIO0 and GPIO1 pins. There are twomodes of operation relating to the serial EEPROM and the SubsystemID and Subsystem Vendor ID registers. These modes...

Power Management 2-51 2.4.2 No Download Mode When MAD7 is pulled up through an external resistor, the automaticdownload is disabled and no data is automatically loaded into chipregisters at power-up. The Subsystem ID and Subsystem Vendor IDregisters are read only, per the PCI specification, with a d...

2-52 Functional Description The LSI53C875A power states shown in Table 2.8 are independently controlled through two power state bits that are located in the PCI Power Management Control/Status (PMCSR) register 0x44. Although the PCI Bus Power Management Interface Specification doesnot allow power st...

Power Management 2-53 2.5.3 Power State D2 Power state D2 is a lower power state than D1. In this state theLSI53C875A core is placed in the coma mode. The following PCIConfiguration Space command register enable bits are suppressed: • I/O Space Enable • Memory Space Enable • Bus Mastering Enable • S...

LSI53C875A PCI to Ultra SCSI Controller 3-1 Chapter 3Signal Descriptions This chapter presents the LSI53C875A pin configuration and signaldefinitions using tables and illustrations. This chapter contains thefollowing sections: • Section 3.1, “LSI53C875A Functional Signal Grouping” • Section 3.2, “Si...

3-2 Signal Descriptions 3.1 LSI53C875A Functional Signal Grouping Figure 3.1 presents the LSI53C875A signals by functional group. Figure 3.1 LSI53C875A Functional Signal Grouping LSI53C875A CLKRST/ AD[31:0]C_BE[3:0]/PAR FRAME/TRDY/IRDY/STOP/DEVSEL/IDSEL REQ/GNT/ PERR/SERR/ IRQ/ GPIO0_FETCH/GPIO1_MAS...

Signal Descriptions 3-3 3.2 Signal Descriptions The Signal Descriptions are divided into PCI Bus Interface Signals , SCSI Bus Interface Signals , GPIO Signals, ROM Flash and Memory Interface Signals , Test Interface Signals , and Power and Ground Signals . The PCI Bus Interface Signals are subdivide...

3-4 Signal Descriptions 3.3 PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing thesignals for the following signal groups: System Signals , Address and Data Signals , Interface Control Signals , Arbitration Signals , Error Reporting Signals , and Interrupt Sig...

PCI Bus Interface Signals 3-5 3.3.2 Address and Data Signals Table 3.3 describes Address and Data signals. Table 3.3 Address and Data Signals Name PQFP BGA Type Strength Description AD[31:0] 150, 151,153, 154,156, 157,159, 160, 3,5, 6, 7, 9,11–13, 28–30, 32, 34–36, 38, 40,41, 43, 44,46, 47, 49,50 B5...

3-6 Signal Descriptions 3.3.3 Interface Control Signals Table 3.4 describes the Interface Control signals. Table 3.4 Interface Control Signals Name PQFP BGA Type Strength Description FRAME/ 16 F2 S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate the beginning and duration of an ...

PCI Bus Interface Signals 3-7 3.3.4 Arbitration Signals Table 3.5 describes Arbitration signals. 3.3.5 Error Reporting Signals Table 3.6 describes the Error Reporting signals. Table 3.5 Arbitration Signals Name PQFP BGA Type Strength Description REQ/ 148 E6 O 8 mA PCI Request indicates to the system...

3-8 Signal Descriptions 3.3.6 Interrupt Signal Table 3.7 describes the Interrupt signal. 3.4 SCSI Bus Interface Signals The SCSI Bus Interface signals section contains tables describing thesignals for the following signal groups: SCSI Bus Interface Signals , SCSI Signals , and SCSI Control Signals ....

SCSI Bus Interface Signals 3-9 3.4.2 SCSI Signals Table 3.9 describes the SCSI signals. 3.4.3 SCSI Control Signals Table 3.10 describes the SCSI Control signals. Table 3.9 SCSI Signals Name PQFP BGA Type Strength Description SD[15:0] 113, 115–17, 85–87, 89,102, 103, 105–108, 110,111 D13, E10, C13, D...

3-10 Signal Descriptions 3.5 GPIO Signals Table 3.11 describes the SCSI GPIO signals. Table 3.11 GPIO Signals Name PQFP BGA Type Strength Description GPIO0_FETCH/ 53 N5 I/O 8 mA SCSI General Purpose I/O pin. Optionally,when driven LOW, indicates that the next busrequest will be for an opcode fetch. ...

ROM Flash and Memory Interface Signals 3-11 3.6 ROM Flash and Memory Interface Signals Table 3.12 describes the ROM Flash and Memory Interface signals. Table 3.12 ROM Flash and Memory Interface Signals Name PQFP BGA Type Strength Description MWE/ 139 C7 O 4 mA Memory Write Enable. This pin is used a...

3-12 Signal Descriptions 3.7 Test Interface Signals Table 3.13 describes Test Interface signals. MAD[7:0] 59–62,64–67 L7, M7,N7, K7,M8, N8,L8, K8 I/O 4 mA Memory Address/Data Bus. This bus is used inconjunction with the memory address strobe pinsand external address latches to assemble up to a20-bit...

Power and Ground Signals 3-13 3.8 Power and Ground Signals Table 3.14 describes the Power and Ground signals. Table 3.14 Power and Ground Signals Name PQFP BGA Type Strength Description VSS_I/O 4, 10, 14, 18,23, 27, 31, 37,42, 48, 69, 79,88, 93, 99,104, 109, 114,123, 133, 152,158 A9, B11, D12,E13, F...

3-14 Signal Descriptions 3.9 MAD Bus Programming The MAD[7:0] pins, in addition to serving as the address/data bus for thelocal memory interface, also are used to program power-up options forthe chip. A particular option is programmed allowing the internalpull-down current sink to pull the pin LOW a...

MAD Bus Programming 3-15 • The MAD[0] pin is the slow ROM pin. When pulled up, it enables twoextra cycles of data access time to allow use of slower memorydevices. • All MAD pins have internal pull-down resistors.

LSI53C875A PCI to Ultra SCSI Controller 4-1 Chapter 4Registers This chapter describes all LSI53C875A registers and is divided into thefollowing sections: • Section 4.1 “PCI Configuration Registers” • Section 4.2 “SCSI Registers” • Section 4.3 “64-Bit SCRIPTS Selectors” • Section 4.4 “Phase Mismatch ...

4-2 Registers bits that are currently supported by the LSI53C875A are described in thischapter. Reserved bits should not be accessed . Registers: 0x00–0x01 Vendor IDRead Only VID Vendor ID [15:0] This 16-bit register identifies the manufacturer of thedevice. The Vendor ID is 0x1000. Table 4.1 PCI Co...

PCI Configuration Registers 4-3 Registers: 0x02–0x03 Device IDRead Only DID Device ID [15:0] This 16-bit register identifies the particular device. TheLSI53C875A Device ID is 0x0013. Registers: 0x04–0x05 CommandRead/Write The Command register provides coarse control over a device’s ability to genera...

4-4 Registers R Reserved 5 WIE Write and Invalidate Enable 4 This bit allows the LSI53C875A to generate write andinvalidate commands on the PCI bus. The WIE bit in the DMA Control (DCNTL) register must also be set for the device to generate Write and Invalidate commands. R Reserved 3 EBM Enable Bus ...

PCI Configuration Registers 4-5 Registers: 0x06–0x07 StatusRead/Write Reads to this register behave normally. Writes are slightly different in thatbits can be cleared, but not set. A bit is cleared whenever the register iswritten, and the data in the corresponding bit location is a one. Forinstance,...

4-6 Registers These bits are read only and should indicate the slowesttime that a device asserts DEVSEL/ for any buscommand except Configuration Read and ConfigurationWrite. The LSI53C875A supports a value of 0b01. DPR Data Parity Error Reported 8 This bit is set when all of the following conditions...

4-8 Registers Register: 0x0D Latency TimerRead/Write LT Latency Timer [7:0] The Latency Timer register specifies, in units of PCI busclocks, the value of the Latency Timer for this PCI busmaster. The LSI53C875A supports this timer. All eightbits are writable, allowing latency values of 0–255 PCIcloc...

PCI Configuration Registers 4-9 Registers: 0x10–0x13 Base Address Register Zero (I/O)Read/Write BAR0 Base Address Register Zero - I/O [31:0] This base address register is used to map the operatingregister set into I/O space. The LSI53C875A requires256 bytes of I/O space for this base address registe...

4-10 Registers Registers: 0x18–0x1B Base Address Register Two (SCRIPTS RAM)Read/Write BAR2 Base Address Register Two [31:0] This base register is used to map the SCRIPTS RAM intomemory space. The default value of this register is0x00000000. The LSI53C875A points to 4096 bytes ofaddress space with th...

PCI Configuration Registers 4-11 controller installed on them (and therefore the sameVendor ID and Device ID). If the external serial EEPROM interface is enabled(MAD[7] LOW), this register is automatically loaded atpower-up from the external serial EEPROM and willcontain the value downloaded from th...

4-12 Registers value that should be stored in the external serialEEPROM is vendor specific. Please see the Section 2.4 “Serial EEPROM Interface” in Chapter 2 for additional information on downloading a value for this register. Registers: 0x30–0x33 Expansion ROM Base AddressRead/Write ERBA Expansion ...

PCI Configuration Registers 4-17 DSCL Data_Scale [14:13] The LSI53C875A does not support the data register.Therefore, these two bits are always cleared. DSLT Data_Select [12:9] The LSI53C875A does not support the data register.Therefore, these four bits are always cleared. PEN PME_Enable 8 The LSI53...

SCSI Registers 4-19 Table 4.2 SCSI Register Address Map 31 16 15 0 SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 GPREG0 SDID SXFER SCID 0x04 SBCL SSID SOCL SFBR 0x08 SSTAT2 SSTAT1 SSTAT0 DSTAT 0x0C DSA 0x10 MBOX1 MBOX0 ISTAT1 ISTAT0 0x14 CTEST3 CTEST2 CTEST1 CTEST0 0x18 TEMP 0x1C CTEST6 CTEST5 CTEST4 DFIFO 0x20 ...

4-20 Registers Register: 0x00 SCSI Control Zero (SCNTL0)Read/Write ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6] Simple Arbitration 1. The LSI53C875A waits for a bus free condition to occur. 2. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus. If the ...

SCSI Registers 4-21 Full Arbitration, Selection/Reselection 1. The LSI53C875A waits for a bus free condition. 2. It asserts SBSY/ and its SCSI ID (the highest priority ID stored in the SCSI Chip ID (SCID) register) onto the SCSI bus. 3. If the SSEL/ signal is asserted by another SCSI device or if th...

4-22 Registers WATN Select with SATN/ on a Start Sequence 4 When this bit is set and the LSI53C875A is in the initiatormode, the SATN/ signal is asserted during selection of aSCSI target device. This is to inform the target that theLSI53C875A has a message to send. If a selectiontime-out occurs whil...

SCSI Registers 4-23 ( SET TARGET or CLEAR TARGET ). When this bit is set, the chip is a target device by default. When this bit is cleared,the LSI53C875A is an initiator device by default. Caution: Writing this bit while not connected may cause the loss ofa selection or reselection due to the changi...

4-24 Registers may transfer up to three additional bytes before halting tosynchronize between internal core cells. Duringsynchronous operation, the LSI53C875A transfers datauntil there are no outstanding synchronous offsets. If theLSI53C875A is receiving data, any data residing in theDMA FIFO is sen...

SCSI Registers 4-25 SCSI Control Zero (SCNTL0) register are set for full arbitration and selection before setting this bit. Arbitration is retried until won. At that point, theLSI53C875A holds SBSY and SSEL asserted, and waitsfor a select or reselect sequence. The ImmediateArbitration bit is cleared...

4-26 Registers Caution: Writing to this register while not connected may cause theloss of a selection/reselection by clearing the Connectedbit. Register: 0x02 SCSI Control Two (SCNTL2)Read/Write SDU SCSI Disconnect Unexpected 7 This bit is valid in the initiator mode only. When this bit isset, the S...

SCSI Registers 4-27 combined with the first byte from the subsequent transferso that a wide transfer is completed. SLPMD SLPAR Mode 5 If this bit is cleared, the SCSI Longitudinal Parity (SLPAR) register functions as a byte-wide longitudinal parityregister. If this bit is set, the SLPAR functions as...

4-28 Registers group codes. If this bit is set, the device does not reloadthe Block Move byte count, regardless of the group code. WSR Wide SCSI Receive 0 When read, this bit returns the value of the Wide SCSIReceive (WSR) flag. Setting this bit clears the WSR flag.This clearing function is self-cle...

SCSI Registers 4-29 SCF[2:0] Synchronous Clock Conversion Factor [6:4] These bits select a factor by which the frequency ofSCLK is divided before being presented to thesynchronous SCSI control logic. Write these to the samevalue as the Clock Conversion Factor bits below unlessfast SCSI operation is ...

4-30 Registers Register: 0x04 SCSI Chip ID (SCID)Read/Write R Reserved 7 RRE Enable Response to Reselection 6 When this bit is set, the LSI53C875A is enabled torespond to bus-initiated reselection at the chip ID in the Response ID Zero (RESPID0) and Response ID One (RESPID1) registers. Note that the...

SCSI Registers 4-31 Register: 0x05 SCSI Transfer (SXFER)Read/Write Note: When using Table Indirect I/O commands, bits [7:0] of thisregister are loaded from the I/O data structure. TP[2:0] SCSI Synchronous Transfer Period [7:5] These bits determine the SCSI synchronous transferperiod used by the LSI5...

4-32 Registers (This SCSI synchronous core clock is determined inSCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is assertedand the LSI53C875A is sending data. ExtCC = 0 if theLSI53C875A is receiving data.) SXFERP = 100 ÷ 25 = 4 Where: Table 4.3 shows examples of synchronous transfer periods and rates ...

SCSI Registers 4-33 Table 4.4 shows example transfer periods and rates for fast SCSI-2 and Ultra SCSI. MO[4:0] Max SCSI Synchronous Offset [4:0] These bits describe the maximum SCSI synchronousoffset used by the LSI53C875A when transferringsynchronous SCSI data in either the initiator or targetmode....

4-34 Registers Table 4.5 Maximum Synchronous Offset MO4 MO3 MO2 MO1 MO0 Synchronous Offset 0 0 0 0 0 0-Asynchronous 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 0 0 1 0 1 5 0 0 1 1 0 6 0 0 1 1 1 7 0 1 0 0 0 8 0 1 0 0 1 9 0 1 0 1 0 10 0 1 0 1 1 11 0 1 1 0 0 12 0 1 1 0 1 13 0 1 1 1 0 14 0 1 1 1 1 1...

SCSI Registers 4-35 Register: 0x06 SCSI Destination ID (SDID)Read/Write R Reserved [7:4] ENC Encoded Destination SCSI ID [3:0] Writing these bits set the SCSI ID of the intended initiatoror target during SCSI reselection or selection phases,respectively. When executing SCRIPTS, the SCRIPTSprocessor ...

4-36 Registers is also possible to program these signals as live inputsand sense them through a SCRIPTS register to registerMove Instruction. GPIO4 may be used to enable ordisable V PP , the 12 Volt power supply to the external flash memory. This bit powers up with the power to externalmemory disabl...

4-38 Registers Register: 0x0A SCSI Selector ID (SSID)Read Only VAL SCSI Valid 7 If VAL is asserted, then the two SCSI IDs are detectedon the bus during a bus-initiated selection or reselection,and the encoded destination SCSI ID bits below are valid.If VAL is deasserted, only one ID is present and t...

SCSI Registers 4-39 REQ SREQ/ Status 7 ACK SACK/ Status 6 BSY SBSY/ Status 5 SEL SSEL/ Status 4 ATN SATN/ Status 3 MSG SMSG/ Status 2 C_D SC_D/ Status 1 I_O SI_O/ Status 0 Register: 0x0C DMA Status (DSTAT)Read Only Reading this register clears any bits that are set at the time the registeris read, b...

4-40 Registers MDPE Master Data Parity Error 6 This bit is set when the LSI53C875A as a master detectsa data parity error, or a target device signals a parity errorduring a data phase. This bit is completely disabled bythe Master Parity Error Enable bit (bit 3 of Chip Test Four (CTEST4) ). BF Bus Fa...

SCSI Registers 4-41 • During a Transfer Control instruction, the CompareData (bit 18) and Compare Phase (bit 17) bits are setin the DMA Byte Counter (DBC) register while the LSI53C875A is in target mode. • During a Transfer Control instruction, the Carry Testbit (bit 21) is set and either the Compar...

4-42 Registers Register: 0x0D SCSI Status Zero (SSTAT0)Read Only ILF SIDL Least Significant Byte Full 7 This bit is set when the least significant byte in the SCSI Input Data Latch (SIDL) register contains data. Data is transferred from the SCSI bus to the SCSI Input DataLatch register before being ...

4-44 Registers synchronous data transfers, or up to 31 words for wide.Values over 31 will not occur. Table 4.6 SCSI Synchronous Data FIFO Word Count FF4 (SSTAT2 bit 4) FF3 FF2 FF1 FF0 Bytes or Words in the SCSI FIFO 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 0 0 1 0 1 5 0 0 1 1 0 6 ...

SCSI Registers 4-45 SDP0L Latched SCSI Parity 3 This bit reflects the SCSI parity signal (SDP0/),corresponding to the data latched in the SCSI Input Data Latch (SIDL) . It changes when a new byte is latched into the least significant byte of the SIDL register. This bit isactive HIGH, in other words,...

4-46 Registers Register: 0x0F SCSI Status Two (SSTAT2)Read Only ILF1 SIDL Most Significant Byte Full 7 This bit is set when the most significant byte in the SCSI Input Data Latch (SIDL) contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch registerbefore being sent to the...

SCSI Registers 4-47 field, see the definition for SCSI Status One (SSTAT1) bits [7:4]. SPL1 Latched SCSI Parity for SD[15:8] 3 This active HIGH bit reflects the SCSI odd parity signalcorresponding to the data latched into the mostsignificant byte in the SCSI Input Data Latch (SIDL) register. R Reser...

4-48 Registers Register: 0x14 Interrupt Status Zero (ISTAT0)Read/Write This register is accessible by the host CPU while a LSI53C875A isexecuting SCRIPTS (without interfering in the operation of the function).It is used to poll for interrupts if hardware interrupts are disabled. Readthis register af...

4-50 Registers the SCRIPTS processor is still executing a SCRIPTSprogram. If this bit is set when the Interrupt Status Zero (ISTAT0) or Interrupt Status One (ISTAT1) registers are read they are not automatically cleared. To clear this bit,write it to a one. The reset operation is self-clearing. Note...

SCSI Registers 4-51 • A bus fault is detected • An abort condition is detected • A SCRIPTS instruction is executed in single stepmode • A SCRIPTS interrupt instruction is executed • An illegal instruction is detected To determine exactly which condition(s) caused theinterrupt, read the DMA Status (D...

4-52 Registers addition, this bit may be read and written while SCRIPTSare executing. Register: 0x16 Mailbox Zero (MBOX0)Read/Write MBOX0 Mailbox Zero [7:0] These are general purpose bits that may be read orwritten while SCRIPTS are running. They also may beread or written by the SCRIPTS processor. ...

4-54 Registers Register: 0x1A Chip Test Two (CTEST2)Read Only (bit 3 write) DDIR Data Transfer Direction 7 This status bit indicates which direction data is beingtransferred. When this bit is set, the data is transferredfrom the SCSI bus to the host bus. When this bit is clear,the data is transferre...

SCSI Registers 4-55 Base Address Register One (MEMORY) . This is the memory mapped operating register base address. Bits[9:0] will be 0. The SCRATCHB register contains bits[31:13] of the RAM Base Address value from the PCI Base Address Register Two (SCRIPTS RAM) . This is the base address for the in...

4-56 Registers Register: 0x1B Chip Test Three (CTEST3)Read/Write V Chip Revision Level [7:4] These bits identify the chip revision level for softwarepurposes. It should have the same value as the lowernibble of the PCI Revision ID (Rev ID) register, at address 0x08 in the configuration space. FLF Fl...

4-60 Registers LSI53C875A is informed of the error by the PERR/ pinbeing asser ted by the target. When this bit is cleared, theLSI53C875A does not interrupt if a master parity erroroccurs. This bit is cleared at power-up. FBL[2:0] FIFO Byte Control [2:0] These bits steer the contents of the Chip Tes...

SCSI Registers 4-61 the current DBC value. This bit automatically clears itselfafter incrementing the DNAD register. BBCK Clock Byte Counter 6 Setting this bit decrements the byte count contained inthe 24-bit DBC register. It is decremented based on the DMA Byte Counter (DBC) contents and the curren...

4-62 Registers BO[9:8] DMA FIFO Byte Offset Counter, Bits [9:8] [1:0] These are the upper two bits of the DFBOC. The DFBOCconsists of these bits, and the DMA FIFO (DFIFO) register, bits [7:0]. Register: 0x23 Chip Test Six (CTEST6)Read/Write DF DMA FIFO [7:0] Writing to this register writes data to t...

SCSI Registers 4-63 LSI53C875A. The DBC counter is decremented eachtime data is transferred on the PCI bus. It is decrementedby an amount equal to the number of bytes that aretransferred. The maximum number of bytes that can be transferred inany one Block Move command is 16,777,215 bytes. Themaximum...

4-64 Registers Registers: 0x28–0x2B DMA Next Address (DNAD)Read/Write DNAD DMA Next Address [31:0] This 32-bit register contains the general purpose addresspointer. At the start of some SCRIPTS operations, itsvalue is copied from the DMA SCRIPTS Pointer Save (DSPS) register. Its value may not be val...

SCSI Registers 4-65 Registers: 0x30–0x33 DMA SCRIPTS Pointer Save (DSPS)Read/Write DSPS DMA SCRIPTS Pointer Save [31:0] This register contains the second Dword of a SCRIPTSinstruction. It is overwritten each time a SCRIPTSinstruction is fetched. When a SCRIPTS interruptinstruction is executed, this ...

4-66 Registers Register: 0x38 DMA Mode (DMODE)Read/Write BL[1:0] Burst Length [7:6] These bits control the maximum number of Dwordstransferred per bus ownership, regardless of whether thetransfers are back-to-back, burst, or a combination ofboth. The LSI53C875A asserts the Bus Request (REQ/)output w...

SCSI Registers 4-69 Register: 0x39 DMA Interrupt Enable (DIEN)Read/Write R Reserved 7 MDPE Master Data Parity Error 6 BF Bus Fault 5 ABRT Aborted 4 SSI Single Step Interrupt 3 SIR SCRIPTS Interrupt Instruction Received 2 R Reserved 1 IID Illegal Instruction Detected 0 This register contains the inte...

4-70 Registers For more information on interrupts, see Chapter 2, “Functional Description” . Register: 0x3A Scratch Byte Register (SBR)Read/Write SBR Scratch Byte Register [7:0] This is a general purpose register. Apar t from CPUaccess, only register Read/Write and Memory Moves intothis register alt...

SCSI Registers 4-71 the LSI53C875A to make more efficient use of thesystem PCI bus, thus improving overall systemperformance. The unit will flush whenever the PFF bit isset, as well as on all transfer control instructions whenthe transfer conditions are met, on every write to the DMA SCRIPTS Pointer...

4-72 Registers STD Start DMA Operation 2 The LSI53C875A fetches a SCSI SCRIPTS instructionfrom the address contained in the DMA SCRIPTS Pointer (DSP) register when this bit is set. This bit is required if the LSI53C875A is in one of the following modes: • Manual start mode – Bit 0 in the DMA Mode (D...

SCSI Registers 4-73 Registers: 0x3C–0x3F Adder Sum Output (ADDER)Read Only ADDER Adder Sum Output [31:0] This register contains the output of the internal adder,and is used primarily for test purposes. The power-upvalue for this register is indeterminate. It is used todetermine if the correct memory...

4-74 Registers CMP Function Complete 6 Indicates full arbitration and selection sequence iscompleted. SEL Selected 5 Indicates the LSI53C875A is selected by a SCSI initiatordevice. Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register for this to occur. RSL Reselected 4 Indica...

4-76 Registers HTH Handshake-to-Handshake Timer Expired 0 The handshake-to-handshake timer is expired. The timemeasured is the SCSI Request-to-Request (target) orAcknowledge-to-Acknowledge (initiator) period. See thedescription of the SCSI Timer Zero (STIME0) register, bits [7:4], for more informati...

SCSI Registers 4-77 target. In target mode, this bit is set when the SATN/signal is asserted by the initiator. CMP Function Complete 6 This bit is set when an arbitration only or full arbitrationsequence is completed. SEL Selected 5 This bit is set when the LSI53C875A is selected byanother SCSI devi...

4-78 Registers • Residual data in the synchronous data FIFO – atransfer other than synchronous data receive isstarted with data left in the synchronous data FIFO. UDC Unexpected Disconnect 2 This bit is set when the LSI53C875A is operating in theinitiator mode and the target device unexpectedlydisco...

SCSI Registers 4-79 (SIEN1) register or not. Each bit that is set indicates an occurrence of the corresponding condition. Reading the SIST1 clears the interrupt condition. R Reserved [7:3] STO Selection or Reselection Time-out 2 The SCSI device which the LSI53C875A is attempting toselect or reselect...

4-80 Registers check byte are received from the SCSI bus (all signalsare shown active HIGH): A one in any bit position of the final SLPAR value wouldindicate a transmission error. The SLPAR register is also used to generate the checkbytes for SCSI send operations. If the SLPAR registercontains all z...

SCSI Registers 4-81 Which byte is accessed is controlled by the SLPHBEN bitin the SCSI Control Two (SCNTL2) register. Register: 0x45 SCSI Wide Residue (SWIDE)Read/Write SWIDE SCSI Wide Residue [7:0] After a wide SCSI data receive operation, this registercontains a residual data byte if the last byte...

4-82 Registers DWR Data Write 3 This bit is used to define if a data write is considered tobe a local memory access. DRD Data Read 2 This bit is used to define if a data read is considered tobe a local memory access. PSCPT Pointer SCRIPTS 1 This bit is used to define if a pointer to a SCRIPTSindirec...

SCSI Registers 4-83 LEDC LED_CNTL 5 The internal connected signal (bit 3 of the Interrupt Status Zero (ISTAT0) register) will be presented on GPIO0 if this bit is set and bit 6 of GPCNTL0 is cleared and the chipis not in progress of performing an EEPROMautodownload regardless of the state of bit 0 (...

4-84 Registers SEL[3:0] Selection Time-Out [3:0] These bits select the SCSI selection/reselection time-outperiod. When this timing (plus the 200 µ s selection abort time) is exceeded, the STO bit in the SCSI Interrupt Status One (SIST1) register is set. For a more detailed explanation of interrupts,...

SCSI Registers 4-85 Register: 0x49 SCSI Timer One (STIME1)Read/Write R Reserved 7 HTHBA Handshake-to-Handshake Timer Bus ActivityEnable 6 Setting this bit causes this timer to begin testing for SCSIREQ/, ACK/ activity as soon as SBSY/ is asserted,regardless of the agents participating in the transfe...

4-86 Registers Register: 0x4A Response ID Zero (RESPID0)Read/Write RESPIO0 Response ID Zero [7:0] RESPID0 and Response ID One (RESPID1) contain the selection or reselection IDs. In other words, these two8-bit registers contain the ID that the chip responds to onthe SCSI bus. Each bit represents one ...

SCSI Registers 4-87 chip can arbitrate with only one ID value in the SCIDregister. Register: 0x4C SCSI Test Zero (STEST0)Read Only SSAID SCSI Selected As ID [7:4] These bits contain the encoded value of the SCSI ID thatthe LSI53C875A is selected during a SCSI selectionphase. These bits work in conju...

4-88 Registers SOM SCSI Synchronous Offset Maximum 0 This bit indicates that the current synchronous SREQ/,SACK/ offset is the maximum specified by bits [3:0] in the SCSI Transfer (SXFER) register. This bit is not latched and may change at any time. It is used in low levelsynchronous SCSI operations...

SCSI Registers 4-91 Register: 0x4F SCSI Test Three (STEST3)Read/Write TE TolerANT Enable 7 Setting this bit enables the active negation portion ofLSI Logic TolerANT technology. Active negation causesthe SCSI Request, Acknowledge, Data, and Paritysignals to be actively deasserted, instead of relying ...

SCSI Registers 4-93 STW SCSI FIFO Test Write 0 Setting this bit places the SCSI core into a test mode inwhich the FIFO is easily read or written. While this bit isset, writes to the least significant byte of the SCSI Output Data Latch (SODL) register cause the entire word contained in the SODL to be...

SCSI Registers 4-95 Register: 0x56 Chip Control 0 (CCNTL0)Read/Write ENPMJ Enable Phase Mismatch Jump 7 Upon setting this bit, any phase mismatches do notinterrupt but force a jump to an alternate location tohandle the phase mismatch. Prior to actually taking thejump, the appropriate remaining byte ...

4-98 Registers Index Mode 1 (64TIMOD set) table entry format: EN64TIBMV Enable 64-Bit Table Indirect BMOV 1 Setting this bit enables 64-bit addressing for TableIndirect BMOVs using the upper byte (bit [24:31]) of thefirst Dword of the table entry. When this bit is clearedtable indirect BMOVs will us...

64-Bit SCRIPTS Selectors 4-99 Register: 0x5A–0x5B Reserved Registers: 0x5C–0x5F Scratch Register B (SCRATCHB)Read/Write SCRATCHB Scratch Register B [31:0] This is a general purpose user definable scratch padregister. Apart from CPU access, only registerRead/Write and Memory Moves directed at theSCRA...

64-Bit SCRIPTS Selectors 4-101 Registers: 0xA4–0xA7 Memory Move Write Selector (MMWS)Read/Write MMWS Memory Move Write Selector [31:0] Supplies the upper Dword of a 64-bit address during datawrite operations during Memory-to-Memory Moves andabsolute address STORE operations. A special mode of this r...

4-102 Registers Writes to the SFS register are unaffected. Clearing thePCI Configuration Into Enable bit causes the SFS registerto return to normal operation. Registers: 0xAC–0xAF DSA Relative Selector (DRS)Read/Write DRS DSA Relative Selector [31:0] Supplies the upper Dword of a 64-bit address duri...

Phase Mismatch Jump Registers 4-103 Registers: 0xB4–0xB7 Dynamic Block Move Selector (DBMS)Read/Write DBMS Dynamic Block Move Selector [31:0] Supplies the upper Dword of a 64-bit address duringblock move operations, reads or writes. This register isused only during 64-bit direct BMOV instructions an...

4-104 Registers Registers: 0xC0–0xC3 Phase Mismatch Jump Address 1 (PMJAD1)Read/Write PMJAD1 Phase Mismatch Jump Address 1 [31:0] This register contains the 32-bit address that will bejumped to upon a phase mismatch. Depending upon thestate of the PMJCTL bit in register Chip Control 0 (CCNTL0) this ...

4-106 Registers In the case of a SCSI data receive, if there is a byte inthe SCSI Wide Residue (SWIDE) register then this address will point to the location where that byte must bestored. The SWIDE byte must be manually written tomemory and this address must be incremented prior toupdating any scatt...

Phase Mismatch Jump Registers 4-107 Registers: 0xD4–0xD7 Instruction Address (IA)Read/Write IA Instruction Address [31:0] This register always contains the address of the BMOVinstruction that was executing when the phase mismatchoccurred. This value will always match the value in the Entry Storage A...

LSI53C875A PCI to Ultra SCSI Controller 5-1 Chapter 5SCSI SCRIPTSInstruction Set The LSI53C875A contains a SCSI SCRIPTS processor that permits bothDMA and SCSI commands to be fetched from host memory or internalSCRIPTS RAM. Algorithms written in SCSI SCRIPTS control the actionsof the SCSI and DMA co...

5-2 SCSI SCRIPTS Instruction Set require certain unique timings or bus sequences to operate properly.Another feature allowed at the low level is loopback testing. In loopbackmode, the SCSI core can be directed to talk to the DMA core to testinternal data paths all the way out to the chip’s pins. 5.2...

High Level SCSI SCRIPTS Mode 5-3 Each instruction consists of two or three 32-bit words. The first 32-bitword is always loaded into the DMA Command (DCMD) and DMA Byte Counter (DBC) registers, the second into the DMA SCRIPTS Pointer Save (DSPS) register. The third word, used only by Memory Move inst...

5-4 SCSI SCRIPTS Instruction Set • The LSI53C875A typically fetches two Dwords (64 bits) and decodesthe high order byte of the first longword as a SCRIPTS instruction. Ifthe instruction is a Block Move, the lower three bytes of the firstlongword are stored and interpreted as the number of bytes to b...

High Level SCSI SCRIPTS Mode 5-5 Figure 5.1 SCRIPTS Overview System Processor System Memory SCSI Initiator Write Example × Select ATN 0, alt_addr × Move from identify_msg_buf, when MSG_OUT × Move from data_buf when DATA_OUT × Move from stat_in_buf, when STATUS × Move SCNTL2 & 7F to SCNTL2 × Clea...

5-6 SCSI SCRIPTS Instruction Set 5.3 Block Move Instruction Performing a Block Move instruction, bit 5, Source I/O - Memory Enable(SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the DMA Mode (DMODE) register determines whether the source/destination address resides in memory or I/O space...

Block Move Instruction 5-7 Direct Addressing The byte count and absolute address are: Indirect Addressing Use the fetched byte count, but fetch the data addressfrom the address in the instruction. Once the data pointer address is loaded, it is executedas when the chip operates in the direct mode. Th...

5-8 SCSI SCRIPTS Instruction Set the data structure. Sign extended values of all ones fornegative values are allowed, but bits [31:24] are ignored. Note: Do not use indirect and table indirect addressingsimultaneously; use only one addressing method at a time. Prior to the start of an I/O, the Data ...

Block Move Instruction 5-9 OPC OpCode 27 This 1-bit OpCode field defines the type of Block Move(MOVE) Instruction to be preformed in Target and Initiatormode. Target Mode In Target mode, the OpCode bit defines the followingoperations: These instructions perform the following steps: 1. The LSI53C875A...

5-10 SCSI SCRIPTS Instruction Set register contains 0x000000, an illegal instructioninterrupt is generated. 4. The LSI53C875A transfers the number of bytes specified inthe DBC register starting at the address specified in the DMA Next Address (DNAD) register. If the OpCode bit is set and a data tran...

Block Move Instruction 5-11 register. These phase lines are latched when SREQ/ isasserted. 4. If the SCSI phase bits match the value stored in the SCSI SCSI Status One (SSTAT1) register, the LSI53C875A transfers the number of bytes specified in the DMA Byte Counter (DBC) register star ting at the ad...

5-12 SCSI SCRIPTS Instruction Set TC[23:0] Transfer Counter [23:0] This 24-bit field specifies the number of data bytes to bemoved between the LSI53C875A and system memory.The field is stored in the DMA Byte Counter (DBC) register. When the LSI53C875A transfers data to/frommemory, the DBC register i...

I/O Instruction 5-13 5.3.2 Second Dword Start Address [31:0] This 32-bit field specifies the starting address of the datato move to/from memory. This field is copied to the DMA Next Address (DNAD) register. When the LSI53C875A transfers data to or from memory, the DNAD register isincremented by the ...

5-14 SCSI SCRIPTS Instruction Set 5.4.1 First Dword IT[1:0] Instruction Type - I/O Instruction [31:30] The IT bit configuration (01) defines an I/O InstructionType. OPC[2:0] OpCode [29:27] The OpCode bit configurations define the I/O operationperformed but the OpCode bit meanings change in Targetmod...

I/O Instruction 5-15 This way the SCRIPTS can move on to the nextinstruction before the reselection completes. It continuesexecuting SCRIPTS until a SCRIPT that requires aresponse from the Initiator is encountered. If the LSI53C875A is selected or reselected beforewinning arbitration, it fetches the...

5-16 SCSI SCRIPTS Instruction Set When the SACK/ or SATN/ bits are cleared, thecorresponding bits are cleared in the SCSI Output Control Latch (SOCL) register. Do not set SACK/ or SATN/ except for testing purposes. When thetarget bit is cleared, the corresponding bit in the SCSI Control Zero (SCNTL0...

I/O Instruction 5-17 the LSI53C875A to Initiator mode if it is reselected, or toTarget mode if it is selected. If the Select with SATN/ field is set, the SATN/ signal isasserted during the selection phase. Wait Disconnect Instruction The LSI53C875A waits for the Target to perform a “legal”disconnect...

5-18 SCSI SCRIPTS Instruction Set RA Relative Addressing Mode 26 When this bit is set, the 24-bit signed value in the DMA Next Address (DNAD) register is used as a relative displacement from the current DMA SCRIPTS Pointer(DSP) address. Use this bit only in conjunction with theSelect, Reselect, Wait...

I/O Instruction 5-19 Use this bit only in conjunction with the Select, Reselect,Wait Select, and Wait Reselect instructions. Use bits 25and 26 individually or in = combination to produce the following conditions: Direct Uses the device ID and physical address in theinstruction. Table Indirect Uses t...

5-20 SCSI SCRIPTS Instruction Set Table Relative Treats the alternate jump address as a relative jump andfetches the device ID, synchronous offset, andsynchronous period indirectly. The value in bits [23:0] ofthe first four bytes of the SCRIPTS instruction is addedto the data structure base address ...

5-22 SCSI SCRIPTS Instruction Set If relative or table relative addressing is used, this valueis a 24-bit signed offset relative to the current DMA SCRIPTS Pointer (DSP) register value. 5.5 Read/Write Instructions The Read/Write instruction supports addition, subtraction, andcomparison of two separa...

Read/Write Instructions 5-23 A[6:0] Register Address - A[6:0] [22:16] It is possible to change register values from SCRIPTS inread-modify-write cycles or move to/from SFBR cycles.A[6:0] selects an 8-bit source/destination register withinthe LSI53C875A. ImmD Immediate Data [15:8] This 8-bit value is ...

5-24 SCSI SCRIPTS Instruction Set 5.5.4 Move To/From SFBR Cycles All operations are read-modify-writes. However, two registers areinvolved, one of which is always the SFBR. Table 5.3 shows the possible read-modify-write operations. The possible functions of this instructionare: • Write one byte (val...

Transfer Control Instructions 5-25 Miscellaneous Notes: • Substitute the desired register name or address for “RegA” in the syntax examples.• data8 indicates eight bits of data.• Use SFBR instead of data8 to add two register values. 5.6 Transfer Control Instructions This section describes the Transf...

5-26 SCSI SCRIPTS Instruction Set 5.6.1 First Dword IT[1:0] Instruction Type - Transfer ControlInstruction [31:30] The IT bit configuration (10) defines the Transfer ControlInstruction Type. OPC[2:0] OpCode [29:27] This 3-bit field specifies the type of Transfer ControlInstruction to execute. All Tr...

Transfer Control Instructions 5-27 DMA SCRIPTS Pointer Save (DSPS) register. The DSP register now contains the address of the next instruction. If the comparisons are false, the LSI53C875A fetches thenext instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register, leaving the ...

5-28 SCSI SCRIPTS Instruction Set If the comparisons are false, the LSI53C875A fetches thenext instruction from the address pointed to by the DSPregister and the instruction pointer is not modified. Interrupt Instruction The LSI53C875A can do a true/false comparison of theALU carry bit, or compare t...

Transfer Control Instructions 5-29 RA Relative Addressing Mode 23 When this bit is set, the 24-bit signed value in the DMA SCRIPTS Pointer Save (DSPS) register is used as a relative offset from the current DMA SCRIPTS Pointer(DSP) address (which is pointing to the next instruction,not the one curren...

Transfer Control Instructions 5-31 CD Compare Data 18 When this bit is set, the first byte received from the SCSIdata bus (contained in the SCSI First Byte Received (SFBR) register) is compared with the Data to be Compared Field in the Transfer Control instruction. TheWait for Valid Phase bit contro...

5-32 SCSI SCRIPTS Instruction Set DCV Data Compare Value [7:0] This 8-bit field is the data compared against the register.These bits are used in conjunction with the DataCompare Mask Field to test for a particular data value. 5.6.2 Second Dword Jump Address [31:0] This 32-bit field contains the addr...

Memory Move Instructions 5-33 • Indirect addresses are not allowed. A burst of data is fetched fromthe source address, put into the DMA FIFO and then written out tothe destination address. The move continues until the byte countdecrements to zero, then another SCRIPTS is fetched from systemmemory. T...

5-34 SCSI SCRIPTS Instruction Set 5.7.2 Read/Write System Memory from SCRIPTS By using the Memory Move instruction, single or multiple register valuesare transferred to or from system memory. Because the LSI53C875A responds to addresses as defined in the Base Address Register Zero (I/O) or Base Addr...

Load and Store Instructions 5-35 5.7.4 Third Dword TEMP Register [31:0] These bits contain the destination address for theMemory Move. 5.8 Load and Store Instructions The Load and Store instructions provide a more efficient way to movedata from/to memory to/from an internal register in the chip with...

5-36 SCSI SCRIPTS Instruction Set The SIOM and DIOM bits in the DMA Mode (DMODE) register determine whether the destination or source address of the instruction is in Memoryspace or I/O space, as illustrated in the following table. The Load andStore utilizes the PCI commands for I/O read and I/O wri...

Load and Store Instructions 5-37 Note: This bit has no effect unless the Prefetch Enable bit in the DMA Control (DCNTL) register is set. LS Load and Store 24 When this bit is set, the instruction is a Load. Whencleared, it is a Store. R Reserved 23 RA[6:0] Register Address [22:16] A[6:0] selects the...

LSI53C875A PCI to Ultra SCSI Controller 6-1 Chapter 6ElectricalSpecifications This section specifies the LSI53C875A electrical and mechanicalcharacteristics. It is divided into the following sections: • Section 6.1, “DC Characteristics” • Section 6.2, “TolerANT Technology Electrical Characteristics”...

6-2 Electrical Specifications Table 6.1 Absolute Maximum Stress Ratings 1 1. Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond thoseindicated in the Operating Conditio...

DC Characteristics 6-3 Table 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/ Symbol Parameter Min Max Unit Test Conditions V IH Input high voltage 2.0 5.25 V – V IL Input low voltage V SS − 0.5 0.8 V – V OH Output high voltage 2.4 V DD V − 4 mA V OL Output low voltage V SS 0.4 V 4 mA...

6-4 Electrical Specifications Table 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/,DEVSEL/, STOP/, PERR/, PAR Symbol Parameter Min Max Unit Test Conditions V IH Input high voltage 0.5 V DD 5.25 V – V IL Input low voltage V SS 0.3 V DD V – V OH Output high voltage 0.9 V DD V DD ...

TolerANT Technology Electrical Characteristics 6-5 6.2 TolerANT Technology Electrical Characteristics The LSI53C875A features TolerANT technology, which includes activenegation on the SCSI drivers and input signal filtering on the SCSIreceivers. Active negation actively drives the SCSI Request,Ackno...

TolerANT Technology Electrical Characteristics 6-7 Figure 6.1 Rise and Fall Time Test Condition Figure 6.2 SCSI Input Filtering Figure 6.3 Hysteresis of SCSI Receivers + − 2.5 V 47 Ω 20 pF REQ/ or SACK/ Input t 1 V TH Note: t 1 is the input filtering period. 1 0 Rec e iv ed Logic L e v el Input Volt...

6-8 Electrical Specifications Figure 6.4 Input Current as a Function of Input Voltage Figure 6.5 Output Current as a Function of Output Voltage +40 +20 0 − 20 − 40 − 4 0 4 8 12 16 − 0.7 V 8.2 V HIGH-Z OUTPUT ACTIVE Input Voltage (Volts) Input Current (m illi A m per es) 14.4 V Output S ink Curr ent ...

AC Characteristics 6-9 6.3 AC Characteristics The AC characteristics described in this section apply over the entirerange of operating conditions (refer to the DC Characteristics section). Chip timings are based on simulation at worst case voltage, temperature,and processing. Timing was developed wi...

6-10 Electrical Specifications Table 6.13 and Figure 6.7 provide Reset Input timing data. Figure 6.7 Reset Input Table 6.14 and Figure 6.8 provide Interrupt Output timing data. Table 6.13 Reset Input Symbol Parameter Min Max Unit t 1 Reset pulse width 10 – t CLK t 2 Reset deasserted setup to CLK HIG...

PCI and External Memory Interface Timing Diagrams 6-11 Figure 6.8 Interrupt Output 6.4 PCI and External Memory Interface Timing Diagrams Figure 6.9 through Figure 6.32 represent signal activity when the LSI53C875A accesses the PCI bus. This section includes timingdiagrams for access to three groups ...

PCI and External Memory Interface Timing Diagrams 6-13 6.4.1 Target Timing The tables and figures in this section describe target timings. Figure 6.9 PCI Configuration Register Read Table 6.15 PCI Configuration Register Read Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2...

6-14 Electrical Specifications Figure 6.10 PCI Configuration Register Write Table 6.16 PCI Configuration Register Write Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time 0 – ns t 3 CLK to shared signal output valid – 11 ns CLK (Driven by System...

PCI and External Memory Interface Timing Diagrams 6-15 Figure 6.11 32-Bit Operating Register/SCRIPTS RAM Read Table 6.17 32-Bit Operating Register/SCRIPTS RAM Read Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time 0 – ns t 3 CLK to shared signa...

6-16 Electrical Specifications Figure 6.12 64-Bit Address Operating Register/SCRIPTS RAM Read Table 6.18 64-Bit Address Operating Register/SCRIPTS RAM Read Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time 0 – ns t 3 CLK to shared signal output...

PCI and External Memory Interface Timing Diagrams 6-17 Figure 6.13 32-Bit Operating Register/SCRIPTS RAM Write Table 6.19 32-Bit Operating Register/SCRIPTS RAM Write Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time 0 – ns t 3 CLK to shared sig...

6-18 Electrical Specifications Figure 6.14 64-Bit Address Operating Register/SCRIPTS RAM Write Table 6.20 64-Bit Address Operating Register/SCRIPTS RAM Write Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time 0 – ns t 3 CLK to shared signal outp...

PCI and External Memory Interface Timing Diagrams 6-19 6.4.2 Initiator Timing The tables and figures in this section describe LSI53C875A initiatortimings. Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared sign...

PCI and External Memory Interface Timing Diagrams 6-21 Table 6.22 Burst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time 0 – ns t 3 CLK to shared signal output valid 2 11 ns t 4 Side signal input setup tim...

6-28 Electrical Specifications Figure 6.19 Burst Read, 32-Bit Address and Data t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PAR (Driven by LSI53C875A- IRDY/ (Driven by LSI53C875A) TRDY/ (Driven by Target) STOP/ (Driven by Target) DE...

PCI and External Memory Interface Timing Diagrams 6-35 6.4.3 External Memory Timing The tables and figures in this section describe LSI53C875A externaltimings. The External Memory Write timings start on page 6-40 . Table 6.29 External Memory Read Symbol Parameter Min Max Unit t 1 Shared signal input...

6-36 Electrical Specifications Figure 6.23 External Memory Read 1 2 3 4 5 6 7 8 9 CLK (Driven by System) PAR (Driven by Master-Addr; IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) AD (Driven by Master-Addr; C_BE[3:0]/ (Driven by Mast...

6-38 Electrical Specifications Table 6.30 External Memory Write Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time 0 – ns t 3 CLK to shared signal output valid – 11 ns t 11 Address setup to MAS/ HIGH 25 – ns t 12 Address hold from MAS/ HIGH 15 –...

PCI and External Memory Interface Timing Diagrams 6-39 The External Memory Write timings start on page 6-40 .

6-40 Electrical Specifications Figure 6.24 External Memory Write 1 2 3 4 5 6 7 8 9 CLK (Driven by System) PAR (Driven by Master-Addr; IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) AD (Driven by Master-Addr; C_BE[3:0]/ (Driven by Mas...

6-42 Electrical Specifications Figure 6.25 Normal/Fast Memory ( ≥ = 128 Kbytes) Single Byte Access Read Cycle Table 6.31 Normal/Fast Memory ( ≥ = 128 Kbytes) Single Byte Access Read Cycle Symbol Parameter Min Max Unit t 11 Address setup to MAS/ HIGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t...

PCI and External Memory Interface Timing Diagrams 6-43 Figure 6.26 Normal/Fast Memory ( ≥ = 128 Kbytes) Single Byte Access Write Cycle Table 6.32 Normal/Fast Memory ( ≥ = 128 Kbytes) Single Byte Access Write Cycle Symbol Parameter Min Max Unit t 11 Address setup to MAS/ HIGH 25 – ns t 12 Address hol...

6-44 Electrical Specifications Figure 6.27 Normal/Fast Memory ( ≥ = 128 Kbytes) Multiple Byte Access Read Cycle MAD (Addr Driven by LSI53C875A; MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A) MWE/ (Driven by LSI53C875A) 0 2 4 6 8 10 1...

6-46 Electrical Specifications Figure 6.28 Normal/Fast Memory ( ≥ = 128 Kbytes) Multiple Byte Access Write Cycle MAD (Driven by LSI53C875A) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A) MWE/ (Driven by LSI53C875A) 0 2 4 6 8 10 12 14...

6-48 Electrical Specifications Figure 6.29 Slow Memory ( ≤ = 128 Kbytes) Read Cycle Table 6.33 Slow Memory ( ≤ = 128 Kbytes) Read Cycle Symbol Parameter Min Max Unit t 11 Address setup to MAS/ HIGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse width 25 – ns t 14 MCE/ LOW to data c...

PCI and External Memory Interface Timing Diagrams 6-49 Figure 6.30 Slow Memory ( ≤ = 128 Kbytes) Write Cycle Table 6.34 Slow Memory ( ≤ 128 Kbytes) Write Cycle Symbol Parameter Min Max Unit t 11 Address setup to MAS/ HIGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse width 25 – ns...

6-50 Electrical Specifications Figure 6.31 ≤ 64 Kbytes ROM Read Cycle Table 6.35 ≤ = 64 Kbytes ROM Read Cycle Symbol Parameter Min Max Unit t 11 Address setup to MAS/ HIGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse width 25 – ns t 14 MCE/ LOW to data clocked in 150 – ns t 15 Ad...

PCI and External Memory Interface Timing Diagrams 6-51 Figure 6.32 ≤ 64 Kbyte ROM Write Cycle Table 6.36 ≤ = 64 Kbyte ROM Write Cycle Symbol Parameter Min Max Unit t 11 Address setup to MAS/ HIGH 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse width 25 – ns t 20 Data setup to MWE/ L...

6-52 Electrical Specifications 6.5 SCSI Timing Diagrams The tables and diagrams in this section describe the LSI53C875A SCSItimings. Figure 6.33 Initiator Asynchronous Send Table 6.37 Initiator Asynchronous Send Symbol Parameter Min Max Unit t 1 SACK/ asserted from SREQ/ asserted 5 – ns t 2 SACK/ de...

SCSI Timing Diagrams 6-53 Figure 6.34 Initiator Asynchronous Receive Table 6.38 Initiator Asynchronous Receive Symbol Parameter Min Max Unit t 1 SACK/ asserted from SREQ/ asserted 5 – ns t 2 SACK/ deasserted from SREQ/ deasserted 5 – ns t 3 Data setup to SREQ/ asserted 0 – ns t 4 Data hold from SACK...

6-54 Electrical Specifications Figure 6.35 Target Asynchronous Send Table 6.39 Target Asynchronous Send Symbol Parameter Min Max Unit t 1 SREQ/ deasserted from SACK/ asserted 5 – ns t 2 SREQ/ asserted from SACK/ deasserted 5 – ns t 3 Data setup to SREQ/ asserted 55 – ns t 4 Data hold from SACK/ asse...

SCSI Timing Diagrams 6-55 Figure 6.36 Target Asynchronous Receive Table 6.40 Target Asynchronous Receive Symbol Parameter Min Max Unit t 1 SREQ/ deasserted from SACK/ asserted 5 – ns t 2 SREQ/ asserted from SACK/ deasserted 5 – ns t 3 Data setup to SACK/ asserted 0 – ns t 4 Data hold from SREQ/ deas...

SCSI Timing Diagrams 6-57 Figure 6.37 Initiator and Target Synchronous Transfer SREQ/ or SACK/ Send Data SD[15:0]/, SDP[1:0]/ Receive Data SD[15:0]/, SDP[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 n n + 1 Valid n Valid n + 1 Valid n Valid n + 1

Package Diagrams 6-59 Figure 6.38 160-pin PQFP (P3) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain themost recent engineering drawings from your LSI Logic marketing representative byrequesting the outline drawing fo...

6-60 Electrical Specifications Table 6.44 160 PQFP Pin List by Location NC 121 NC 122 VSSIO 123 NC 124 NC 125 TEST_HSC/ 126 TEST_RST/ 127 VDDIO 128 VDDA 129 TCK 130 TRST/ 131 VSSA 132 VSSIO 133 NC 134 NC 135 MASN[1]/ 136 MASN[0]/ 137 VDDIO 138 MEW/ 139 MOE/ 140 MCE/ 141 TDI 142 SERR/ 143 RST/ 144 CL...

Package Diagrams 6-61 Figure 6.39 169-Pin BGA Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain themost recent engineering drawings from your LSI Logic marketing representative byrequesting the outline drawing for package code GV.

6-62 Electrical Specifications Table 6.45 169 BGA Pin List by Location VSSIO K12 SIO K13 PCI_AD[9] L1 PCI_AD[8] L2 PCI_AD[4] L3 PCI_AD[2] L4 VDDCORE L5 VSSCORE L6 MAD[7] L7 MAD[1] L8 GPIO[4] L9 MAC_TESTOUT/ L10VDDIO L11 VDDCORE L12 SD[10] L13 PCI_AD[7] M1 NC M2 PCI_AD[5] M3 NC M4 IRQ/ M5 SCLK M6 MAD...

LSI53C875A PCI to Ultra SCSI Controller A-1 Appendix ARegister Summary Table A.1 LSI53C875A PCI Register Map Register Name Address Read/Write Page Base Address Register One (MEMORY) 0x14–0x17 Read/Write 4-9 Base Address Register Two (SCRIPTS RAM) 0x18–0x1B Read/Write 4-10 Base Address Register Zero ...

Register Summary A-5 SCSI Interrupt Enable Zero (SIEN0) 0x40 Read/Write 4-73 SCSI Interrupt Status One (SIST1) 0x43 Read Only 4-78 SCSI Interrupt Status Zero (SIST0) 0x42 Read Only 4-76 SCSI Longitudinal Parity (SLPAR) 0x44 Read/Write 4-79 SCSI Output Control Latch (SOCL) 0x09 Read/Write 4-37 SCSI O...

LSI53C875A PCI to Ultra SCSI Controller B-1 Appendix BExternal MemoryInterface DiagramExamples Appendix B has example external memory interface diagrams. Figure B.1 16 Kbyte Interface with 200 ns Memory LSI53C875A 27C128 MOE/ OE MCE/ CE D0 8 MAD[7:0] Bus CK Q0 8 A[7:0] QE 6 A[13:8] V DD MAS0/ MAS1/ ...

B-2 External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory LSI53C875A 27C512-15/ MOE/ OE MCE/ CE D0 8 MAD[7:0] Bus CK Q0 8 A[7:0] QE 6 A[15:8] V DD MAS0/ MAS1/ Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 n...

LSI53C875A PCI to Ultra SCSI Controller IX-1 Index Symbols (64TIMOD) 4-97 (A7) 5-23 (AAP) 4-22 (ABRT) 4-40 , 4-48 (ACK) 4-37 , 4-39 (ADB) 4-23 (ADCK) 4-60 (ADDER) 4-73 (AESP) 4-24 (AIP) 4-43 (APS) 4-16 (ARB[1:0]) 4-20 (ART) 4-87 (ATN) 4-37 , 4-39 (AWS) 4-90 (BAR0) 4-9 (BAR1) 4-9 (BAR2) 4-10 (BBCK) 4...

Index IX-3 (SGE) 4-74 , 4-77 (SI) 4-51 (SID) 4-11 (SIEN0) 4-73 (SIEN1) 4-75 (SIGP) 4-49 , 4-54 (SIOM) 4-67 (SIP) 4-50 (SIR) 4-40 (SIST0) 4-76 (SIST1) 4-78 (SLB) 4-89 (SLPAR) 4-79 (SLPHBEN) 4-27 (SLPMD) 4-27 (SLT) 4-87 (SOCL) 4-37 (SODL) 4-94 (SOM) 4-88 (SOZ) 4-87 (SPL1) 4-47 (SRE) 4-30 (SRST) 4-48 (...

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