LSI Logic 53C810A - Manual - manualsarea.com

Page 3 - Preface; Audience

Preface iii Preface This book is the primary reference and technical manual for the LSI LogicLSI53C810A PCI to SCSI I/O Processor. It contains a completefunctional description for the product and includes complete physical andelectrical specifications. Audience This manual provides reference informa...

Page 4 - Chapter 6, Instruction Set of the I/O Processor

iv Preface • Chapter 6, Instruction Set of the I/O Processor , defines all of the SCSI SCRIPTS instructions that are supported by the LSI53C810A. • Chapter 7, Electrical Characteristics , contains the electrical characteristics and AC timings for the chip. • Appendix A, Register Summary , is a regis...

Page 5 - Conventions Used in This Manual; The word; Revision Record; Revision; Revised technical manual.

Preface v PCI Special Interest Group2575 N. E. KatherineHillsboro, OR 97214(800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 SCSI SCRIPTS™ Processors Programming Guide, Order NumberS14044.A Conventions Used in This Manual The word assert means to drive a signal true or active. The w...

Page 7 - Contents; Chapter 1

Contents vii Contents Chapter 1 General Description 1.1 TolerANT ® Technology 1-2 1.2 LSI53C810A Benefits Summary 1-3 1.2.1 SCSI Performance 1-3 1.2.2 PCI Performance 1-4 1.2.3 Integration 1-4 1.2.4 Ease of Use 1-4 1.2.5 Flexibility 1-5 1.2.6 Reliability 1-5 1.2.7 Testability 1-6 Chapter 2 Functiona...

Page 10 - Figures

x Contents Figures 1.1 LSI53C810A System Diagram 1-7 1.2 LSI53C810A Chip Block Diagram 1-8 2.1 DMA FIFO Sections 2-8 2.2 LSI53C810A Host Interface Data Paths 2-10 2.3 Active or Regulated Termination 2-12 2.4 Determining the Synchronous Transfer Rate 2-15 4.1 LSI53C810A Pin Diagram 4-2 4.2 Functional...

Page 11 - Tables

Contents xi 7.21 Target Asynchronous Send 7-29 7.22 Target Asynchronous Receive 7-30 7.23 Initiator and Target Synchronous Transfers 7-30 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2) 7-34 Tables 2.1 Bits Used for Parity Control and Observation 2-6 2.2 SCSI Parity Control 2-7 2.3 SCSI Pari...

Page 13 - LSI53C810A PCI to SCSI I/O Processor; Chapter 1 is divided into the following sections:

LSI53C810A PCI to SCSI I/O Processor 1-1 Chapter 1General Description Chapter 1 is divided into the following sections: • Section 1.1, “TolerANT ® Technology” • Section 1.2, “LSI53C810A Benefits Summary” The LSI53C810A PCI to SCSI I/O processor brings high-performance I/Osolutions to host adapter, w...

Page 14 - General Description; Technology; SCSI

1-2 General Description Software development tools are available to developers who use theSCSI SCRIPTS language to create customized SCSI softwareapplications. The LSI53C810A allows easy firmware upgrades and issupported by advanced SCRIPTS commands. 1.1 TolerANT ® Technology The LSI53C810A features...

Page 16 - Cache Line Size

1-4 General Description 1.2.2 PCI Performance To improve PCI performance, the LSI53C810A: • Bursts 2, 4, 8, or 16 Dwords across PCI bus with 80-byte DMA FIFO • Prefetches up to 8 Dwords of SCRIPTS instructions • Supports 32-bit word data bursts with variable burst lengths. • Bursts SCRIPTS opcode fe...

Page 21 - Chapter 2 is divided into the following sections:

LSI53C810A PCI to SCSI I/O Processor 2-1 Chapter 2Functional Description Chapter 2 is divided into the following sections: • Section 2.1, “SCSI Core” • Section 2.2, “SCRIPTS Processor” • Section 2.3, “Prefetching SCRIPTS Instructions” • Section 2.4, “PCI Cache Mode” • Section 2.5, “Parity Options” •...

Page 22 - Functional Description; SCRIPTS Processor

2-2 Functional Description and diagnostic procedures. In support of loopback diagnostics, the SCSIcore can perform a self-selection and operate as both an initiator and atarget. The SCSI core is controlled by the integrated SCRIPTS processorthrough a high-level logical interface. Commands controllin...

Page 23 - Chapter 6, “Instruction; Prefetching SCRIPTS Instructions; When enabled by setting the Prefetch Enable bit (bit 5) in the

Prefetching SCRIPTS Instructions 2-3 A complete set of development tools is available for writing customdrivers with SCSI SCRIPTS. For more information on SCSI SCRIPTSinstructions supported by the LSI53C810A, see Chapter 6, “Instruction Set of the I/O Processor.” 2.2.1 SDMS Software: The Total SCSI ...

Page 25 - Parity Options

Parity Options 2-5 Write and Invalidate are each software enabled or disabled to allow theuser full flexibility in using these commands. For more information on PCIcache mode operations, refer to Chapter 3, “PCI Functional Description.” 2.4.1 Load and Store Instructions The LSI53C810A supports the L...

Page 26 - Bits Used for Parity Control and Observation; BIt Name; SCSI Input

2-6 Functional Description Table 2.1 Bits Used for Parity Control and Observation BIt Name Location Description Assert SATN/ on ParityErrors SCSI ControlZero (SCNTL0) , Bit 1 Causes the LSI53C810A to automatically assert SATN/when it detects a parity error while operating as aninitiator. Enable Pari...

Page 27 - SCSI Parity Control; This table only applies when the Enable Parity Checking bit is set.

Parity Options 2-7 Table 2.2 SCSI Parity Control EPC AESP Description 0 0 Does not check for parity errors. Parity is generated when sendingSCSI data. Asserts odd parity when sending SCSI data. 0 1 Does not check for parity errors. Parity is generated when sendingSCSI data. Asserts even parity when ...

Page 28 - DMA FIFO Sections; shows how data is moved to/from the SCSI bus in each of the

2-8 Functional Description 2.5.1 DMA FIFO The DMA FIFO is divided into four sections, each one byte wide and20 transfers deep. The DMA FIFO is illustrated in Figure 2.1 . Figure 2.1 DMA FIFO Sections 2.5.1.1 Data Paths The data path through the LSI53C810A is dependent on whether data isbeing moved i...

Page 29 - Asynchronous SCSI Send –; Synchronous SCSI Send –; SCSI Output Data Latch; Asynchronous SCSI Receive –

Parity Options 2-9 Asynchronous SCSI Send – Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC) registers and calculate if there are bytes left in the DMA FIFO.To make this calculation, subtract the seven least significant bitsof the DMA Byte Counter (DBC) register from the 7-bit value o...

Page 30 - SCSI Input Data Latch; Synchronous SCSI Receive –; DMA Byte; LSI53C810A Host Interface Data Paths

2-10 Functional Description Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) register to determine if any bytes are left in the SCSI Input Data Latch (SIDL) register. If bit 7 is set in SSTAT0, then the SCSI Input Data Latch (SIDL) register is full. Synchronous SCSI Receive – Step 1. Subtract the...

Page 31 - SCSI Bus Interface; SE cables can use a 220

SCSI Bus Interface 2-11 2.6 SCSI Bus Interface The LSI53C810A supports SE operation only. All SCSI signals are activeLOW. The LSI53C810A contains the SE output drivers and can beconnected directly to the SCSI bus. Each output is isolated from thepower supply to ensure that a powered-down LSI53C810A ...

Page 32 - bits 5 and 6, respectively) should both be asserted; Active or Regulated Termination

2-12 Functional Description Once a change in operating mode occurs, the initiator SCRIPTS shouldstart with a Set Initiator instruction or the target SCRIPTS should startwith a Set Target instruction. The Selection and Reselection Enable bits( SCSI Chip ID (SCID) bits 5 and 6, respectively) should bo...

Page 33 - register controls

SCSI Bus Interface 2-13 2.6.3 Synchronous Operation The LSI53C810A can transfer synchronous SCSI data in both theinitiator and target modes. The SCSI Transfer (SXFER) register controls both the synchronous offset and the transfer period. It may be loaded bythe CPU before SCRIPTS execution begins, fr...

Page 35 - Determining the Synchronous Transfer Rate; Interrupt Handling

Interrupt Handling 2-15 Figure 2.4 Determining the Synchronous Transfer Rate 2.7 Interrupt Handling The SCRIPTS processor in the LSI53C810A performs most functionsindependently of the host microprocessor. However, certain interruptsituations must be handled by the external microprocessor. This secti...

Page 36 - SCSI Interrupt Status Zero; SIST0 and SIST1 – The

2-16 Functional Description that could be used for other system tasks. The preferred method ofdetecting interrupts in most systems is hardware interrupts. In this case,the LSI53C810A asserts the Interrupt Request (IRQ/) line that interruptsthe microprocessor, causing the microprocessor to execute an...

Page 37 - Chip Test Three; DSTAT – The; DIEN – The

Interrupt Handling 2-17 If the LSI53C810A is sending data to the SCSI bus and a fatal SCSIinterrupt condition occurs, data could be left in the DMA FIFO. Becauseof this the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) should be checked. If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF ...

Page 38 - Interrupt Status

2-18 Functional Description 2.7.1.2 Fatal vs. Nonfatal Interrupts A fatal interrupt, as the name implies, always causes SCRIPTS to stoprunning. All nonfatal interrupts become fatal when they are enabled bysetting the appropriate interrupt enable bit. Interrupt masking isdiscussed in Section 2.7.1.3,...

Page 39 - SCSI Interrupt

Interrupt Handling 2-19 whether polling or hardware interrupts are being used; whether theinterrupt is fatal or nonfatal; and whether the chip is operating in theInitiator or Target mode. If a nonfatal interrupt is masked and that condition occurs, the SCRIPTSdo not stop, the appropriate bit in the ...

Page 40 - SCSI Interrupt Status

2-20 Functional Description interrupts are cleared, all the interrupts that came in afterward move intoSIST0, SIST1, and DSTAT. After the first interrupt is cleared by readingthe appropriate register, the IRQ/ pin is deasserted for a minimum ofthree CLKs; the stacked interrupts move into SIST0, SIST...

Page 41 - DMA

Interrupt Handling 2-21 • If the DMA direction is a write to memory and a SCSI interruptoccurs, the LSI53C810A attempts to flush the DMA FIFO to memorybefore halting. Under any other circumstances only the current cycleis completed before halting, so the DFE bit in DMA Status (DSTAT) should be check...

Page 43 - Chapter 3 is divided into the following sections:

LSI53C810A PCI to SCSI I/O Processor 3-1 Chapter 3PCI FunctionalDescription Chapter 3 is divided into the following sections: • Section 3.1, “PCI Addressing” • Section 3.2, “PCI Cache Mode” • Section 3.3, “Configuration Registers” 3.1 PCI Addressing There are three types of PCI-defined address space...

Page 44 - PCI Functional Description; area this device occupies.; PCI Bus Commands and Functions Supported

3-2 PCI Functional Description The LSI53C810A operating registers are available in both the upper andlower 128-byte portions of the 256-byte space selected. At initialization time, each PCI device is assigned a base address formemory and I/O accesses. In the case of the LSI53C810A, the upper24 bits ...

Page 45 - PCI Cache Mode; The LSI53C810A supports the PCI specification for an 8-bit; Support for PCI Cache Line Size Register; The LSI3C810A supports the PCI specification for an 8-bit

PCI Cache Mode 3-3 3.1.2.3 Memory Read Command The Memory Read reads data from an agent mapped in memoryaddress space. All 32 address bits are decoded. 3.1.2.4 Memory Read Multiple Command The Memory Read Multiple command reads data from an agent mappedin memory address space. All 32 address bits ar...

Page 46 - register and the PCI

3-4 PCI Functional Description 3.2.2 Selection of Cache Line Size The cache logic selects a cache line size based on the values for theburst size in the DMA Mode (DMODE) register and the PCI Cache Line Size register. Note: The LSI53C810A does not automatically use the value inthe PCI Cache Line Size...

Page 48 - ) resembles the Write and Invalidate mode in

3-6 PCI Functional Description finish the transfer at a later time using another bus ownership. If the chipis transferring multiple cache lines it continues to transfer until the nextcache boundary is reached. PCI Target Retry – During a Write and Invalidate transfer, if the targetdevice issues a re...

Page 50 - burst size settings for the Read Multiple

3-8 PCI Functional Description When these conditions are met, the chip issues a Read Multiplecommand instead of a Memory Read during all PCI read cycles. Burst Size Selection – The Read Multiple command reads in multiplecache lines of data in a single bus ownership. The number of cache linesto read ...

Page 51 - Configuration Registers; The operating registers can be; PCI Bus Commands and Encoding Types; Supported as Master Supported as Slave

Configuration Registers 3-9 3.3 Configuration Registers The Configuration registers are accessible only by system BIOS duringPCI configuration cycles, and are not available to the user at any time.No other cycles, including SCRIPTS operations, can access theseregisters. The lower 128 bytes hold conf...

Page 52 - For detailed information, refer to the PCI Specification.; PCI Configuration Register Map; zeros when read. Reserved registers also return zeros when read.

3-10 PCI Functional Description Note: The configuration register descriptions are provided forgeneral information only, to indicate which PCIconfiguration addresses are supported in the LSI53C810A. For detailed information, refer to the PCI Specification. All PCI-compliant devices, such as the LSI53...

Page 53 - Configuration Registers; VID

Configuration Registers 3-11 Register: 0x00 Vendor IDRead Only VID Vendor ID [15:0] This field identifies the manufacturer of the device. TheVendor ID is 0x1000. Register: 0x02 Device IDRead Only DID Device ID [15:0] This field identifies the particular device. TheLSI53C810A device ID is 0x0001. Reg...

Page 54 - To enable Write and Invalidate

3-12 PCI Functional Description R Reserved [15:9] SE SERR/ Enable 8 This bit enables the SERR/ driver. SERR/ is disabledwhen this bit is cleared. The default value of this bit iszero. This bit and bit 6 must be set to report addressparity errors. R Reserved 7 EPER Enable Parity Error Response 6 This...

Page 55 - EIS; Base Address Zero; DPE

Configuration Registers 3-13 EIS Enable I/O Space 0 This bit controls the LSI53C810A’s response to I/O spaceaccesses. A value of zero disables the response. A valueof one allows the LSI53C810A to respond to I/O spaceaccesses at the address specified in Base Address Zero (I/O) . Register: 0x06 Status...

Page 56 - RTA; Fast

3-14 PCI Functional Description RTA Received Target Abort (from Master) 12 A master device should set this bit whenever itstransaction is terminated with a target abort. All masterdevices should implement this bit. R Reserved 11 DT[1:0] DEVSEL/ Timing [10:9] These bits encode the timing of DEVSEL/. ...

Page 58 - Latency Timer

3-16 PCI Functional Description Register: 0x0C Cache Line SizeRead/Write CLS Cache Line Size [7:0] This register specifies the system cache line size in unitsof 32-bit words. Cache mode is enabled and disabled bythe Cache Line Size Enable (CLSE) bit, bit 7 in the DMA Control (DCNTL) register. Settin...

Page 63 - is the pin diagram

LSI53C810A PCI to SCSI I/O Processor 4-1 Chapter 4Signal Descriptions This chapter presents the LSI53C810A pin configuration and signaldefinitions using tables and illustrations. Figure 4.1 is the pin diagram and Figure 4.2 is a functional signal grouping. The pin definitions are presented in Table ...

Page 64 - Signal Descriptions

4-2 Signal Descriptions Figure 4.1 LSI53C810A Pin Diagram A slash (/) at the end of the signal name indicates that the active stateoccurs when the signal is at a LOW voltage. When the slash is absent,the signal is active at a HIGH voltage. AD21 V DD -I V SS -I AD16 FRAME/ DEVSEL/ STOP/ V SS -I V SS ...

Page 65 - Power and Ground Signals; Name; Power supplies to the internal logic core.; pins must be supplied 5 V.

4-3 Signals are assigned a type. There are four signal types: Table 4.1 describes the Power and Ground Signals group. I Input, a standard input only signal. O Output, a standard output driver (typically a Totem Pole Output). T/S 3-state, a bidirectional, 3-state input/output signal. S/T/S Sustained ...

Page 66 - Functional Signal Grouping

4-4 Signal Descriptions Figure 4.2 Functional Signal Grouping CLKRST AD[31:0]C_BE/[3:0]PAR FRAME/TRDY/IRDY/STOP/DEVSEL/IDSEL REQ/GNT/ SERR/ PERR/ GPIO0_FETCH/ GPIO1_MASTER/ MAC/_TESTOUT IRQ/ System Address and Data Interface Control Arbitration Error Reporting SCSI SCLK SD[7:0] SDP SCTRL/ Additional...

Page 67 - PCI Bus Interface Signals; describes the System Signals group.; System Signals; CLK

PCI Bus Interface Signals 4-5 4.1 PCI Bus Interface Signals The PCI signal definitions are organized into the following functionalgroups: Power and Ground Signals , System Signals , Address and Data Signals , Interface Control Signals , Arbitration Signals , and Error Reporting Signals . 4.1.1 Syste...

Page 68 - describes the Address and Data Signals group.; Address and Data Signals

4-6 Signal Descriptions 4.1.2 Address and Data Signals Table 4.3 describes the Address and Data Signals group. Table 4.3 Address and Data Signals Name Pin No. Type Description AD[31:0] 85, 86, 88, 89,91, 92, 94, 95,98, 100, 1, 2, 4,6, 7, 8, 23, 24,25, 27, 29, 30,31, 33, 35, 36,38, 39, 41, 42,44, 45 ...

Page 69 - describes the Interface Control Signals group.; Interface Control Signals; IDSEL

PCI Bus Interface Signals 4-7 4.1.3 Interface Control Signals Table 4.4 describes the Interface Control Signals group. Table 4.4 Interface Control Signals Name Pin No. Type Description FRAME/ 11 S/T/S Cycle Frame is driven by the current master to indicate the beginningand duration of an access. FRA...

Page 70 - describes the Arbitration Signals group.; Arbitration Signals

4-8 Signal Descriptions 4.1.4 Arbitration Signals Table 4.5 describes the Arbitration Signals group. 4.1.5 Error Reporting Signals Table 4.6 describes the Error Reporting Signals group. Table 4.5 Arbitration Signals Name Pin No. Type Strength Description REQ/ 200, A4 O 16 mA PCI Request indicates to...

Page 71 - SCSI Bus Interface Signals; SCSI Bus Interface Signals

SCSI Bus Interface Signals 4-9 4.2 SCSI Bus Interface Signals The SCSI signal definitions are organized into the following functionalgroups: SCSI Bus Interface Signals and Additional Interface Signals . 4.2.1 SCSI Bus Interface Signals Table 4.7 describes the SCSI Bus Interface Signals group. Table ...

Page 72 - describes the Additional Interface Signals group.; Additional Interface Signals; operating register, at

4-10 Signal Descriptions 4.2.2 Additional Interface Signals Table 4.8 describes the Additional Interface Signals group. Table 4.8 Additional Interface Signals Name Pin No. Type Description TESTIN/ 52 I Test In. When this pin is driven LOW, the LSI53C810A connects allinputs and outputs to an “AND tre...

Page 75 - This chapter describes all LSI53C810A operating registers.

LSI53C810A PCI to SCSI I/O Processor 5-1 Chapter 5Operating Registers This chapter describes all LSI53C810A operating registers. Table 5.1 , the register map, lists registers by operating and configuration addresses.The terms “set” and “assert” are used to refer to bits that areprogrammed to a binar...

Page 76 - Operating Registers; Register Address Map

5-2 Operating Registers Figure 5.1 Register Address Map Register: 0x00 (0x80) SCSI Control Zero (SCNTL0)Read/Write 31 16 15 0 Mem I/O Config SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 0x80 GPREG SDID SXFER SCID 0x04 0x84 SBCL SSID SOCL SFBR 0x08 0x88 SSTAT2 SSTAT1 SSTAT0 DSTAT 0x0C 0x8C DSA 0x10 0x90 Reserved...

Page 77 - SCSI Output Control Latch; Arbitration Mode; Simple arbitration

5-3 ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6] Simple Arbitration 1. The LSI53C810A waits for a bus free condition tooccur. 2. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus. If the SSEL/ signal is asserted by another SCSIdevice, the LSI53C810A d...

Page 78 - SCSI Status Zero; START; SCSI Control; WATN

5-4 Operating Registers 4. The LSI53C810A repeats arbitration until it winscontrol of the SCSI bus. When it wins, the WonArbitration bit is set in the SCSI Status Zero (SSTAT0) register, bit 2. 5. The LSI53C810A performs selection by assertingthe following onto the SCSI bus: SSEL/, the target’sID (s...

Page 80 - register onto the

5-6 Operating Registers Register: 0x01 (0x81) SCSI Control One (SCNTL1)Read/Write EXC Extra Clock Cycle of Data Setup 7 When this bit is set, an extra clock period of data setupis added to each SCSI data transfer. The extra data setuptime can provide additional system design margin, thoughit affects...

Page 82 - register. Then one of two things eventually happens:; SST

5-8 Operating Registers bit is cleared automatically when the selection orreselection sequence is completed, or times out.Interrupts do not occur until after this bit is reset. An unexpected disconnect condition clears IARB withoutit attempting arbitration. See the SCSI DisconnectUnexpected bit ( SC...

Page 83 - output of this divider is always divided by 4 and that value

5-9 Register: 0x02 (0x82) SCSI Control Two (SCNTL2)Read/Write SDU SCSI Disconnect Unexpected 7 This bit is valid in the initiator mode only. When this bit isset, the SCSI core is not expecting the SCSI bus to enterthe Bus Free phase. If it does, an unexpected disconnecterror is generated (see the Un...

Page 84 - . All other combinations are; Synchronous Clock Conversion Factor; Factor Frequency; Reserved

5-10 Operating Registers determines the transfer rate. For example, if SCLK is40 MHz and the SCF value is set to divide by one, thenthe maximum synchronous receive rate is 10 Mbytes/s((40/1) /4 = 10). For synchronous send, the output of this divider getsdivided by the transfer period (XFERP) bits in...

Page 87 - SCSI clock

5-13 Use the following formula to calculate the synchronoussend and receive rates. Table 5.3 and Table 5.4 show examples of possible bit combinations. Synchronous Send Rate = (SCLK/SCF)/XFERPSynchronous Receive Rate = (SCLK/SCF) /4 Where: TP2 TP1 TP0 XFERP 0 0 0 4 0 0 1 5 0 1 0 6 0 1 1 7 1 0 0 8 1 0...

Page 88 - describes the possible combinations and

5-14 Operating Registers R Reserved 4 MO[3:0] Max SCSI Synchronous Offset [3:0] These bits describe the maximum SCSI synchronousoffset used by the LSI53C810A when transferringsynchronous SCSI data in either the initiator or targetmode. Table 5.5 describes the possible combinations and their relation...

Page 89 - Synchronous Offset

5-15 the LSI53C810A. These bits determine theLSI53C810A’s method of transfer for Data-In andData-Out phases only; all other information transfersoccur asynchronously. Register: 0x06 (0x86) SCSI Destination ID (SDID)Read/Write R Reserved [7:3] ENC[2:0] Encoded destination SCSI ID [2:0] Writing these ...

Page 90 - These bits are programmed through the

5-16 Operating Registers Register: 0x07 (0x87) General Purpose (GPREG)Read/Write R Reserved [7:2] GPIO[1:0] General Purpose [1:0] These bits are programmed through the General Purpose Pin Control (GPCNTL) register as inputs, outputs, or to perform special functions. These signals can also beprogramm...

Page 92 - is used only when

5-18 Operating Registers Register: 0x09 (0x89) SCSI Output Control Latch (SOCL)Read/Write REQ Assert SCSI REQ/ Signal 7 ACK Assert SCSI ACK/ Signal 6 BSY Assert SCSI BSY/ Signal 5 SEL Assert SCSI SEL/ Signal 4 ATN Assert SCSI ATN/ Signal 3 MSG Assert SCSI MSG/ Signal 2 C/D Assert SCSI C_D/ Signal 1 ...

Page 96 - This bit is set when the

5-22 Operating Registers R Reserved 1 IID Illegal Instruction Detected 0 This status bit is set any time an illegal instruction isdetected, whether the LSI53C810A is operating insingle step mode or automatically executing SCSISCRIPTS. Any of the following conditions during instructionexecution also ...

Page 98 - FIFO Flags; SCSI Input Data; Bytes or Words in

5-24 Operating Registers Register: 0x0E (0x8E) SCSI Status One (SSTAT1)Read Only FF[3:0] FIFO Flags [7:4] These four bits define the number of bytes that currentlyreside in the LSI53C810A’s SCSI synchronous dataFIFO. These bits are not latched and they will change asdata moves through the FIFO. The ...

Page 99 - . It allows the user to

5-25 MSG SCSI MSG/ Signal 2 C/D SCSI C_D/ Signal 1 I/O SCSI I_O/ Signal 0 These three SCSI phase status bits (MSG, C/D, and I/O)are latched on the asserting edge of SREQ/ whenoperating in either initiator or target mode. These bits areset when the corresponding signal is active. They areuseful when ...

Page 100 - DSA; Chapter 2, “Functional; ABRT

5-26 Operating Registers Registers: 0x10–0x13 (0x90–0x93) Data Structure Address (DSA)Read/Write DSA Data Structure Address [31:0] This 32-bit register contains the base address used for alltable indirect calculations. The DSA register is usuallyloaded prior to starting an I/O, but it is possible fo...

Page 102 - CON; SIP; An arbitration sequence completes

5-28 Operating Registers also notify the LSI53C810A of a predefined condition andthe SCRIPTS processor may take action while SCRIPTSare executing. CON Connected 3 This bit is automatically set any time the LSI53C810A isconnected to the SCSI bus as an initiator or as a target.It is set after successf...

Page 104 - Byte Empty in DMA FIFO

5-30 Operating Registers Register: 0x19 (0x99) Chip Test One (CTEST1)Read Only FMT[3:0] Byte Empty in DMA FIFO [7:4] These bits identify the bottom bytes in the DMA FIFO thatare empty. Each bit corresponds to a byte lane in theDMA FIFO. For example, if byte lane three is empty, thenFMT3 will be set....

Page 110 - FIFO Byte Control; Chip Test Six; BBCK; DMA FIFO; Disabled

5-36 Operating Registers FBL[2:0] FIFO Byte Control [2:0] These bits steer the contents of the Chip Test Six (CTEST6) register to the appropriate byte lane of the 32-bit DMA FIFO. If the FBL2 bit is set, then FBL1 andFBL0 determine which of four byte lanes can be read orwritten. When cleared, the by...

Page 114 - DMA SCRIPTS Pointer

5-40 Operating Registers the first SCRIPTS instruction is written to this register,SCRIPTS instructions are automatically fetched andexecuted until an interrupt condition occurs. In single step mode, there is a single step interrupt aftereach instruction is executed. The DMA SCRIPTS Pointer (DSP) re...

Page 116 - Chip Test; Burst Length

5-42 Operating Registers SIOM Source I/O Memory Enable 5 This bit is defined as an I/O Memory Enable bit for thesource address of a Memory Move or Block MoveCommand. If this bit is set, then the source address is inI/O space; and if cleared, then the source address is inmemory space. This function i...

Page 118 - For more information on interrupts, see

5-44 Operating Registers Register: 0x39 (0xB9) DMA Interrupt Enable (DIEN)Read/Write This register contains the interrupt mask bits corresponding to theinterrupting conditions described in the DMA Status (DSTAT) register. An interrupt is masked by clearing the appropriate mask bit. Masking aninterru...

Page 121 - COM

5-47 assert. As with any register other than Interrupt Status (ISTAT) , this register cannot be accessed except by a SCRIPTS instruction during SCRIPTS execution. COM LSI53C700 Family Compatibility 0 When this bit is cleared, the LSI53C810A behaves in amanner compatible with the LSI53C700 family;sel...

Page 124 - SCSI Interrupt Status One

5-50 Operating Registers Register: 0x41 (0xC1) SCSI Interrupt Enable One (SIEN1)Read/Write This register contains the interrupt mask bits corresponding to theinterrupting conditions described in the SCSI Interrupt Status One (SIST1) register. An interrupt is masked by clearing the appropriate mask b...

Page 125 - CMP

5-51 Register: 0x42 (0xC2) SCSI Interrupt Status Zero (SIST0)Read Only Reading the SCSI Interrupt Status Zero (SIST0) register returns the status of the various interrupt conditions, whether they are enabled in the SCSI Interrupt Enable Zero (SIEN0) register or not. Each bit set indicates an occurre...

Page 126 - the

5-52 Operating Registers SEL Selected 5 This bit is set when the LSI53C810A is selected byanother SCSI device. The Enable Response to Selectionbit must be set in the SCSI Chip ID (SCID) register (and the Response ID (RESPID) register must hold the chip’s ID) for the LSI53C810A to respond to selectio...

Page 127 - RST

5-53 when the LSI53C810A operates in the initiator mode.When the LSI53C810A operates in low level mode, anydisconnect causes an interrupt, even a valid SCSIdisconnect. This bit is also set if a selection time-outoccurs (it may occur before, at the same time, or stackedafter the STO interrupt, since ...

Page 129 - SCSI Longitudinal; Chip Type; Data Bytes

5-55 A one in any bit position of the final SCSI Longitudinal Parity (SLPAR) value would indicate a transmission error. The SCSI Longitudinal Parity (SLPAR) register is also used to generate the check bytes for SCSI sendoperations. If the SCSI Longitudinal Parity (SLPAR) register contains all zeros ...

Page 130 - This register is used to determine if the pins controlled by the

5-56 Operating Registers When bits 3 through 0 are set, the corresponding accessis considered local and the MAC/_TESTOUT pin is drivenhigh. When these bits are cleared, the correspondingaccess is to far memory and the MAC/_TESTOUT pin isdriven low. This function is enabled after a TransferControl SC...

Page 131 - Minimum Timeout

5-57 FE Fetch Enable 6 The internal opcode fetch signal is presented on GPIO0if this bit is set, regardless of the state of bit 0(GPIO0_EN). R Reserved 5 GPIO_EN[1:0] GPIO Enable [1:0] These bits power up set, causing the GPIO1 and GPIO0pins to become inputs. Resetting these bits causesGPIO[1:0] to ...

Page 132 - SEL; s selection abort; These values are correct if the CCF bits in the

5-58 Operating Registers SEL Selection Time-Out [3:0] These bits select the SCSI selection/reselection time-outperiod. When this timing (plus the 200 µ s selection abort time) is exceeded, the STO bit in the SCSI Interrupt Sta- tus One (SIST1) register is set. For a more detailed explanation of inte...

Page 133 - SCSI Timer Zero; RESPID; SCSI Chip ID

5-59 GEN bit in the SCSI Interrupt Status One (SIST1) register is set. Refer to the table under SCSI Timer Zero (STIME0) , bits [3:0], for the available time-out periods. Note: To reset a timer before it expires and obtain repeatabledelays, the time value must be written to zero first, and thenwritt...

Page 135 - register. This bit is not

5-61 SOM SCSI Synchronous Offset Maximum 0 This bit indicates that the current synchronousSREQ/SACK offset is the maximum specified by bits [3:0]in the SCSI Transfer (SXFER) register. This bit is not latched and may change at any time. It is used in lowlevel synchronous SCSI operations. When this bi...

Page 136 - and

5-62 Operating Registers Register: 0x4E (0xCE) SCSI Test Two (STEST2)Read/Write SCE SCSI Control Enable 7 Setting this bit allows assertion of all SCSI control anddata lines through the SCSI Output Control Latch (SOCL) and SCSI Output Data Latch (SODL) registers regardless of whether the LSI53C810A ...

Page 138 - register are set, the

5-64 Operating Registers LSI53C810A is in an information transfer phase.TolerANT active negation should be enabled to improvesetup and deassertion times at fast SCSI timings. Activenegation is disabled after reset or when this bit is cleared.For more information on TolerANT technology, refer to Chap...

Page 139 - STW; SCSI Output Data

5-65 SCSI Input Data Latch (SIDL) , SCSI Output Data Latch (SODL) , and SODR full bits in the SCSI Status Zero (SSTAT0) register are cleared. STW SCSI FIFO Test Write 0 Setting this bit places the SCSI core into a test mode inwhich the FIFO is easily written. While this bit is set,writes to the SCSI...

Page 141 - This chapter is divided into the following sections:; Low Level Register Interface Mode

LSI53C810A PCI to SCSI I/O Processor 6-1 Chapter 6Instruction Set of theI/O Processor This chapter is divided into the following sections: • Section 6.1, “Low Level Register Interface Mode” • Section 6.2, “SCSI SCRIPTS” • Section 6.3, “Block Move Instructions” • Section 6.4, “I/O Instruction” • Sect...

Page 142 - Instruction Set of the I/O Processor; register

6-2 Instruction Set of the I/O Processor 6.2 SCSI SCRIPTS To operate in the SCSI SCRIPTS mode, the LSI53C810A requires onlya SCRIPTS start address. The start address must be at a Dword (fourbyte) boundary. This aligns subsequent SCRIPTS at a Dword boundarysince all SCRIPTS are 8 or 12 bytes long. Al...

Page 143 - SCSI SCRIPTS; SCRIPTS Instructions; Instruction; Block Move

SCSI SCRIPTS 6-3 Each instruction consists of two or three 32-bit words. The first 32-bitword is always loaded into the DMA Command (DCMD) and DMA Byte Counter (DBC) registers, the second into the DMA SCRIPTS Pointer Save (DSPS) register. The third word, used only by Memory Move instructions, is loa...

Page 144 - register. Execution of

6-4 Instruction Set of the I/O Processor • The LSI53C810A typically fetches two Dwords (64 bits) and decodesthe high order byte of the first Dword as a SCRIPTS instruction. Ifthe instruction is a Block Move, the lower three bytes of the firstDword are stored and interpreted as the number of bytes to...

Page 145 - SCRIPTS Overview; Block Move Instructions; illustrates the register bit values that represent a

Block Move Instructions 6-5 Figure 6.1 SCRIPTS Overview 6.3 Block Move Instructions The Block Move SCRIPTS instruction is used to move data between theSCSI bus and memory. For a Block Move instruction, the LSI53C810Aoperates much like a chaining DMA device with a SCSI controllerattached. Figure 6.2 ...

Page 146 - register using

6-6 Instruction Set of the I/O Processor 6.3.1 First Dword IT[1:0] Instruction Type - Block Move [31:30] IA Indirect Addressing 29 When this bit is cleared, user data is moved to or fromthe 32-bit data start address for the Block Moveinstruction. The value is loaded into the chip’s addressregister a...

Page 147 - TIA; register, to fetch first the; Command

Block Move Instructions 6-7 Note: Do not use indirect and table indirect addressingsimultaneously; use only one addressing method at a time. TIA Table Indirect Addressing 28 When this bit is set, the 24-bit signed value in the startaddress of the move is treated as a relative displacementfrom the va...

Page 148 - Block Move Instruction Register; Data Structure Address; DSPS Register

6-8 Instruction Set of the I/O Processor Figure 6.2 Block Move Instruction Register Prior to the start of an I/O, the Data Structure Address (DSA) register should be loaded with the base address of the I/O data structure. The address may be any addresson a Dword boundary. After a Table Indirect opco...

Page 149 - OpCode; Byte Count; OPC; MOVE

Block Move Instructions 6-9 SCRIPTS can directly execute operating system I/O datastructures, saving time at the beginning of an I/Ooperation. The I/O data structure can begin on any Dwordboundary and may cross system segment boundaries. There are two restrictions on the placement of pointerdata in ...

Page 150 - Initiator Mode

6-10 Instruction Set of the I/O Processor – If any other Group Code is received, the DMA Byte Counter (DBC) register is not modified and the LSI53C810A will request the number of bytesspecified in the DMA Byte Counter (DBC) register. If the DMA Byte Counter (DBC) register contains 0x000000, an illeg...

Page 151 - SCSI Status One; SCSI Phase

Block Move Instructions 6-11 3. The LSI53C810A compares the SCSI phase bits in the DMA Command (DCMD) register with the latched SCSI phase lines stored in the SCSI Status One (SSTAT1) register. These phase lines are latched when SREQ/ is asserted. 4. If the SCSI phase bits match the value stored in ...

Page 152 - Transfer Counter; register is; Start Address; LSI53C810A transfers data to or from memory, the

6-12 Instruction Set of the I/O Processor TC[23:0] Transfer Counter [23:0] This 24-bit field specifies the number of data bytes to bemoved between the LSI53C810A and system memory.The field is stored in the DMA Byte Counter (DBC) register. When the LSI53C810A transfers data to/frommemory, the DMA By...

Page 153 - Instruction Defined; Reselect

I/O Instruction 6-13 indirect addressing, the value in this field is an offset intoa table pointed to by the Data Structure Address (DSA) . The table entry contains byte count and addressinformation. 6.4 I/O Instruction The I/O SCRIPTS instruction causes the LSI53C810A to trigger commonSCSI hardware...

Page 154 - Reselect Instruction

6-14 Instruction Set of the I/O Processor Reselect Instruction 1. The LSI53C810A arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCSI Chip ID (SCID) register. If it loses arbitration, it tries again during the next available arbitration cycle withoutreporting any lost arbitration ...

Page 155 - Wait Select Instruction

I/O Instruction 6-15 Wait Select Instruction 1. If the LSI53C810A is selected, it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register. 2. If reselected, the LSI53C810A fetches the next instruction from the address pointed to by the 32-bitjump address fi...

Page 156 - illustrates the register bit values that represent an I/O; I/O Instruction Register

6-16 Instruction Set of the I/O Processor Figure 6.3 illustrates the register bit values that represent an I/O instruction. Figure 6.3 I/O Instruction Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 ...

Page 157 - SCSI Control Zero; Select

I/O Instruction 6-17 Clear InstructionWhen the SACK/ or SATN/ bits are cleared, thecorresponding bits are cleared in the SCSI Output Con- trol Latch (SOCL) register. Do not set SACK/ or SATN/ except for testing purposes. When the target bit iscleared, the corresponding bit in the SCSI Control Zero (...

Page 158 - Wait Disconnect Instruction

6-18 Instruction Set of the I/O Processor field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C810A to Initiator mode if it isreselected, or to Target mode if it is selected. 4. If the Select with SATN/ field is set, the SATN/ signal is asserted during the selection phase. Wa...

Page 159 - TI

I/O Instruction 6-19 Clear InstructionWhen the SACK/or SATN/ bits are cleared, thecorresponding bits are cleared in the SCSI Output Con- trol Latch (SOCL) register. When the target bit is cleared, the corresponding bit in the SCSI Control Zero (SCNTL0) register is cleared. When the Carry bit is clea...

Page 162 - ACK

6-22 Instruction Set of the I/O Processor ACK Set/Clear SACK/ 6 ATN Set/Clear SATN/ 3 These two bits are used in conjunction with a Set or Clearinstruction to assert or deassert the corresponding SCSIcontrol signal. Bit 6 controls the SCSI SACK/ signal. Bit 3controls the SCSI SATN/ signal. Setting e...

Page 163 - Read/Write Instructions; Instruction Type - Read/Write Instruction; Operator; for field definitions.; Destination Address

Read/Write Instructions 6-23 6.5 Read/Write Instructions The Read/Write instruction type moves the contents of one register toanother, or performs arithmetic operations such as AND, OR, XOR,Addition, and Shift. 6.5.1 First Dword IT[1:0] Instruction Type - Read/Write Instruction [31:30] The Read/Writ...

Page 165 - illustrates the register bit values that represent a Read/Write; Read/Write Register Instruction

Read/Write Instructions 6-25 Figure 6.4 illustrates the register bit values that represent a Read/Write instruction. Figure 6.4 Read/Write Register Instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 ...

Page 167 - Transfer Control Instructions; SCSI First Byte

Transfer Control Instructions 6-27 Miscellaneous Notes: ˘ Substitute the desired register name or address for “RegA” in the syntax examples.˘ data8 indicates eight bits of data. 6.6 Transfer Control Instructions The Transfer Control, or Conditional Jump, instruction allows you to writeSCRIPTS that m...

Page 170 - illustrates the register bit values that represent a Transfer; Transfer Control Instruction

6-30 Instruction Set of the I/O Processor Figure 6.5 illustrates the register bit values that represent a Transfer Control instruction. Figure 6.5 Transfer Control Instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 172 - When this bit is set, the 24-bit signed value in the; MSG

6-32 Instruction Set of the I/O Processor RA Relative Addressing Mode 23 When this bit is set, the 24-bit signed value in the DMA SCRIPTS Pointer Save (DSPS) register is used as a relative offset from the current DMA SCRIPTS Pointer (DSP) address (which is pointing to the next instruction, not the o...

Page 173 - Action

Transfer Control Instructions 6-33 A relative transfer can be to any address within a16 Mbyte segment. The program counter is combinedwith the 24-bit signed offset (using addition orsubtraction) to form the new execution address. SCRIPTS programs may contain a mixture of directjumps and relative jum...

Page 174 - data byte is

6-34 Instruction Set of the I/O Processor CD Compare Data 18 When this bit is set, the first byte received from the SCSIdata bus (contained in SCSI First Byte Received (SFBR) register) is compared with the Data to be Compared Fieldin the Transfer Control instruction. The Wait for ValidPhase bit cont...

Page 175 - Second Dword; Jump Address; register and becomes the current instruction pointer.

Transfer Control Instructions 6-35 6.6.2 Second Dword Jump Address [31:0] This 32-bit field contains the address of the nextinstruction to fetch when a jump is taken. Once theLSI53C810A has fetched the instruction from the addresspointed to by these 32 bits, this address is incrementedby 4, loaded i...

Page 176 - Memory Move Instructions; For Memory Move instructions, bits 5 and 4 (SIOM and DIOM) in the

6-36 Instruction Set of the I/O Processor 6.7 Memory Move Instructions This SCRIPTS instruction allows the LSI53C810A to executehigh-performance block moves of 32-bit data from one part of mainmemory to another. In this mode, the LSI53C810A is an independent,high-performance DMA controller irrespect...

Page 177 - Memory Move Instructions; illustrates the register bit values that represent a Memory; Memory to Memory Move Instruction; TEMP Register

Memory Move Instructions 6-37 Figure 6.6 illustrates the register bit values that represent a Memory Move instruction. Figure 6.6 Memory to Memory Move Instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 179 - Base; Load and Store Instructions

Load and Store Instructions 6-39 6.7.4 Read/Write System Memory from a SCRIPTS Instruction By using the Memory Move instruction, single or multiple register valuesmay be transferred to or from system memory. Because the LSI53C810A responds to addresses as defined in the Base Address Zero (I/O) or Ba...

Page 180 - The SIOM and DIOM bits in the; Instruction Type; When this bit is cleared, the value in the; Number of Bytes Allowed to Load/Store; One or two

6-40 Instruction Set of the I/O Processor operating register set of the chip. If it does, a PCI illegal read/write cycleoccur, the chip issues an interrupt (Illegal Instruction Detected)immediately following. The SIOM and DIOM bits in the DMA Mode (DMODE) register determine whether the destination o...

Page 181 - SCSI First Byte Received

Load and Store Instructions 6-41 Note: This bit has no effect unless the Prefetch Enable bit in the DMA Control (DCNTL) register is set. For information on SCRIPTS instruction prefetching, see Chapter 2, “Func- tional Description.” LS Load and Store 24 When this bit is set, the instruction is a Load...

Page 182 - illustrates the register bit values that represent a Load and; Load and Store Instruction Format; DCMD Register

6-42 Instruction Set of the I/O Processor Figure 6.7 illustrates the register bit values that represent a Load and Store instruction. Figure 6.7 Load and Store Instruction Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20...

Page 183 - Section 7.4, “PCI Interface Timing Diagrams”; DC Characteristics; through

LSI53C810A PCI to SCSI I/O Processor 7-1 Chapter 7ElectricalCharacteristics This chapter specifies the LSI53C810A electrical and mechanicalcharacteristics. It is divided into the following sections: • Section 7.1, “DC Characteristics” • Section 7.2, “TolerANT Technology” • Section 7.3, “AC Character...

Page 184 - Absolute Maximum Stress Ratings; Operating Conditions

7-2 Electrical Characteristics Table 7.1 Absolute Maximum Stress Ratings Symbol Parameter Min Max Unit Test Conditions T STG Storage temperature − 55 150 ° C – V DD Supply voltage − 0.5 7.0 V – V IN Input voltage V SS − 0.5 V DD +0.5 V – I LP 1 1. − 2 V < V PIN < 8 V. Latch-up current ± 150 – ...

Page 186 - Capacitance

7-4 Electrical Characteristics Table 7.6 Capacitance Symbol Parameter Min Max Unit Test Conditions C I Input capacitance of input pads – 7 pF – C IO Input capacitance of I/O pads – 10 pF – Table 7.7 Output Signals—MAC/_TESTOUT, REQ/ Symbol Parameter Min Max Unit Test Conditions V OH Output high volt...

Page 188 - TolerANT Technology; provides electrical

7-6 Electrical Characteristics 7.2 TolerANT Technology The LSI53C810A features TolerANT technology, which includes activenegation on the SCSI drivers and input signal filtering on the SCSIreceivers. Active negation actively drives the SCSI Request,Acknowledge, Data, and Parity signals HIGH rather th...

Page 189 - TolerANT Technology Electrical Characteristics

TolerANT Technology 7-7 Table 7.12 TolerANT Technology Electrical Characteristics Symbol Parameter Min Max Unit Test Conditions V OH 1 1. Active negation outputs only: Data, Parity, SREQ/, SACK/. Output high voltage 2.5 3.5 V I OH = 2.5 mA V OL Output low voltage 0.1 0.5 V I OL = 48 mA V IH Input hi...

Page 190 - Electrical Characteristics; Rise and Fall Time Test Conditions

7-8 Electrical Characteristics Figure 7.1 Rise and Fall Time Test Conditions Figure 7.2 SCSI Input Filtering Figure 7.3 Hysteresis of SCSI Receiver 2.5 V 47 Ω 20 pF +− REQ/ or ACK/ Input t 1 V TH Note: t 1 is the input filtering period. 1 Receiving Logic Le v e l 0 1.1 1.3 1.5 1.7 Input Voltage (Vol...

Page 191 - TolerANT Technology; Input Current as a Function of Input Voltage

TolerANT Technology 7-9 Figure 7.4 Input Current as a Function of Input Voltage Figure 7.5 Output Current as a Function of Output Voltage +40 +20 0 − 20 − 40 − 4 0 4 8 12 16 − 0.7 V 8.2 V HIGH-Z OUTPUT ACTIVE Input Voltage (Volts) Input Current (milliAmperes) 14.4 V Output Sink Current (milliamperes...

Page 192 - AC Characteristics; Clock Timing; Symbol

7-10 Electrical Characteristics 7.3 AC Characteristics The AC characteristics described in this section apply over the entirerange of operating conditions (refer to Section 7.1, “DC Characteristics” ). Chip timings are based on simulation at worst case voltage, temperature,and processing. Timings we...

Page 193 - Reset Input; Interrupt Output Waveforms; Interrupt Output

AC Characteristics 7-11 Table 7.14 and Figure 7.7 provide reset input timing data. Figure 7.7 Reset Input Table 7.15 and Figure 7.8 provide interrupt output timing data. Figure 7.8 Interrupt Output Waveforms Table 7.14 Reset Input Timing Symbol Parameter Min Max Unit t 1 Reset pulse width 10 – t CLK...

Page 194 - PCI Interface Timing Diagrams; Target Timing

7-12 Electrical Characteristics 7.4 PCI Interface Timing Diagrams Figure 7.9 through Figure 7.18 represent signal activity when the LSI53C810A accesses the PCI bus. The timings for the PCI bus interfaceare listed on page 7-26 . The following timing diagrams are included in this section: Target Timin...

Page 195 - PCI Interface Timing Diagrams; PCI Configuration Register Read

PCI Interface Timing Diagrams 7-13 7.4.1 Target Timing Figure 7.9 through Figure 7.12 describe target timing. Figure 7.9 PCI Configuration Register Read Data Out Byte Enable t 2 In Out t 1 t 2 t 1 t 3 t 2 t 1 t 1 t 2 t 2 t 3 t 3 t 2 t 1 t 3 t 2 t 1 CLK (Driven by System) FRAME/ (Driven by System) C_...

Page 196 - Figure 7.10 PCI Configuration Register Write

7-14 Electrical Characteristics Figure 7.10 PCI Configuration Register Write t 1 t 2 CLK (Driven by System) FRAME/ (Driven by Master) Addr In Data In Byte Enable t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 t 2 t 1 AD/ (Driven by Master) C_BE/ (Driven by Master) PAR/ (Driven by Master) IRDY/ (Driven ...

Page 197 - Figure 7.11 Target Read

PCI Interface Timing Diagrams 7-15 Figure 7.11 Target Read Data Byte Enable t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 CLK (Driven by System) FRAME/ (Driven by Master) AD/ (Driven by Master-Addr; C_BE/ (Driven by Master) PAR (Driven by Master-Addr; IRDY/ (Driven by Master) TRDY/ (Driven by ...

Page 198 - Figure 7.12 Target Write

7-16 Electrical Characteristics Figure 7.12 Target Write Byte Enable CMD t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 CLK (Driven by System) FRAME/ (Driven by Master) AD/ (Driven by Master) C_BE/ (Driven by Master) PAR/ (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C810A) ...

Page 200 - Figure 7.14 Burst Opcode Fetch

7-18 Electrical Characteristics Figure 7.14 Burst Opcode Fetch CLK (Driven by System) FRAME/ (Driven by LSI53C810A) AD/ (Driven by LSI53C810A- C_BE/ (Driven by LSI53C810A) PAR (Driven by LSI53C810A- IRDY/ (Driven by LSI53C810A) TRDY/ (Driven by Target) STOP/ (Driven by Target) DEVSEL/ (Driven by Tar...

Page 203 - This page intentionally left blank.

PCI Interface Timing Diagrams 7-21 This page intentionally left blank.

Page 204 - Figure 7.17 Burst Read

7-22 Electrical Characteristics Figure 7.17 Burst Read t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C810A) GPIO1_MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) PAR (Driven by LSI53C810A- IRDY/ (Driven by LSI53C810A) TRDY/ (Driven by Target) STOP/ (Driven by Target) DEVSEL/ (Driven by Target)...

Page 206 - Figure 7.18 Burst Write

7-24 Electrical Characteristics Figure 7.18 Burst Write CLK (Driven by System) GPIO0_ FETCH/ PAR (Driven by LSI53C810A) IRDY/ (Driven by LSI53C810A) TRDY/ (Driven by Target) STOP/ (Driven by Target) DEVSEL/ (Driven by Target) AD (Driven by LSI53C810A) C_BE/ (Driven by LSI53C810A) t 3 FRAME/ (Driven ...

Page 208 - PCI Interface Timing; describes the PCI timing data for the LSI53C810A.; PCI Timing

7-26 Electrical Characteristics 7.5 PCI Interface Timing Table 7.16 describes the PCI timing data for the LSI53C810A. Table 7.16 PCI Timing Symbol Parameter Min Max Unit t 1 Shared signal input setup time 7 – ns t 2 Shared signal input hold time – – ns t 3 CLK to shared signal output valid – 11 ns t...

Page 209 - Figure 7.19 Initiator Asynchronous Send

SCSI Timings 7-27 7.6 SCSI Timings Tables 7.17 through 7.23 and Figures 7.19 through 7.23 describe the LSI53C810A SCSI timing data. Figure 7.19 Initiator Asynchronous Send Table 7.17 Initiator Asynchronous Send (5 Mbytes/s) Symbol Parameter Min Max Unit t 1 SACK/ asserted from SREQ/ asserted 10 – ns...

Page 210 - Figure 7.20 Initiator Asynchronous Receive

7-28 Electrical Characteristics Figure 7.20 Initiator Asynchronous Receive Table 7.18 Initiator Asynchronous Receive (5 Mbytes/s) Symbol Parameter Min Max Unit t 1 SACK/ asserted from SREQ/ asserted 10 – ns t 2 SACK/ deasserted from SREQ/ deasserted 10 – ns t 3 Data setup to SREQ/ asserted 0 – ns t ...

Page 211 - Figure 7.21 Target Asynchronous Send

SCSI Timings 7-29 Figure 7.21 Target Asynchronous Send Table 7.19 Target Asynchronous Send (5 Mbytes/s) Symbol Parameter Min Max Unit t 1 SACK/ asserted from SREQ/ asserted 10 – ns t 2 SACK/ deasserted from SREQ/ deasserted 10 – ns t 3 Data setup to SREQ/ asserted 55 – ns t 4 Data hold from SACK/ as...

Page 215 - Package Drawings; illustrates the mechanical drawing for the LSI53C810A.

Package Drawings 7-33 7.7 Package Drawings Figure 7.24 illustrates the mechanical drawing for the LSI53C810A.

Page 219 - lists the LSI53C810A configuration registers by register name.; Register Name

LSI53C810A PCI to SCSI I/O Processor A-1 Appendix ARegister Summary Table A.1 lists the LSI53C810A configuration registers by register name. Table A.1 Configuration Registers Register Name Address Read/Write Page Base Address One (Memory) 0x14 Read/Write 3-17 Base Address Zero (I/O) 0x10 Read/Write ...

Page 220 - Register Summary; lists the LSI53C810A SCSI registers by register name.; SCSI Registers; Read Only

A-2 Register Summary Table A.2 lists the LSI53C810A SCSI registers by register name. Table A.2 SCSI Registers Register Name Address Read/Write Page Adder Sum Output (ADDER) 0x3C–0x3F (0xBC–0xBF) Read Only 5-47 Chip Test Five (CTEST5) 0x22 (0xA2) Read/Write 5-36 Chip Test Four (CTEST4) 0x21 (0xA1) Re...

Page 223 - Index; Symbols

LSI53C810A PCI to SCSI I/O Processor IX-1 Index Symbols (AD[31:0]) 4-6 (BARO[31:0]) 3-17 (BARZ[31:0]) 3-17 (CLS[7:0]) 3-16 (FMT) 5-29 (HT[7:0]) 3-17 (IL[7:0]) 3-18 (IP[7:0]) 3-18 (LT[7:0]) 3-16 (MG[7:0]) 3-19 (ML[7:0]) 3-19 Numerics encoded chip SCSI ID, bits 5-12 3.3/5 volt PCI interface 2-5 3-stat...

Page 226 - to

IX-4 Index SCSI bus data lines 5-66 SCSI chip ID 5-11 SCSI control one register 5-6 SCSI control register two 5-9 SCSI control three 5-9 SCSI control zero 5-2 SCSI destination ID 5-15 SCSI first byte received 5-17 SCSI input data latch 5-65 SCSI interrupt enable one 5-50 SCSI interrupt enable zero 5...

Page 231 - Customer Feedback; Thank you for your help in improving the quality of our documents.

LSI53C810A PCI to SCSI I/O Processor Customer Feedback We would appreciate your feedback on this document. Please copy thefollowing page, add your comments, and fax it to us at the numbershown. If appropriate, please also fax copies of any marked-up pages from thisdocument. Important: Please include...

Page 232 - Reader’s Comments; Excellent Good Average

Customer Feedback Reader’s Comments Fax your comments to: LSI Logic CorporationTechnical PublicationsM/S E-198Fax: 408.433.4333 Please tell us how you rate this document: LSI53C810A PCI to SCSI I/O Processor Technical Manual. Place a check mark in the appropriateblank for each category. What could w...

Page 237 - International Distributors

International Distributors AustraliaNew South WalesReptechnic Pty Ltd ♦ Tel: 612.9953.9844Fax: 612.9953.9683 BelgiumAcal nv/saTel: 32.2.7205983Fax: 32.2.7251014 ChinaBeijingLSI Logic InternationalServices Inc.Tel: 86.10.6804.2534Fax: 86.10.6804.2521 FranceRungis CedexAzzurri Technology FranceTel: 33...

LSI Logic 53C810A - Manual

Table of Contents:

Summary

Other LSI Logic Models