Lantronix DSTni-EX - Manual

Page 3 - Copyright & Trademark; Am186 is a trademark of Advanced Micro Devices, Inc.; Lantronix

i Copyright & Trademark © 2003 Lantronix, Inc. All rights reserved. Lantronix and the Lantronix logo, and combinations thereof are registered trademarks of Lantronix, Inc. DSTni is a registered trademark of Lantronix, Inc. Ethernet is a registered trademark of Xerox Corporation. All other produc...

Page 4 - ii; Warranty

ii Warranty Lantronix warrants each Lantronix product to be free from defects in material and workmanship for a period specified on the product warranty registration card after the date of shipment. During this period, if a customer is unable to resolve a product problem with Lantronix Technical Sup...

Page 5 - iii; Contents

iii Contents Copyright & Trademark ________________________________________________________ i Warranty___________________________________________________________________ ii Contents ___________________________________________________________________ iii List of Tables ___________________________...

Page 6 - iv; List of Tables

iv Host Mode Operation ________________________________________________________ 50 Sample Host Mode Operations ________________________________________________ 51 USB Pull-up/Pull-down Resistors_______________________________________________ 53 USB Interface Signals _________________________________...

Page 8 - vi; List of Figures

vi Table 5-34. Tx/Rx Message Level Register .............................................................................. 71 Table 5-35. Tx/Rx Message Level Register Definitions............................................................. 71 Table 5-36. Interrupt Flags ................................

Page 10 - Notes are information requiring attention.; Navigating Online; hyperlinks

2 Intended Audience This User Guide is intended for use by hardware and software engineers, programmers, and designers who understand the basic operating principles of microprocessors and their systems and are considering designing systems that utilize DSTni. Conventions This User Guide uses the fol...

Page 11 - Organization

3 Organization This User Guide contains information essential for system architects and design engineers. The information in this User Guide is organized into the following chapters and appendixes. Section 1: Introduction Describes the DSTni architecture, design benefits, theory of operations, ball ...

Page 12 - Theory of Operation; SPI Background

4 2 2 : : S S P P I I C C o o n n t t r r o o l l l l e e r r This chapter describes the DSTni Serial Peripheral Interface (SPI) controller. Topics include: Theory of Operation on page 4 SPI Controller Register Summary on page 5 SPI Controller Register Definitions on page 6 Theory of Operation SPI B...

Page 13 - SPI Controller Register Summary; Table 2-1. SPI Controller Register Summary

5 When operating as a slave, the SPI clock signal (SCLK) must be slower than 1/8th of the CPU clock (1/16th is recommended). Note: The SPI is fully synchronous to the CLK signal. As a result, SCLK is sampled and then operated on. This results in a delay of 3 to 4 clocks, which may violate the SPI sp...

Page 14 - SPI Controller Register Definitions; SPI_DATA is the SPI Controller Data register.; BIT; Bits; Reserved; Always returns zero.; Data

6 SPI Controller Register Definitions SPI_DATA Register SPI_DATA is the SPI Controller Data register. Table 2-2. SPI_DATA Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B800 FIELD /// DATA[7:0] RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW R W RW RW RW RW RW RW RW RW RW RW RW RW RW Table...

Page 15 - CTL Register; CTL is the SPI Controller Control register.

7 CTL Register CTL is the SPI Controller Control register. Table 2-4. CTL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B802 FIELD /// IRQENB AUTODRV INVCS PHASE CKPOL WOR MSTN ALT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW R W RW RW RW RW RW RW RW RW RW RW RW Table 2-5. CTL Re...

Page 16 - To clear a bit in the SPI_STAT register, write a 1 to that bit.; IRQ; RESET; default

8 SPI_STAT Register To clear a bit in the SPI_STAT register, write a 1 to that bit. Table 2-6. SPI_STAT Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B804 FIELD /// IRQ OVERRUN COL /// TXRUN SLVSEL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R Tab...

Page 17 - SPI_SSEL is the Slave Select Bit Count register.; SELECTO; Bit Shift Count; SelectO Signal; Number of Bits Shifted

9 SPI_SSEL Register SPI_SSEL is the Slave Select Bit Count register. Table 2-8. SPI_SSEL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B806 FIELD /// BCNT[2:0] /// SELECTO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-9. SPI_SSEL Registe...

Page 18 - Divisor Select

10 DVD_CNTR_LO Register DVD_CNTR_LO is the DVD Counter Low Byte register. Table 2-11. DVD_CNTR_LO Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B808 FIELD /// DVDCNT[7:0] RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-12. DVD_CNTR_LO Regi...

Page 19 - Features

11 3 3 : : I I 2 2 C C C C o o n n t t r r o o l l l l e e r r This chapter describes the DSTni I 2 C controller. Topics include: Features on page 11 Block Diagram on page 12 Theory of Operation on page 12 Programmer’s Reference on page 22 I 2 C Controller Register Summary on page 22 I 2 C Controlle...

Page 20 - Block Diagram; C Controller Block Diagram; C Background

12 Block Diagram Figure 3-1 shows a block diagram of the DSTni I 2 C controller. Figure 3-1. DSTni I 2 C Controller Block Diagram Theory of Operation I 2 C Background The I 2 C bus is a popular serial, two-wire interface used in many systems because of its low overhead. Capable of 100 KHz operation,...

Page 21 - Master Transmit Mode; successfully, the status code is 18h or 20h.

13 I 2 C Controller The I 2 C controller base address is D000h and shares INT2 with the SPI controller. The I 2 C bus interface requires two bi-directional buffers with open collector (or open drain) outputs and Schmitt inputs. Operating Modes The following sections describe the possible I 2 C opera...

Page 23 - Arbitration lost

15 Servicing the Interrupt After servicing this interrupt, and transmitting the second part of the address, the Status register contains one of the codes in Table 3-2. Note: If a repeated START condition transmits, the status code is 10h instead of 08h. Table 3-2. Codes After Servicing Interrupts (M...

Page 24 - OR; All Bytes Transmit Completely

16 Transmitting Each Data Byte After each data byte transmits, the IFLG is set, and one of the three status codes in Table 3-3 is in the Status register. Table 3-3. Status Codes After Each Data Byte Transmits Code I 2 C State Microprocessor Response Next I 2 C Action 28h Data byte transmitted, ACK r...

Page 27 - Slave Transmit Mode; If the I

19 Receiving Each Data Byte After receiving each data byte, the IFLG is set and one of three status codes in Table 3-6 is in the Status register. When all bytes are received, set the STP bit by writing a 1 to it in the Control register. The I 2 C controller: Transmits a STOP condition Clears the STP...

Page 28 - Slave Receive Mode

20 − The IFLG is set and the Status register contains B8h. − After the last transmission byte loads in the Data register, clear AAK when IFLG clears. − After the last byte is transmitted, the IFLG is set and the Status register contains C8h. − The I 2 C controller returns to the idle state and the A...

Page 29 - Bus Clock Considerations; Bus Clock Speed

21 Bus Clock Considerations Bus Clock Speed The I 2 C bus can be defined for bus clock speeds up to 100 Kb/s and up to 400 Kb/s in fast mode. To detect START and STOP conditions on the bus, the M I 2 C must sample the I 2 C bus at least 10 times faster than the fastest master bus clock on the bus. T...

Page 30 - Programmer’s Reference; C Controller Register Summary

22 Resetting the I 2 C Controller There are two ways to reset the I 2 C controller. Using the RSTIN# pin Writing to the Software Reset register Using the RSTIN# pin reset method: Clears the Address, Extended Slave Address, Data, and Control registers to 00h. Sets the Status register to F8h. Sets the...

Page 31 - C Controller Register Definitions; Slave Address Register; General Call Address Enable; FIELD; Slave Address

23 I 2 C Controller Register Definitions Slave Address Register Table 3-8. Slave Address Register BIT 7 6 5 4 3 2 1 0 OFFSET D000 EXTENDED ADDRESS 1 1 1 1 0 SLAX9 SLAX8 General Call Address Enable FIELD SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GCE RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3-9...

Page 32 - Data Register; In transmit mode, the byte is sent most-significant bits first.; Transmission Data/Slave Address or Receipt Data Byte

24 Data Register The Data register contains the transmission data/slave address or the receipt data byte. In transmit mode, the byte is sent most-significant bits first. In receive mode, the first bit received is placed in the register’s most-significant bits. After each byte transmits, the Data reg...

Page 33 - Control Register; Table 3-13. Control Register Definitions; Extended Slave Address; Start Condition

25 Control Register Table 3-12. Control Register BIT 7 6 5 4 3 2 1 0 OFFSET D004 FIELD IEN ENAB STA STP IFLG AAK /// /// RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3-13. Control Register Definitions Bits Field Name Description 7 IEN Extended Slave Address l = interrupt line (INTR) goes H...

Page 34 - Status Register; causing the I

26 Bits Field Name Description 2 AAK Acknowledge 1 = send Acknowledge (LOW level on SDA) during acknowledge clock pulse on the I 2 C bus if: − The entire 7-bit slave address or the first or second bytes of a 10-bit slave address are received. − The general call address is received and the GCE bit in...

Page 35 - Status Code; Code

27 Table 3-15. Status Register Definitions Bits Field Name Description 7:3 STATUS CODE Status Code Five-bit status code. See Table 3-16. 2:0 /// Reserved Table 3-16. Status Codes Code Description 00h Bus error 08h START condition sent 10h Repeated START condition sent 18h Address + write bit sent, A...

Page 36 - Clock Control Register; W W W W; Table 3-18. Clock Control Register Definitions; These bits define the M value used in the calculations above.; N Value; These bits define the N value used in the calculations above

28 Clock Control Register The Clock Control register is a Write Only register that contains seven least-significant bits. These least-significant bits control the frequency: At which the I 2 C bus is sampled. Of the I 2 C clock line (SCL) when the I 2 C controller is in master mode. The CPU clock fr...

Page 37 - Extended Slave Address Register; Table 3-19. Extended Slave Address Register; Software Reset Register; Table 3-22. Software Reset Register Definitions; Hardware Reset to I

29 Extended Slave Address Register Table 3-19. Extended Slave Address Register BIT 7 6 5 4 3 2 1 0 OFFSET D008 FIELD SLAX7 SLAX6 SLAX5 SLAX4 SLAX3 SLAX2 SLAX1 SLAX0 RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3-20. Extended Slave Address Register Definitions Bits Field Name Description 7 ...

Page 39 - USB Background; Serial Interface Engine

31 Theory of Operation USB Background USB is a serial bus operating at 12 Mb/s. USB provides an expandable, hot-pluggable Plug-and-Play serial interface that ensures a standard, low-cost socket for adding external peripheral devices. USB allows the connection of up to 127 devices. Devices suitable f...

Page 40 - USB Hardware/Software Interface; Buffer Descriptor Table

32 Microprocessor Interface The USB microprocessor interface is made up of a slave interface and a master interface. The slave interface consists of a number of USB control and configuration registers. USB internal registers can be accessed using a simple microprocessor interface. The master interfa...

Page 41 - Rx vs. Tx as a Target Device or Host

33 Figure 4-1. Buffer Descriptor Table The microprocessor manages buffers intelligently for the USB by updating the BDT as necessary. This allows the USB to handle data transmission and reception efficiently while the microprocessor performs communication-overhead processing and other function-depen...

Page 42 - TX; Register in the Control Block; Buffer Descriptor Formats

34 Table 4-1. USB Data Direction Rx Tx Device OUT or SETUP IN Host IN OUT or SETUP Addressing BDT Entries Before describing how to access endpoint data via the USB or microprocessor, it is important to understand the BDT addressing mechanism. The BDT occupies up to 256 bytes of system memory. Sixtee...

Page 43 - Low Byte

35 Table 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines… Microprocessor Determines… Who owns the buffer in system memory Who owns the buffer in system memory Data0 or Data1 PID Data0 or Data1 PID Release Own upon packet completion No address increment (FIFO Mode) D...

Page 44 - NINC

36 Table 4-6. USB Buffer Descriptor Format Definitions Bits Field Name Description 7 OWN BD Owner Specifies which unit has exclusive access to the BD. 0 = microprocessor has exclusive and entire BD access; USB ignores all other fields in the BD 1 = USB has exclusive BD access SIE writes a 0 to this ...

Page 45 - USB Transaction; When the USB transmits or receives data:

37 USB Transaction When the USB transmits or receives data: 1. The USB uses the address generation in Table 4-5 to compute the BDT address. 2. After reading the BDT, if the OWN bit equals 1, the SIE DMAs the data to or from the buffer indicated by the BD’s ADDR field. 3. When the TOKEN is complete, ...

Page 46 - USB Register Summary; Mnemonic; Dedicated to host mode.

38 USB Register Summary Table 4-7. USB Register Summary Hex Offset Mnemonic Register Description Page 00 INT_STAT Bits for each interrupt source in the USB. 39 02 ERR_STAT Bits for each error source in the USB. 41 04 STAT Transaction status in the USB. 43 06 ADDR USB address that the USB decodes in ...

Page 47 - USB Register Definitions; The register mnemonic is provided for reference purposes.; Interrupt Status Register; Interrupt Mask; Enable/Disable STALL Interrupt; ATTACH; Enable/Disable ATTACH Interrupt; SLEEP; Enable/Disable SLEEP Interrupt; ERROR; Enable/Disable ERROR Interrupt

39 USB Register Definitions The following sections provide the USB register definitions. In these sections: The register mnemonic is provided for reference purposes. The register address shown is the address location of the register in the CRB. The initialization value shown is the register’s initia...

Page 49 - Error Register; Table 4-10. Error Interrupt Status Register; Error Mask; BTOERR

41 Error Register The Error register contains bits for each of the error sources in the USB. Each of these bits is qualified with its respective error enable bits. The result is OR’ed together and sent to the ERROR bit of the Interrupt Status register. Once an interrupt bit has been set it may only ...

Page 50 - DMAERR; Data Field Received Not 8 Bits

42 Bits Field Name Description 5 DMAERR 1 = USB requests a DMA access to read a new BDT, but is not given the bus before USB needs to receive or transmit data. • If processing a TX transfer, this causes a transmit data underflow condition. • If processing an Rx transfer, this causes a receive data o...

Page 51 - TXDSUSPEND; Live USB Differential Receiver JSTATE Signal

43 Status Register The Status register reports the transaction status within the USB. When the microprocessor has received a TOK_DNE interrupt, the Status register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOK_DNE...

Page 53 - Address Register; BDT Page Register; R R R R R; BDT Base Address; LSEN; Low Speed Enable (valid for host mode only)

45 Address Register The Address register contains the unique USB address that the USB decodes in peripheral mode (HOST_MODE_EN=0). In host mode (HOST_MODE_EN=1), the USB transmits this address with a TOKEN packet. This enables the USB to uniquely address any USB peripheral. In either mode the USB_EN...

Page 54 - Frame Number Registers; Table 4-17. Frame Number Register Definitions; The 11 bits of the Frame Number.

46 Frame Number Registers The Frame Number registers contain the 11-bit frame number. The current frame number is updated in these registers when a SOF_TOKEN is received. Table 4-16. Frame Number Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 08h FIELD /// FRM[10:0] RESET 0 0 0 0 0 0 0 0 ...

Page 55 - Token Register

47 Token Register The Token register performs USB transactions when in host mode (HOST_MODE_EN=1). When the host microprocessor wants to execute a USB transaction to a peripheral, it writes the TOKEN type and endpoint to this register. After this register is written, the USB begins the specified USB...

Page 56 - SOF Count Threshold; Token Type

48 Table 4-18. Token Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0Ah SOF Threshold Register Token Register FIELD CNT[7:0] TOKEN_PID TOKEN_ENDPT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W Table 4-19. Token Reg...

Page 57 - Endpoint Control Registers; Table 4-22. Endpoint Control Register Definitions; Endpoint Enable

49 Endpoint Control Registers The Endpoint Control registers contain the endpoint control bits for the 16 endpoints available on USB for a decoded address. These four bits define all the control necessary for any one endpoint. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required ...

Page 58 - Disable; Host Mode Operation; Token Register on page 47

50 Table 4-23. Endpoint Control Register Definitions EP_CTL_DIS EP_RX_EN EP_TX_EN Endpoint Enable / Direction Control /// 0 0 Disable endpoint. /// 0 1 Enable endpoint for TX transfer only. /// 1 0 Enable endpoint for RX transfer only. 1 1 1 Enable endpoint for RX and TX transfers. 0 1 1 Enable endp...

Page 59 - Sample Host Mode Operations; Figure 3. Enable Host Mode and Configure a Target Device

51 Sample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target Device

Page 60 - Figure 4. Full-Speed Bulk Data Transfers to a Target Device

52 Figure 4. Full-Speed Bulk Data Transfers to a Target Device

Page 62 - USB Interface Signals; = USB core drives serial data on to the USB.

54 USB Interface Signals Clock (CLK) The clock input is required to be connected to a 12 MHz signal that is derived from the USB signals. USP Speed (SPEED) The USB speed indicator is used by external USB transceiver logic to determine which speed interface the USB is implementing. 1 = USB is operati...

Page 64 - CANBUS Background; Data Exchanges and Communication

56 CANBUS Background CAN is a fast and highly reliable, multicast/multimaster, prioritized serial communications protocol that is designed to provide reliable and cost-effective links. CAN uses a twisted-pair cable to communicate at speeds of up to 1 MB/s with up to 127 nodes. It was originally deve...

Page 65 - CANBUS Speed and Length; Table 5-1. Bit Rates for Different Cable Lengths

57 CANBUS Speed and Length Table 7-1 shows the relationship between the bit rate and cable length. Table 5-1. Bit Rates for Different Cable Lengths Bit Rate Cable Length 10 KB/s 6.7 km 20 KB/s 3.3 km 50 KB/s 1.3 km 125 KB/s 530 m 250 KB/s 270 m 500 KB/s 130 m 1 MB/s 40 m Features Three programmable ...

Page 66 - CAN Controller; CAN Register Summaries; Register Summary; Hex Offset

58 Theory of Operation The CAN controller appears to the microprocessor as an I/O device. Each peripheral has 256 bytes of I/O address space allocated to it. CAN0 and CAN1 share Interrupt 6. Table 5-2. CAN I/O Address CAN Controller Base Address CAN0 A800h CAN1 A900h CAN Register Summaries DSTni con...

Page 68 - Detailed CAN Register Map

60 Detailed CAN Register Map Table 5-4. Detailed CAN Register Map Hex Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 TX Msg 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 0x02 /// ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 /// /// ...

Page 71 - CAN Register Definitions; TX Message Registers; Sending a Message; The following sequence describes how to send a message.; Removing a Message from a Transmit Holding Register; Set TxAbort to request the message removal.

63 CAN Register Definitions TX Message Registers To avoid priority inversion issues in the transmit path, three transmit buffers are available with a built-in priority arbiter. When a message is transmitted, the priority arbiter evaluates all pending messages and selects the one with the highest pri...

Page 72 - Tx Message Registers

64 Tx Message Registers Table 5-5 shows TxMessage_0 registers. The registers for TxMessage_1 and TxMessage_2 are identical except for the offsets. Table 5-5. TxMessage_0:ID28 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 00h FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 I...

Page 73 - Field Name

65 Table 5-12. TxMessage_0:Ctrl Flags BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0E FIELD /// /// /// /// /// /// /// /// /// /// /// /// /// /// Tx Abort TRX Table 5-13. TxMessage_0 Register Definitions Field Name Description ID_28:ID_0 Message Identifier for Both Standard and Extended Messag...

Page 74 - RX Message Registers; Rx; To read received messages:

66 RX Message Registers A 4-message-deep FIFO stores the incoming messages. Status flags indicate how many messages are stored. Additional flags determine from which acceptance filter the actual message is coming from. Figure 5-2. RX Message Routing Rx M es sage 1 MESSAGE FILTERS CAN Module uP Bus C...

Page 75 - Rx Message Registers; Message Identifier for Both Standard and Extended Messages

67 Rx Message Registers The following table shows RxMessage registers. See the complete register table at the start of this section. Table 5-14. RxMessage:ID28 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 30h FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 R...

Page 77 - Msg Avail

69 Table 5-26. RxMessage: RTR BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 3C FIELD /// AFI_2 AFI_1 AFI_0 /// RTR IDE DLC_3 DLC_2 DLC_1 DLC_0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-27. Rx Message: RTR Register Definitions...

Page 78 - Error Count and Status Registers; Table; The receiver error counter is greater than or equal to 96 (dec).

70 Error Count and Status Registers Table 5-30. Tx/Rx Error Count BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 40h FIELD RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 TE7 TE6 TE5 TE4 TE3 TE2 TE1 TE0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table...

Page 80 - Interrupt Flags; The reset value of this register’s bits is indeterminate.

72 Interrupt Flags The following flags are set on internal events (they activate an interrupt line when enabled). They are cleared by writing a ‘ 1’ to the appropriate flag. Acknowledging the tx_msg interrupt also acknowledges all tx_xmit interrupt sources. Acknowledging one of the tx_xmit interrupt...

Page 81 - Interrupt Enable Registers; Table 5-39. Interrupt Enable Register Definitions

73 Interrupt Enable Registers All interrupt sources are grouped into three groups (traffic, error and diagnostics interrupts). To enable a particular interrupt, set its enable flag to ‘ 1’ . Table 5-38. Interrupt Enable Registers BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 48h FIELD RX_MSG TX_M...

Page 82 - CAN Operating Mode; Table 5-41. Interrupt Enable Register Definitions

74 Bits Field Name Description 3 OVR_LOAD Overload Condition − int3n group (diagnostic interrupts) 1 = enable flag set. 0 = enable flag not set. 2 ARB_LOSS Arbitration Loss − int3n group (diagnostic interrupts) 1 = enable flag set. 0 = enable flag not set. 1 /// Reserved 0 INT_ENB General Interrupt ...

Page 83 - CAN Configuration Registers; Table 5-43. Bit Rate Divisor Register Definitions

75 Figure 5-3. CAN Operating Mode CAN Module 1 CAN Module 2 a c b d CAN Port 1 CAN Port 2 DSTni Note: The Loopback Mode register in CAN module 2 is not functional. For proper operation in loopback mode, the configuration of both CAN modules must be the same. CAN Configuration Registers The following...

Page 84 - Table 5-45. Configuration Register Definitions; Sampling Mode

76 Table 5-44. Configuration Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 4Eh FIELD OV R_MS G TS2_2 TS2_1 TS2_0 TS1_3 TS1_2 TS1_1 TS1_0 /// AUTO _RES CFG_SJW1 SAMP_MO D E D GE _MOD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...

Page 85 - Observe the following conditions when setting tseg1 and tseg2:

77 The following relations exist for bit time, time quanta, time segments ½, and the data sampling point. Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships Bit Time 1 tseg1 + 1 tseg2 + 1 time quanta (TQ) Sample Point Bittime = (1+ ( tseg1 + 1) + (tseg2 + 1)) x timequanta timequanta =...

Page 86 - Acceptance Filter and Acceptance Code Mask; Table 5-46. Acceptance Filter Enable Register; Table 5-49. Acceptance Mask 0 Register Definitions; Incoming Bit Check

78 Acceptance Filter and Acceptance Code Mask Three programmable Acceptance Mask and Acceptance Code register (AMR/ACR) pairs filter incoming messages. The acceptance mask register (AMR) defines whether the incoming bit is checked against the acceptance code register (ACR). Table 5-46. Acceptance Fi...

Page 87 - Message Data; IDE; Extended Identifier Bit

79 Table 5-50. Acceptance Mask Register: ID 12 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 54h FIELD ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 IDE RTR /// RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-51....

Page 88 - Table 5-55. Acceptance Code Register Definitions

80 Table 5-54. Acceptance Code Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 58h FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-55. Acc...

Page 89 - CANbus Analysis; Arbitration Lost Capture Register; Table 5-61. Arbitration Lost Capture Register Definitions

81 CANbus Analysis Three additional registers are provided for advanced analysis of a CAN system. These registers include arbitration lost and error capture registers, as well as a CANbus frame reference register that contains information about the CANbus state and the physical Rx and TX pins. Arbit...

Page 90 - Error Capture Register; Table 5-63. Error Capture Register Definitions; TX Mode

82 Error Capture Register The Error Capture register captures the most recent error event with the frame reference pointer, rx- and tx-mode and the associated error code. Table 5-62. Error Capture Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 78h FIELD ERR2 ERR1 ERR0 FR4 FR3 FR2 FR1 FR0 ...

Page 91 - Frame Reference Register; Table 5-65. Error Capture Register Definitions; Stuff Bit Inserted

83 Frame Reference Register The Frame Reference register contains information of the current bit of the CAN message. A frame reference pointer indicates the current bit position. This enables message tracing on bit level. Note: The reset value of this register’s bits is indeterminate. Table 5-64. Fr...

Page 92 - CAN Bus Interface; Interface Connections

84 Bits Field Name Description 5:0 FRB[5:0] frame_ref_bit_nr A 6-bit vector that counts the bit numbers in one field. Example: if field = “data” = “01010”, “bit_nr” = “000000”, and “tx_mode” = ‘1’, it indicates that the first data bit is being transmitted. CAN Bus Interface DSTni contains two comple...

Page 94 - Figure 5-8. CAN Transceiver and Isolation Circuits

86 Figure 5-8. CAN Transceiver and Isolation Circuits +5_CAN 1 U6 HCPL-O601 VCC GND 8 5 C67 0.01uf R191 680 7 +3.3v 2 R193 270 CAN_TX 3 4 +5_CAN 470 6 RXD 4 TXD U18 PCA82C251 CANL CANH 6 CAN- 7 CAN+ C10 0.01uf GND_CAN 3 V+ 8 2 GND_CAN GND RS 1 GND_CAN C9 0.01uf 1 VCC GND 8 5 C12 0.01uf R190 680 7 +5...

Lantronix DSTni-EX - Manual

Table of Contents:

Summary

Other Lantronix Models