Kawasaki 80C152 - Manual

Kawasaki 80C152

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Table of Contents:

  • Page 3 – TXC GSC input pin for external transmit clock; , on the data sheet) because of the internal pullups. port 2 emits
  • Page 4 – RST; Table 1: PIN DESCRIPTION
  • Page 5 – for internal program execution.
  • Page 6 – Special function Registers; Note: SFR’s in marked column are bit addressable.; Table 2: SFR map for the cpu
  • Page 7 – Table 3: Reset Values of the SFRs; Reset Timing
  • Page 8 – PORT STRUCTURES AND OPERATION
  • Page 10 – Writing to a Port
  • Page 11 – ACCESSING EXTERNAL MEMORY; Active
  • Page 12 – TMOD: Timer/Counter Mode Control Register
  • Page 15 – Timer/Counter 0 in Mode 3
  • Page 16 – Priority Level Structure
  • Page 21 – Power Down and Idle; Table 6: Status of the External Pins during Idle and Power Down
  • Page 23 – Local Serial Channel; The serial port can operate in four different modes.
  • Page 24 – The figure below gives the simplified functional block for Mode 1.; Local Serial Port Mode 0
  • Page 25 – Serial Port Mode 1
  • Page 27 – Local Serial Port Mode 2
  • Page 28 – Baud Rates; In Mode 0 the baud rate is fixed at 1/12 of the oscillator frequency.; Local Serial Port Mode 3
  • Page 29 – Table 7: Timer 1 generated commonly used Baud rates
  • Page 31 – Kawasaki
  • Page 32 – GLOBAL SERIAL CHANNEL
  • Page 35 – preamble
  • Page 39 – This method of calculating the CRC is compatible with IEEE 802.3
  • Page 40 – link remains high for 2 or more bit times.
  • Page 41 – Jitter Tolerance; MANCHESTER ENCODING
  • Page 42 – Narrow Pulses
  • Page 43 – nothing
  • Page 44 – Backoff; M1 and M0 reside in GMOD, and DCR is in MYSLOT.; DCR
  • Page 45 – Random Backoff
  • Page 46 – Deterministic Backoff
  • Page 53 – Ring Network
  • Page 54 – User Defined Protocols
  • Page 55 – PLANNING FOR NETWORK CHANGES AND EXPANSIONS
  • Page 63 – CSMA/CD Clock Recovery; SDLC Clock Recovery
  • Page 68 – SUCCESSFUL ENDING OF TRANSMISSIONS AND RECEPTIONS; GSC Register Descriptions
  • Page 77 – DMA Registers
  • Page 80 – DMA Transfer from Internal Memory to Internal Memory
  • Page 91 – Summary of DMA Control Bits
  • Page 92 – INTERRUPT STRUCTURE; PCON
  • Page 96 – GSC Transmitter Error Conditions
  • Page 97 – GSC Receiver Error Conditions; The GSC Receiver section reports four kinds of error conditions:
  • Page 103 – EA
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KS152JB Universal Communications Controller
Technical Specifications

Kawasaki LSI USA, Inc.

Page 1 of 120 Ver. 0.9 KS152JB2

1.0 INTRODUCTION

The 80C152 Universal Communications Controller is an 8-bit microcontroller designed for the
intelligent management of peripheral systems or components. The 80C152 is a derivative of the
80C51 and retains the same functionality. These enhancements include: a high speed multi-proto-
col serial communication interface, two channels for DMA transfers, HOLD/HLDA bus control, a
fifth I/O port, expanded data memory, and expanded program memory.

In addition to a standard UART, referred to here as Local Serial Channel (LSC), the 80C152 has
an on-board multi-protocol communication controller called the Global Serial Channel (GSC).
The GSC interface supports SDLC, CSMA/CD, user definable protocols, and a subset of HDLC
protocols. The GSC capabilities include: address recognition, collision resolution, CRC genera-
tion, flag generation, automatic retransmission, and a hardware based acknowledge feature. This
high speed serial channel is capable of implementing the Data Link Layer and the Physical Link
Layer as shown in the OSI open systems communication model. This model can be found in the
document “Reference Model for Open Systems Interconnection Architecture”, ISO/TC97/SC16
N309.

The DMA circuitry consists of two 8-bit DMA channels with 16-bit addressability. The control
signals; Read (RD), Write (WR), hold and hold acknowledge (HOLD/HLDA) are used to access
external memory. The DMA channels are capable of addressing up to 64K bytes (16 bits). The
destination or source address can be automatically incremented. The lower 8 bits of the address
can be automatically incremented. The lower 8 bits of the address are multiplexed on the data bus
Port 0 and the upper eight bits of address will be on Port 2. Data is transmitted over an 8-bit
address/data bus. Up to 64k bytes of data may be transmitted for each DMA activation.

The new I/O port (P4) function the same as Ports 1-3 found on the 80C51.

Internal memory has been doubled in the 80C152. Data memory has been expanded to 256 bytes,
and internal program memory has been expanded to 8 bytes.

There are also some specific differences between the 80C152 and the 80C51. The first difference
is that RESET is active low in the 80C152 and active high in the 80C51H. The second difference
is that GF0 and GF1, general purpose flags in PCON, have been renamed GFIEN and XRCLK.
GFIEN enables idle flags to be generated in SDLC mode, and XRCLK enables the receiver to be
externally clocked. All of the previously unused bits are now being used and interrupt vectors
have been added to support the new enhancements.

Throughout the rest of this manual the 80C152 will be referred to generically as the “C152”. The
C152 is based on the 80C51 architecture and utilizes the same 80C51 instruction set. There have
been no new instructions added. All the new features and peripherals are supported by an exten-
sion of the Special Function Registers (SFRs). A brief information on cpu functions as: the
instruction set, port operation, timer/counters, etc., is included in this document.

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Summary

Page 3 - TXC GSC input pin for external transmit clock; , on the data sheet) because of the internal pullups. port 2 emits

KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 3 of 120 Ver. 0.9 KS152JB2 2.1 Pin Description Table 1: PIN DESCRIPTION Name Description Port 0 Port 0 is an 8-bit open drain bi-directional I/O Port. As an output port each pin cansink 8 LS TTL inputs. P...

Page 4 - RST; Table 1: PIN DESCRIPTION

KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 4 of 120 Ver. 0.9 KS152JB2 Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have1s written to them are pulled high by the internal pullups, and in that state can b...

Page 5 - for internal program execution.

KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 5 of 120 Ver. 0.9 KS152JB2 ALE Address Latch Enable output signal for latching the low byte of the address duringaccesses to external memory.In normal operation ALE is emitted at a constant rate of 1/6 th...

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