Kawasaki 80C152 - Manuals
Kawasaki 80C152 – Manual in PDF format online.
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Manual Kawasaki 80C152
Summary
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 3 of 120 Ver. 0.9 KS152JB2 2.1 Pin Description Table 1: PIN DESCRIPTION Name Description Port 0 Port 0 is an 8-bit open drain bi-directional I/O Port. As an output port each pin cansink 8 LS TTL inputs. P...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 4 of 120 Ver. 0.9 KS152JB2 Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have1s written to them are pulled high by the internal pullups, and in that state can b...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 5 of 120 Ver. 0.9 KS152JB2 ALE Address Latch Enable output signal for latching the low byte of the address duringaccesses to external memory.In normal operation ALE is emitted at a constant rate of 1/6 th...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 6 of 120 Ver. 0.9 KS152JB2 2.2 Special function Registers The following table lists the SFR’s present in 80152. Note that not all the addresses are occupiedby SFR’s. The unoccupied addresses are not imple...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 7 of 120 Ver. 0.9 KS152JB2 between the RST pin being pulled low and the internal reset being generated. During this time theCPU continues its normal operations. The internal reset signal clears the SFRs e...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 8 of 120 Ver. 0.9 KS152JB2 2.4 PORT STRUCTURES AND OPERATION The ports are all bidirectional. Each port consists of two sections, the port SFR and the I/O pad. The Ports 0 and 2 are involved in accesses t...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 10 of 120 Ver. 0.9 KS152JB2 Writing to a Port During the execution of an instruction that changes the value of a port SFR, the new value arrivesat the port latch during S6P2. However, the port latch conte...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 11 of 120 Ver. 0.9 KS152JB2 2.6 ACCESSING EXTERNAL MEMORY External Memory is accessed if either of the following two conditions is met1) The signal EA is low2) Whenever the program counter (PC) contains a...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 12 of 120 Ver. 0.9 KS152JB2 During External Memory Accesses, both Ports 0 and 2 are used for Address/ Data transfer andtherefore cannot be used for general I/O purposes. During external program fetches, P...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 15 of 120 Ver. 0.9 KS152JB2 Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 canbe turned on and off by switching it out of and into its own Mode 3. It can als...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 16 of 120 Ver. 0.9 KS152JB2 case of level triggered interrupt, the IE0 and IE1 flags are not cleared and will have to be clearedby the software. This is because in the level activated mode, it is the exte...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 21 of 120 Ver. 0.9 KS152JB2 2.9 Power Down and Idle The processor has two Power Reduction modes, Idle and Power Down. Backup power is suppliedthrough the VCC pin in these operations. The processor can be ...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 23 of 120 Ver. 0.9 KS152JB2 The DMA circuitry stops operation in both Idle and power Down modes. Since operation isstopped in both modes, the process should be similar in each case. Specific steps that ne...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 24 of 120 Ver. 0.9 KS152JB2 MODE 1 In Mode 1, the full duplex mode is used. Serial communication frames are made up of 10 bitstransmitted on TXD and received on RXD. The 10 bits consist of a start bit (0)...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 25 of 120 Ver. 0.9 KS152JB2 Reception is enabled only if REN is high. The serial port actually starts the receiving of serialdata, with the detection of a falling edge on the RxD pin. The 1-to-0 detector ...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 27 of 120 Ver. 0.9 KS152JB2 MODE 3 This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. In all four modes, transmission is started by any instruction that uses SBUF a...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 28 of 120 Ver. 0.9 KS152JB2 Baud Rates In Mode 0 the baud rate is fixed at 1/12 of the oscillator frequency. In Mode 2 the baud rate depends on the value of bit SMOD in PCON SFR. If SMOD is 0 then thebaud...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 29 of 120 Ver. 0.9 KS152JB2 in auto-reload mode. In such a case the baud rate is given by Mode 1,3 baud rate = 2 (SMOD - 5) X Oscillator Frequency / (12 x [256 - TH1]) It is also possible to achieve very ...
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA Inc. Page 31 of 120 Ver. 0.9 KS152JB2 Table 8: Instruction Table lsn msn 0 1 2 3 4 5 6-7 8-F 0 nop ajmp ljmp rr a inc a inc d inc @ inc rn 1 jbc acall lcall rrc a dec a dec d dec @ dec rn 2 jb ajmp ret rl a add a, ...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 32 of 120 Ver. 0.9 KS152JB2 3.0 GLOBAL SERIAL CHANNEL 3.1 Introduction The Global Serial Channel (GSC) is a multi-protocol, high performance serial interface targetedfor data rates up to 2 MBPS with on-ch...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 35 of 120 Ver. 0.9 KS152JB2 CRC: NONE16-bit CCITT32-bitAUTODIN II N N N 1 1 1 1 N N 1 1 1 1 1 1 1 1 O O O O O O O O O O O O O 1 1 O O O O O O O O O O O O O O O 1 1 O O Half DuplesFull Duplex O O O O O O O...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 39 of 120 Ver. 0.9 KS152JB2 The CRC generator, as shown in figure below, operates by taking each bit as it is received andXOR’ing it with bit 31 of the current CRC. This result is then placed in temporary...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 40 of 120 Ver. 0.9 KS152JB2 link remains high for 2 or more bit times. 3.2.3 INTERFRAME SPACE The interframe space is the amount of time that transmission is delayed after the link is sensed asbeing idle ...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 41 of 120 Ver. 0.9 KS152JB2 3.2.4 CSMA/CD DATA ENCODING Manchester encoding/decoding is automatically selected when the user software selects CSMA/CD transmission mode (See Figure below). In Manchester en...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 42 of 120 Ver. 0.9 KS152JB2 Narrow Pulses A valid Manchester waveform must stay high or low for at least a half bit-time, nominally 4 sam-ple-times. Jitter tolerance allows a waveform which stays high or ...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 43 of 120 Ver. 0.9 KS152JB2 3.2.6 RESOLUTION OF COLLISIONS How the GSC responds to a detected collision depends on what it was doing at the time the colli-sion was detected. What it might be doing is eith...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 44 of 120 Ver. 0.9 KS152JB2 If a transmitting 8XC152 detects a collision during the preamble/BOF part of the frame that it istrying to transmit, it will complete the preamble/BOF and then begin the jam si...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 45 of 120 Ver. 0.9 KS152JB2 Random Backoff In either of the random algorithms, the first thing that happens after a collision is detected is that aI gets shifted into the TCDCNT (Transmit Collision Detect...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 46 of 120 Ver. 0.9 KS152JB2 BKOFF starts counting down from its preload value, counting slot times. At any time, the currentvalue in BKOFF can be read by the CPU, but CPU writes to BKOFF have no effect. W...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 53 of 120 Ver. 0.9 KS152JB2 count must be done by the user software. The Hardware Based Acknowledge option that is pro-vided in the C152 is not compatible with standard SDLC protocol. 3.3.8 PRIMARY/SECOND...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 54 of 120 Ver. 0.9 KS152JB2 3.3.9 HDLC/SDLC COMPARISON HDLC (High level Data Link Control) is a standard adopted by the International Standards Orga-nization (ISO). The HDLC standard is defined in the ISO...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 55 of 120 Ver. 0.9 KS152JB2 3.5 USING THE GSC 3.5.1 LINE DISCIPLINE Line discipline is how the management of the transfer of data over the physical medium is con-trolled. Two types of line discipline will...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 63 of 120 Ver. 0.9 KS152JB2 3.5.10 Receiver Clock Recovery The receiver is always monitored at eight times the baud rate frequency, except when an externalclock is used. When using an external clock the r...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 68 of 120 Ver. 0.9 KS152JB2 would be one interframe space period after the line is sensed as being idle. As the number of stations approach 256 the probability of a successful transmission decreasesrapidl...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 77 of 120 Ver. 0.9 KS152JB2 DMA Registers Two bits in DCONn are used to specify the physical destination of the data transfer. These bits areDAS (Destination Address Space) and IDA (Increment Destination ...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 80 of 120 Ver. 0.9 KS152JB2 is still 1 and the DONE bit is still 0. An external interrupt is not generated in this case, since inlevel-activated mode, pulling the pin to a logical 1 clears the interrupt f...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 91 of 120 Ver. 0.9 KS152JB2 4.5 Summary of DMA Control Bits DAS specifies the Destination Address Space. If DAS = 0, the destination is in External DataMemory. If DAS = 1 and IDA = 0, the destination is a...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 92 of 120 Ver. 0.9 KS152JB2 ARB enables the DMA logic to detect HLD and generate HLDA. After it has activated HLDA,the C152 will not begin a new DMA to or from External Data Memory as long as HLD is seen ...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 96 of 120 Ver. 0.9 KS152JB2 It is recommended that user software should never write 1s to unimplemented bits in MCS-51devices. Further versions of the device may have new bits installed in these locations...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 97 of 120 Ver. 0.9 KS152JB2 The UR bit can be set only if the DMA bit in the TSTAT is set. The DMA bit being set informs theGSC hardware that TFIFO is being serviced by DMA. In that case if the GSC goes t...
KS152JB Universal Communications ControllerTechnical Specifications Kawasaki LSI USA, Inc. Page 103 of 120 Ver. 0.9 KS152JB2 added to the 8051BH core to accomplish high-speed transfers of packetized serial data. GTxD - GSC Transmit Data output, an alternate function of one of the port 1 pins (P1.1)....
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