Intel IXC1100 - Manual
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Table of Contents:
- Page 3 – Contents; Intel XScale
- Page 5 – ARM
- Page 7 – Base Address Register, and PCI Memory Base Address
- Page 8 – Intel
- Page 17 – Figures
- Page 18 – 8 Byte Lane Routing During PCI Target Accesses of the AHB –
- Page 19 – Tables
- Page 20 – Processor
- Page 23 – Revision History
- Page 26 – Introduction; About This Document; How to Read This Document; Familiarity with ARM; Other Relevant Documents; Number Representation
- Page 27 – Acronyms and Terminology
- Page 30 – Overview of Product Line; Figure 1
- Page 35 – North AHB; Bridge
- Page 36 – operations which accelerate many of the audio filter operations.; Figure 6
- Page 37 – Memory Management
- Page 38 – “Performance Monitoring” on page 133; Network Processor Functions
- Page 39 – Internal Bus; achieve maximum efficiency.; MII Interfaces; implements the status flags and pointers required for each queue.
- Page 40 – For more information on the AHB Queue Manager, see; UTOPIA 2; For more information on the UTOPIA Level-2 interface, see; PCI; For more information on the PCI interface, see; Memory Controller
- Page 41 – Expansion Bus; Controller” on page 292; High-Speed Serial Interfaces; Speed Serial Interfaces” on page 448
- Page 42 – Universal Asynchronous Receiver Transceiver; Asynchronous Receiver Transceiver (UART)” on page 332; GPIO; Controller” on page 398; Timers
- Page 43 – For more information on the timers, see; For more information on JTAG, see
- Page 44 – Memory Management Unit; “Exceptions” on page 47
- Page 45 – are ignored when the MMU is disabled.; Memory Attributes; Bus Controller Configuration Register 1; Instruction Cache; associated memory region will be cached.
- Page 46 – Details on Data Cache and Write Buffer Behavior; traffic to external memory. For more details on cache policies, see; Data Cache and Write Buffer; detailed in; Data Cache and Buffer Behavior When X = 0
- Page 47 – Memory Operation Ordering; issue a fence to impose a partial ordering on memory accesses.; Exceptions; “Event Architecture” on page 154; Interaction of the MMU, Instruction Cache, and Data Cache; The invalid combination will cause undefined results.; Data Cache and Buffer Behavior When X = 1; Memory Operations that Impose a Fence
- Page 48 – MMU Control; instruction TLB can also be invalidated. See; Valid MMU and Data/Mini-Data Cache Combinations
- Page 49 – Locking Entries; “Cache Lock-Down Functions” on page 83; Example 1. Enabling the MMU
- Page 50 – Example 3 on; Example 2. Locking Entries into the Instruction TLB
- Page 51 – Round-Robin Replacement Algorithm; back to entry 0 upon the next translation.; Example 3. Locking Entries into the Data TLB
- Page 52 – Figure 8; Operation When Instruction Cache is Enabled; “Instruction-Cache ‘Miss’” on page 53; Example of Locked Entries in TLB
- Page 53 – “Memory; Instruction-Cache ‘Miss’; A miss causes the following:; Instruction Cache Organization; Example: 32K byte cache
- Page 54 – instruction to the instruction decoder for execution.; Instruction-Cache Line-Replacement Algorithm; round-robin pointers for the other sets are affected in this case.
- Page 55 – Instruction-Cache Coherence; “Register; Example 4. Recovering from an Instruction Cache Parity Error
- Page 56 – Table 18, “Cache Functions” on page 81; Example 5. Enabling the Instruction Cache
- Page 57 – Figure 9; Locked Line Effect on Round-Robin Replacement
- Page 58 – Table 20, “Cache Lock-Down Functions” on page 83; Branch Target Buffer; executed branch along with two bits of history information.; Example 7. Locking Code into the Cache
- Page 59 – Figure 11, “Branch History” on page 59; Reset; BTB Entry; DATA; Branch History
- Page 60 – “Register 1: Control and Auxiliary Control Registers” on; Data Cache; Data Cache Overview; Figure 12, “Data Cache Organization” on page 61
- Page 61 – Figure 13, “Mini-Data Cache Organization” on page 62; Data Cache Organization
- Page 62 – subsequently taken out when the bus is available.; Mini-Data Cache Organization; Example: 2K byte cache
- Page 63 – “Cacheability” on page 63; Cacheability; “Cacheability” on
- Page 64 – written into the cache before it can complete.
- Page 65 – “Configuration” on page 73; Example 8. Enabling the Data Cache
- Page 66 – Example 9
- Page 67 – Example 9. Global Clean Operation
- Page 68 – “New; Reconfiguring the Data Cache as Data RAM
- Page 69 – Example 10. Locking Data into Data Cache
- Page 70 – Example 11. Creating Data RAM
- Page 73 – Configuration
- Page 74 – the values in those bits.; The format of LDC and STC for CP14 is shown in; Table 8; . LDC and STC follow the; performance monitoring registers are not accessible.
- Page 75 – CP15 Registers; Table 9; LDC/STC Format when Accessing CP14
- Page 76 – Register 0: ID and Cache Type Registers; register and a cache type register.; ID Register
- Page 77 – Register 1: Control and Auxiliary Control Registers; “Register 13: Process ID” on page 84; Cache Type Register
- Page 78 – cache attributes can be changed.
- Page 79 – Register 2: Translation Table Base Register; Auxiliary Control Register
- Page 80 – Register 3: Domain Access Control Register; in; Domain Access Control Register; Fault Status Register
- Page 81 – Register 6: Fault Address Register; Reads from this register, as with an MRC, have an undefined effect.; Fault Address Register; Cache Functions
- Page 82 – Register 8: TLB Operations; TLB Functions
- Page 83 – Register 10: TLB Lock Down; (The protocol for locking down entries can be found in; Cache Lock-Down Functions
- Page 84 – Register 13: Process ID; virtual addresses are remapped and to what value.; The PID Register Affect On Addresses; A breakpoint address (see; TLB Lockdown Functions
- Page 85 – Register 14: Breakpoint Registers; “Software Debug” on page 88; Register 15: Coprocessor Access Register; Accessing the Debug Registers
- Page 86 – Example 12. Disallowing access to CP0; Coprocessor Access Register; CP14 Registers
- Page 87 – Performance Monitoring Registers; of these registers can be found in; Clock and Power Management Registers; not implemented and reserved for future use.; Accessing the Performance Monitoring Registers; PWRMODE Register
- Page 88 – Software Debug Registers; Software Debug; IXP42X product line and IXC1100 control plane processors, namely:; Clock and Power Management
- Page 89 – Definitions
- Page 90 – Halt Mode; “SELDCSR JTAG Register” on page 103
- Page 92 – the Special Debug State (see; Debug Exceptions; architecture defines the following debug exceptions:
- Page 93 – unit is configured for Halt mode or Monitor mode.; of the Halt mode bit.; Event Priority
- Page 94 – “HW Breakpoint Resources” on page 95; Monitor Mode
- Page 95 – The processor ignores vector traps during monitor mode.; HW Breakpoint Resources; Instruction Breakpoints; may result in unpredictable behavior.
- Page 96 – processor sets the DBCR.moe bits to 0b001.; Data Breakpoints; one of two operations:; Instruction Breakpoint Address and Control Register (IBCRx)
- Page 97 – is used only when DBR0 is enabled.; Data Breakpoint Controls Register (DBCON)
- Page 98 – whether the processor is configured for monitor mode or halt mode.; Software Breakpoints; The processor handles the software breakpoint as described in; Transmit/Receive Control Register; “DBGTX JTAG Register” on page 105
- Page 99 – debugger continuously downloads data.; Normal RX Handshaking; High-Speed Download Handshaking States
- Page 100 – TX Handshaking
- Page 101 – Conditional Execution Using TXRXCTRL; Transmit Register; Table 41, “TX Handshaking” on page 100; TXRXCTRL Mnemonic Extensions; TX Register
- Page 102 – Receive Register; debugger through the JTAG interface.; Debug JTAG Access; SELDCSR, DBGTX and DBGRX. LDIC is described in; SELDCSR JTAG Command; RX Register
- Page 103 – SELDCSR JTAG Register; ), allowing the debugger to access the DCSR, generate an external; SELDCSR Hardware
- Page 104 – “Downloading Code in ICache” on page 116; SELDCSR Data Register; TDO
- Page 105 – Only bits specified as writable by JTAG in; DBGTX JTAG Command; debugger can receive data from the debug handler.; DBGTX JTAG Register; The DBGTX JTAG instruction selects the Debug JTAG Data register (; DBGTX Hardware; delay
- Page 106 – The captured TX value is scanned out during the Shift_DR state.; DBGRX JTAG Command; loaded as shown in; DBGRX Hardware
- Page 107 – Rx Write Logic
- Page 108 – DBGRX Data Register
- Page 109 – Debug JTAG Data Register Reset Values; not affect the DEBUG data register.; Trace Buffer; used for debugging an application. Two modes are supported:; Trace Buffer CP Registers; CP14 defines three registers (see; DEBUG Data Register Reset Values
- Page 110 – Checkpoint Registers; reference addresses to help reduce this problem.; CP 14 Trace Buffer Register Summary
- Page 111 – unpredictable results.; Trace Buffer Entries; Message Byte; shows all of the possible trace messages.; TBREG Format; Message Byte Formats; C C C C
- Page 112 – Exception Message Byte; SW to identify which exception occurred.; Non-Exception Message Byte; type of message (refer to
- Page 113 – and before the current one.; Address Bytes; Example 13. Rollover Messages Examples
- Page 114 – Trace Buffer Usage; control plane processors) before the buffer can be parsed.; Indirect Branch Entry Address Byte Organization; High Level View of Trace Buffer
- Page 115 – captures a trace up to the processor reset.
- Page 116 – Downloading Code in ICache; functions are supported.; LDIC JTAG Command; instruction cache through JTAG.
- Page 117 – LDIC JTAG Data Register; The data loaded into LDIC_SR1 during a Capture_DR is unpredictable.; LDIC JTAG Data Register Hardware; unpredictable
- Page 118 – specified instruction cache at the specified virtual address.; LDIC Cache Functions
- Page 119 – As shown in; Loading IC During Reset; Format of LDIC Cache Functions
- Page 120 – “Dynamically Loading IC After Reset” on page 123; Loading IC During Cold Reset for Debug
- Page 121 – Loading IC During a Warm Reset for Debug
- Page 122 – “LDIC Cache Functions” on page 118; Code Download During a Warm Reset For Debug
- Page 123 – Dynamically Loading IC After Reset; “Loading IC During Reset”; Downloading Code in IC During Program Execution
- Page 124 – operation by the processor.; Dynamic Code Download Synchronization; the handler as shown below.
- Page 125 – entire handler to be dynamic.; Download
- Page 126 – Mini-Instruction Cache Overview; details on the main instruction cache, see; Halt Mode Software Protocol; implementation techniques and requirements.; Starting a Debug Session; “Downloading Code in ICache” on
- Page 127 – debug exceptions correctly break to the debug handler.; Setting up Override Vector Tables; the reset vector, or
- Page 128 – “Debug Handler Restrictions” on page 128; Implementing a Debug Handler; Debug Handler Entry; “Halt Mode” on page 93
- Page 129 – Dynamic Debug Handler; limitations and advantages.
- Page 130 – handler returns to the application (or the debugger overwrites it).
- Page 131 – download. This removes the need for a counter in the debug handler.; Ending a Debug Session; Debug Handler Code: Download Bit and Overflow Flag
- Page 132 – Software Debug Notes and Errata
- Page 133 – Performance Monitoring; software programmers.; Overview; which is useful in measuring total execution time.; for more details on accessing these registers with MRC and
- Page 134 – Register Description; The format of CCNT is shown in; Performance Count Registers; There are four 32-bit event counters their format is shown in; Performance Monitoring Registers (Sheet 2 of 2)
- Page 135 – shows the format of the PMNC register.; Performance Monitor Control Register
- Page 136 – interrupt requesting for each counter.; Overflow Flag Status Register; Interrupt Enable Register
- Page 137 – Event Select Register; EVTSEL is used to select events for PMN0, PMN1, PMN2 and PMN3. Refer to
- Page 138 – Managing the Performance Monitor
- Page 139 – Performance Monitoring Events; Common Uses of the PMU
- Page 140 – Instruction Cache Efficiency Mode; “Register 7: Cache Functions” on page 81; Instruction Fetch Latency Mode
- Page 141 – Data/Bus Request Buffer Full Mode; Table 3.9, “Performance Considerations” on page 159
- Page 142 – Instruction TLB Efficiency Mode; Multiple Performance Monitoring Run Statistics
- Page 143 – Example 14. Configuring the Performance Monitor; Example 15. Interrupt Handling
- Page 144 – Programming Model; Big Endian versus Little Endian; Example 16. Computing the Results
- Page 145 – Thumb; Base Register Update
- Page 146 – Extensions to ARM; MRA provide the ability to read and write the 40-bit accumulator.; “Register 15: Coprocessor Access Register” on page 85; Multiply With Internal Accumulate Format
- Page 147 – Multiply with Internal Accumulate Format
- Page 148 – that was loaded into a general purpose register by LDRSH.; condition code status.
- Page 149 – interpreted as signed data values.; Internal Accumulator Access Format; accumulators in CP0.
- Page 150 – Coprocessor Access Register” on page 85
- Page 152 – This instruction executes in any processor mode.; New Page Attributes; “Memory Attributes” on page 45
- Page 153 – the IXP42X product line and IXC1100 control plane processors.; Additions to CP15 Functionality; CP14 have been added or augmented. See; First-Level Descriptors
- Page 154 – not affect the correctness of their code.; Event Architecture; Exception Summary
- Page 155 – “Software; Prefetch Aborts; These aborts are described in
- Page 156 – Data Aborts; advanced beyond the instruction that caused the data abort.; Processors’ Encoding of Fault Status for Prefetch Aborts
- Page 157 – Imprecise Data Aborts
- Page 158 – precautions are not necessary.; Events from Preload Instructions; Example 19 on; Example 18. Shielding Code from Potential Imprecise Aborts
- Page 159 – Debug Events; Debug events are covered in; Performance Considerations; Interrupt Latency; Example 19. Speculatively issuing PLD
- Page 160 – Branch Prediction; Performance Terms; Branch Latency Penalty
- Page 161 – Example 20. Computing Latencies
- Page 162 – the SUB instruction. In; at cycle 5. thus the Result Latency is five.; Branch Instruction Timings; Latency Example
- Page 163 – Multiply Instruction Timings; Multiply Instruction Timings (Sheet 1 of 2)
- Page 164 – Multiply Instruction Timings (Sheet 2 of 2)
- Page 165 – Saturated Arithmetic Instructions; Multiply Implicit Accumulate Instruction Timings
- Page 166 – Semaphore Instructions; Load and Store Multiple Instruction Timings
- Page 167 – Miscellaneous Instruction Timing; instructions, except for the cases listed below.; Optimization Guide; techniques presented in this document.; Exception-Generating Instruction Timings; Count Leading Zeros Instruction Timings
- Page 168 – About This Section; Processors’ Pipeline; General Pipeline Characteristics; Number of Pipeline Stages
- Page 169 – pipeline. These are shown in; Processors’ RISC Super-Pipeline; XWB; Mx; DWB; Main execution pipeline; Pipelines and Pipe Stages
- Page 170 – Register Scoreboarding; Instruction Flow Through the Pipeline
- Page 171 – Pipeline Stalls; Main Execution Pipeline; An understanding of the BTB (See
- Page 172 – The X1 pipe stage performs the following functions:; Memory Pipeline; memory pipeline handles load / store instructions.; D1 and D2 Pipe Stage; alignment occurs for byte and half-word loads.
- Page 173 – Behavioral Description; “Instruction Latencies” on page 160; Basic Optimizations; Conditional Instructions; Optimizing Condition Checks
- Page 174 – the next loop iteration.
- Page 175 – Optimizing Branches; c y c l e s
- Page 177 – Vs using branches can be computed as follows:; Optimizing Complex Expressions; The optimized code for the if condition is:
- Page 178 – Bit Field Manipulation; optimized as follows:; Optimizing the Use of Immediate Values; operation whenever possible.
- Page 179 – Effective Use of Addressing Modes
- Page 180 – Cache and Prefetch Optimizations; Cache Miss Cost; dependent on reducing the cache miss rate.; Round Robin Replacement Cache Policy; distribute the code on a temporal evenness over this space.; Locking Code into the Instruction Cache
- Page 181 – experimentation to optimize.; Data and Mini Cache; memory regions whose cache policies can be set by the user (see; Non-Cacheable Regions
- Page 182 – Write-Through and Write-Back Cached Memory Regions; “Reconfiguring the Data Cache as Data RAM” on page 68
- Page 183 – the benefits of cached accesses.; Data Alignment
- Page 184 – Consider the following example:; Literal Pools; “Basic Optimizations” on page 173; Cache Considerations
- Page 185 – Memory Page Thrashing; Prefetch Considerations; memory type is enabled as write-allocate.; Prefetch Loop Limitations; use value of prefetch are discussed below.; Compute versus Data Bus Bound; bound loops allow complete hiding of all data transfer latencies.; Low Number of Iterations
- Page 186 – Bandwidth Limitations; transfer resources are:; Cache Memory Considerations; enhance the spatial locality of the data.
- Page 187 – close. Array merging can place a and b specially close.
- Page 188 – Cache Blocking; minimizing cache misses and reducing bus traffic.; Prefetch Unrolling; by prefetch unrolling. For example consider:
- Page 189 – Pointer Prefetch; next iteration of the loop.
- Page 190 – Loop Interchange; induction variable interchange. The above examples becomes:
- Page 191 – the data load frees the register for use. The example code becomes:; Instruction Scheduling; Scheduling Loads; to avoid this stall. Consider the following example:
- Page 192 – the unoptimized version.
- Page 194 – on how these instructions may be used:
- Page 195 – achieved using the LDM instructions as shown below:; Scheduling Data Processing Instructions; code segment would incur a one-cycle stall for the MOV instruction:
- Page 196 – following segment of code:; Scheduling Multiply Instructions; values in registers r1 and r2 due to result latency.
- Page 197 – Scheduling SWP and SWPB Instructions
- Page 198 – Scheduling the MIA and MIAPH Instructions
- Page 199 – Scheduling CP15 Coprocessor Instructions; Optimizing C Libraries; Space/Performance Trade Off
- Page 200 – Multiple Word Load and Store; to consecutive addresses in memory whenever possible.; Use of Conditional Instructions; “Conditional Instructions” on page 173; Use of PLD Instructions
- Page 203 – Processor Engine core to operate in parallel.
- Page 204 – Internal Bus Arbiters
- Page 205 – Priority Mechanism; Memory Map; Bus Arbitration Example: Three Requesting Masters
- Page 208 – PCI Controller; The Intel
- Page 209 – Processors’ PCI Bus Configured as a Host
- Page 210 – diagram is given in; Processors’ PCI Controller Block Diagram; P C I B us
- Page 211 – “PCI Controller DMA; PCI Target Interface Supported Commands
- Page 212 – “PCI Controller Configured as Host” on; PCI Initiator Interface-Supported Commands
- Page 213 – configuration space that supports a single function.; PCI Controller Configured as Host; Controller to be enabled.
- Page 214 – Type 0 Configuration Address Phase
- Page 215 – bus cycle. However, these cycles can only be single cycle accesses.; Type 1 Configuration Address Phase
- Page 216 – what the PCI_NP_CBE register contains in the byte enable bits.; Example: Generating a PCI Configuration Write and Read; This value chosen for PCI_NP_AD follows the convention outlined in
- Page 217 – memory and PCI I/O transaction can now take place.
- Page 218 – PCI Controller Configured as Option; “PCI Controller Configured as Host” on page 213
- Page 219 – complete normally on the bus and return all zeroes.; Initializing PCI Controller Configuration and Status
- Page 220 – and the PCI Base Address Registers.
- Page 221 – three bytes from the right of the PCI_AHBIOBASE =; PCI Memory Map Allocation
- Page 222 – Example: PCI Memory Base Address Register and South-AHB; The next example shows an access to the second 16-Mbyte window.; Initializing the PCI Controller Configuration Registers; Configuration and Status Registers:
- Page 223 – and IXC1100 control plane processors.
- Page 224 – to the PCI Configuration Space:; PCI Byte Enables Using CRP Access Method
- Page 225 – PCI Controller South AHB Transactions; PCI Configuration Space
- Page 226 – PCI Controller Functioning as Bus Initiator; PCI transactions in one of three ways:; memory cycle read of non-prefetch memory.
- Page 227 – Initiated Type-0 Read Transaction; this is a PCI Bus Configuration Read Cycle.; Initiated Type-0 Write Transaction; is a PCI Bus Configuration Write Cycle.; Initiated PCI TYPE 0 Configuration Read Cycle
- Page 228 – Initiated Type-1 Read Transaction; Function 0, and Base Address Register 0.; Initiated PCI Type-0 Configuration Write Cycle; Initiated PCI Type-1 Configuration Read Cycle
- Page 229 – Initiated Type-1 Write Transaction; Function number 7, and Base Address Register 0.; Initiated Memory Read Transaction; asserted for the transaction.; Initiated PCI Type-1 Configuration Write Cycle
- Page 230 – Initiated Memory Write Transaction; Initiated PCI Memory Read Cycle
- Page 231 – Initiated I/O Read Transaction; phase — signifies that this is a PCI Bus I/O Read Cycle.; Initiated I/O Write Transaction; Initiated PCI Memory Write Cycle; Initiated PCI I/O Read Cycle
- Page 232 – Initiated Burst Memory Read Transaction; for the transaction.; Initiated PCI I/O Write Cycle
- Page 233 – Initiated Burst Memory Write Transaction; Initiated PCI Burst Memory Read Cycle
- Page 234 – PCI Controller Functioning as Bus Target; processors. Please refer to; PCI Controller DMA Controller; Initiated PCI Burst Memory Write Cycle
- Page 236 – byte swap will occur on the DMA data.; AHB to PCI DMA Transfer Byte Lane Swapping
- Page 238 – read starts towards completion.; AHB to PCI DMA Channel Operation; A DMA transfer from AHB to PCI is processed as follows:; PCI to AHB DMA Channel Operation; A DMA transfer from PCI to AHB is processed as follows:
- Page 239 – registers are updated.; PCI Controller Door Bell Register; interrupt to the Intel XScale processor.
- Page 240 – PCI Controller Interrupts; PCI Interrupt Generation; “PCI Controller Door Bell Register” on page 239; Internal Interrupt Generation; Intel XScale processor at the occurrence of various events:
- Page 241 – • A Doorbell is “pushed” by an external PCI device; PCI Controller Endian Control; used as described previously.
- Page 243 – Byte Lane Routing During PCI Target Accesses of the AHB –
- Page 244 – and
- Page 245 – Byte Lane Routing During AHB Memory Mapped Accesses of the PCI Bus –
- Page 246 – shows the byte lane routing between the PCI bus
- Page 247 – Status Registers or PCI Configuration Registers.; Byte Lane Routing During DMA Transfers
- Page 248 – PCI Controller Clock and Reset Generation; A PCI startup sequence could be as follows:
- Page 249 – requirement of the PCI specification.; PCI RCOMP Circuitry; the Intel; Register Descriptions; PCI Configuration Registers; registers are described in; PCI Configuration Register Map (Sheet 1 of 2)
- Page 250 – Device ID/Vendor ID Register; PCI Configuration Register Map (Sheet 2 of 2)
- Page 252 – Class Code/Revision ID Register
- Page 253 – Base Address 0 Register
- Page 254 – Base Address 1 Register
- Page 255 – Base Address 3 Register
- Page 258 – PCI Controller Configuration and Status Registers; shows the address map for the Control and Status Register.; PCI Controller CSR Address Map
- Page 259 – PCI Controller Non-pre-fetch Address Register
- Page 260 – PCI Controller Non-Pre-fetch Write Data Register
- Page 261 – PCI Controller Configuration Port Write Data Register
- Page 262 – PCI Controller Configuration Port Read Data Register
- Page 263 – PCI Controller Interrupt Status Register
- Page 276 – SDRAM Controller
- Page 277 – memory devices per each bank.; In t el
- Page 278 – utilizing an internal refresh counter.; Supported Configuration of the SDRAM Controller
- Page 279 – transaction to the SDRAM.; SDRAM Memory Space; “Configuration Register 0” on page 322; Initializing the SDRAM Controller; Memory Space
- Page 280 – would be attached when a two-bank configuration is written.
- Page 282 – signaling associated with this command.; SDRAM I/O For Various Commands
- Page 283 – Initializing the SDRAM
- Page 284 – followed by the issue of an auto-refresh command.; of writing to the configuration register of the SDRAM.; Page Register Allocation
- Page 285 – SDRAM Memory Accesses; Read Transfer; incremented address.; Read Cycle Timing (CAS Latency of Two Cycles); Data Transfer Sizes of AHB; SDRAM Read Example (CAS Latency of 2 Cycles)
- Page 286 – Read Burst Transfer (Interleaved AHB Reads); Write Transfer; SDRAM Shared South AHB and North AHB Access
- Page 287 – Configuration Register; with the same type of SDRAM devices.; SDRAM Write Example; SDRAM Register Overview
- Page 288 – Refresh Register; applies to all types of SDRAM (asynchronous and synchronous).; Instruction Register
- Page 289 – SDRAM Configuration Options
- Page 290 – SDRAM Burst Definitions
- Page 292 – Expansion Bus Controller
- Page 293 – Expansion Bus Address Space; Processors’ Trimmed Version of the Memory Map
- Page 294 – lowest 256 Mbytes of address.; Chip Select Address Allocation
- Page 295 – Address and Data Byte Steering; MBytes; Expansion Bus Memory Sizing
- Page 296 – Expansion Bus Address and Data Byte Steering
- Page 297 – Expansion Bus Connections; Expansion Bus Peripheral Connection
- Page 298 – Expansion Bus Interface Configuration; Cycle Type that is selected. For more information refer to section; Expansion Bus Cycle Type Selection
- Page 300 – cycle prior to the end of the T1 phase.
- Page 302 – not finish until Chip Select is deasserted by the processor.; I/O Wait Normal Phase Timing
- Page 303 – Special Design Knowledge for Using HPI mode; function signal pins for HPI as shown in; I/O Wait Extended Phase Timing; Multiplexed Output Pins for HPI Operation
- Page 304 – Registers are ignored.; HPI HCNTL Control Signal Decoding
- Page 305 – Expansion Bus Interface Access Timing Diagrams
- Page 319 – Timing and Control Registers for Chip Select 0; Section; Timing and Control Registers for Chip Select 1; Expansion Bus Register Overview
- Page 320 – Timing and Control Registers for Chip Select 2
- Page 321 – Timing and Control Registers for Chip Select 5
- Page 322 – Configuration Register 0; assertion of the reset signal.; Bit Level Definition for each of the Timing and Control Registers
- Page 323 – read only, all other bits may be written and read from the South AHB.; Configuration Register 0 Description
- Page 324 – XScale processor speed will now be operating at.; User-Configurable Field; Configuration Register 1
- Page 325 – Expansion Bus Configuration Register 1-Bit Definition
- Page 326 – Expansion Bus Controller Performance; shows simulated expansion bus throughput.; Simulated Expansion Bus Performance
- Page 328 – the South AHB and the APB.
- Page 329 – APB Interface
- Page 330 – Address Map for the APB
- Page 333 – High Speed UART; UART Timing Diagram; Start; Parity; LSB MSB; Bit Definition
- Page 334 – UART Block Diagram
- Page 335 – Configuring the UART; Setting the Baud Rate; register makes up the upper eight bits of the 16-bit divisor.; Typical Baud Rate Settings
- Page 337 – against odd parity on the received data.; UART Transmit Parity Operation
- Page 338 – Register is initialized to hexadecimal 0x60 after reset.; Using the Modem Control Signals; diagnostic testing of the UART.; UART Word-Length Select Configuration; • Data Terminal Ready
- Page 339 – UART Interrupts
- Page 341 – Transmit FIFO is half empty or less.
- Page 342 – Transmitting and Receiving UART Data
- Page 343 – will be cleared autonomously when the reset has been completed.; UART FIFO Trigger Level
- Page 344 – three most-significant bits of the byte are filled with zeros.); address locations in the; Receive Buffer Register; High-Speed UART Registers Overview
- Page 345 – Transmit Holding Register; RBR
- Page 346 – Divisor Latch High Register; “Modem; DLL
- Page 347 – Interrupt Identification Register; IER
- Page 348 – IIR
- Page 349 – FIFO Control Register; UART IDD Bit Mapping
- Page 350 – Line Control Register; FCR
- Page 351 – LCR
- Page 352 – Modem Control Register; MCR; — 0 = Normal UART operation; The OUT2 bit is used to mask the UARTs’ interrupt output to
- Page 353 – Line Status Register; LSR
- Page 354 – Modem Status Register; of the Interrupt Enable Register is set.
- Page 355 – scratch-pad register for use by the programmer.; MSR
- Page 356 – Infrared Selection Register; Infrared Data Association Serial Infrared Specification.; SPR
- Page 357 – Console UART; ISR; Console UART Registers Overview
- Page 359 – Divisor Latch Low Register
- Page 361 – Priority Levels of Interrupt Identification Register
- Page 362 – UART Interrupt Identification Bit Level Definition
- Page 365 – The OUT2 bit is used to mask the UART’s interrupt output to
- Page 367 – Modem Status Register.
- Page 368 – register for use by the programmer.
- Page 369 – that this mode is never enabled.
- Page 372 – Internal Bus Performance Monitoring Unit; Initializing the IBPMU
- Page 373 – Using the IBPMU; IBPMU Mode Selection Operation
- Page 374 – to the Intel; Occurrence Events
- Page 375 – split transfer and the first DWORD of data read is received.; Monitored Events South AHB and North AHB; Duration Events
- Page 376 – North and South Modes Event Descriptions (Sheet 1 of 2)
- Page 377 – Monitored SDRAM Events; North and South Modes Event Descriptions (Sheet 2 of 2)
- Page 378 – Internal Bus PMU Register Overview
- Page 379 – ESR
- Page 380 – Possible Event Settings
- Page 381 – set until cleared by writing a 1 to the bit.; PSR
- Page 384 – PSMR
- Page 386 – Using GPIO as Inputs/Outputs
- Page 387 – Using GPIO as Interrupt Inputs
- Page 388 – GPIO Interrupt Selections
- Page 389 – Using GPIO 14 and GPIO 15 as Clocks; are separate for
- Page 390 – GPIO Clock Frequency Select
- Page 391 – after receiving a reset.; GPIO Output Register; depending upon the status of the GPOER.; GPIO Registers Overview
- Page 392 – GPIO Output Enable Register; GPOUTR
- Page 393 – GPIO Interrupt Status Register; masked in the Interrupt Controller block.; GP Interrupt Type Register 1; pin, as described in the following table.; GPINR
- Page 394 – GPIO Interrupt Type Register 2
- Page 395 – GPIO Clock Register; MUX between the clock data and the data defined in GPOUTR.; GPCLKR
- Page 398 – Interrupt Controller; Interrupt Priority
- Page 399 – Assigning FIQ or IRQ Interrupts
- Page 400 – disable the corresponding interrupt number.; Reading Interrupt Status; the status represented on bit 31 of the Interrupt Status Register.
- Page 401 – the FIQ Status Register and the IRQ Status Registers.; Interrupt Controller Register Description; Interrupt Controller Registers
- Page 402 – Interrupt Status Register
- Page 404 – Interrupt-Enable Register
- Page 405 – Interrupt Priority Register
- Page 406 – FIQ Highest-Priority Register
- Page 409 – assume a value of all ones.; General-Purpose Timers; down counter can stop after reaching 0.
- Page 410 – processors’ Interrupt Controller
- Page 411 – Timer Register Definition; General-Purpose Timer 0; Timer Registers
- Page 412 – General-Purpose Timer 0 Reload
- Page 413 – General-Purpose Timer 1 Reload
- Page 414 – Watch-Dog Enable Register
- Page 415 – Timer Status
- Page 416 – Ethernet MAC A; Processors’ Devices with Ethernet Interface
- Page 417 – of the MII interfaces.; Ethernet Coprocessor; displays a block diagram of the Ethernet coprocessor.; Multiple Ethernet PHYS Connected to Processor; Ethernet Coprocessor Interface
- Page 418 – Ethernet Coprocessor APB Interface
- Page 420 – Transmitting Ethernet Frames with MII Interfaces; the 256-byte Transmit FIFO contained in the Ethernet coprocessor.; MDIO Write; MDIO Read; MDC
- Page 421 – unpredictable behavior.
- Page 423 – parameter specifies the Inter Frame Gap.; Receiving Ethernet Frames with MII Interfaces; Receive Engine implements the following functions:
- Page 425 – General Ethernet Coprocessor Configuration
- Page 426 – plane processors becomes a recipient of that MDC clock.
- Page 427 – writeable by the Intel XScale processor via APB bus.
- Page 428 – Transmit Control 1
- Page 429 – Transmit Control 2
- Page 430 – Receive Control 2; rxctrl2
- Page 431 – Threshold For Partially Empty
- Page 432 – Transmit Deferral Parameters
- Page 433 – Transmit Two Part Deferral Parameters 1
- Page 434 – MDIO Commands Registers; The detailed bit descriptions follow the four commands’ bit maps.; MDIO Command 1
- Page 435 – MDIO Command 3; Four registers make up the 32-bit MDIO status:; MDIO Command
- Page 436 – MDIO Status 1
- Page 437 – Address Mask Registers; Six registers make up the 48-bit Address Mask:; Address Mask 1
- Page 438 – Address Mask 2
- Page 439 – Address Mask 6; Six registers that make up the 48 bit Address Mask are:
- Page 440 – Address 1
- Page 441 – Address 5; Six registers that make up the 48 bit Address are:
- Page 442 – Threshold for Internal Clock; Six registers that make up the 48 bit Unicast Address are:
- Page 443 – Unicast Address 1
- Page 444 – Unicast Address 5
- Page 446 – Ethernet MAC B; Not all of the Intel; Processors’ with Ethernet Interface
- Page 448 – High-Speed Serial Interface Receive Operation; Processors with HSS
- Page 449 – IXP400 Software Programmer’s Guide.; High-Speed Serial Interface Transmit Operation; Interface Receive Operation” on page 448
- Page 450 – Configuration of the High-Speed Serial Interface; Software Programmer’s Guide.
- Page 452 – programmed to be inputs or outputs.
- Page 453 – IXP400 Software Programmer’s; Obtaining High-Speed, Serial Synchronization
- Page 454 – HSS Registers and Clock Configuration; IXP400 Software Release. The Intel
- Page 455 – HSS Clock and Jitter; Table 155, “HSS Tx/Rx Clock Output” on page 455; Overview of HSS Clock Configuration; HSS Tx/Rx Clock Output
- Page 456 – HSS Tx/Rx Clock Output Frequencies and PPM Error; HSS Tx/Rx Clock Output Frequencies And Their Associated Jitter; HSS Frame Output Characterization
- Page 457 – HSS Supported Framing Protocols; configured using the IxHssAcc API defined in the Intel; Jitter Definitions; Period; Pj
- Page 458 – T1 Transmit Frame; T1 Receive Frame; FBit
- Page 459 – no frame bits in this protocol.; E1 Transmit Frame
- Page 460 – configuring HSS interface for E1 operation:; MVIP; configuring the HSS interface for MVIP:; E1 Receive Frame
- Page 461 – the protocol is identical to the TX side of the protocol.; MVIP using 2.048Mbps Backplane
- Page 462 – the FIFO and is therefore not sent to the NPE.; MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame
- Page 463 – used for padding the frame due to the shorter length of the T1 frame.; MVIP, Frame Mapping a T1 Frame to an E1 Frame; MVIP, Byte Interlacing Two E1 Streams Onto a 4.096-Mbps Backplane
- Page 464 – MVIP, Byte Interleaving Two T1 Streams Onto a 4.096-Mbps Backplane
- Page 465 – the E1 frames can completely fill all the timeslots available.
- Page 468 – USB Overview
- Page 469 – Device Configuration
- Page 470 – USB Operation; Signalling Levels; Endpoint Configuration: Universal Serial Bus Device Controller
- Page 471 – decoded to represent the current state of the USB.; Bit Encoding; USB States
- Page 472 – Field Formats; NRZI Bit Encoding Example
- Page 473 – Endpoint field follows the Address field.; Endpoint Field Addressing
- Page 474 – Packet Formats; Token Packet Type; SOF Token Packet Format
- Page 475 – Handshake Packet Type; Transaction Formats; Bulk Transaction Type; Data Packet Format
- Page 476 – Isochronous Transaction Type; of isochronous transactions based on data direction are shown in; Control Transaction Type; DATA0 type transfers.; Bulk Transaction Formats
- Page 477 – uses OUT transactions.; Interrupt Transaction Type; shows the four types of interrupt transactions.; UDC Device Requests; endpoint 0 via the USB.; Interrupt Transaction Formats
- Page 478 – UDC Configuration; Host Device Request Summary
- Page 479 – UDC Hardware Connections
- Page 480 – bytes the USB host controller has sent to Endpoint 0.
- Page 481 – UDC Enable; the transmit or receive serial shifter are reset.; UDC Active; the UDC is currently involved in a transaction.
- Page 487 – Bit 6 Reserved; Bit 6 is reserved for future use.
- Page 488 – Bit 2 Reserved
- Page 490 – Bit 4 Reserved
- Page 491 – packet is ready to transmit.
- Page 492 – Bit 3 Reserved
- Page 493 – register is set if transmit interrupts are enabled.
- Page 495 – UDC Endpoint 6 Control/Status Register
- Page 500 – set if transmit interrupts are enabled.
- Page 501 – Bit 5 is reserved for future use.
- Page 510 – operate endpoint 13, an Isochronous IN endpoint.
- Page 511 – The bit’s read value is zero.
- Page 513 – data in the FIFO that Intel XScale
- Page 516 – generated on initial system reset.
- Page 517 – on initial system reset.
- Page 518 – logically ORed together to produce one interrupt request.
- Page 520 – The IR6 bit is cleared by writing a 1 to it.
- Page 522 – The IR15 bit is cleared by writing a 1 to it.
- Page 523 – packet that is corrupted.
- Page 524 – These bits are updated every SOF.
- Page 525 – input buffer is equal to the byte count +1.
- Page 526 – the number of bytes that remain to be read.
- Page 529 – loaded via direct Intel XScale
- Page 530 – from the Intel XScale
- Page 531 – UDC generates an interrupt when the EOP is received.
- Page 533 – can be loaded via direct Intel XScale
- Page 534 – removed from the UDC via a direct read from the Intel XScale
- Page 535 – UDC Data Register 11
- Page 537 – direct Intel XScale
- Page 538 – Processors’ Devices with UTOPIA
- Page 540 – UTOPIA Transmit Module; accessible features are described in the Intel; UTOPIA Level-2 Coprocessor
- Page 542 – UTOPIA Level-2 MPHY Transmit Polling
- Page 543 – UTOPIA Receive Module; IXP400 Software Programmer’s Guide
- Page 545 – The 32-bit counters will maintain the following counts:; UTOPIA Level-2 MPHY Receive Polling
- Page 546 – MPHY Polling Routines
- Page 548 – JTAG Interface; TAP Controller
- Page 549 – Loading the IDCODE register disables test logic.; Figure 100. TAP Controller State Diagram; RESET; *Note: State transitions occur based on the
- Page 550 – logic operation as the result of such an error.
- Page 551 – this state. The instruction does not change in this state.
- Page 552 – selected by the current instruction retain their previous state.
- Page 553 – JTAG Instructions
- Page 554 – Data Registers
- Page 555 – TAP controller enters the Shift-DR state.; Boundary Scan Register; JTAG Device Register Values
- Page 557 – registers, interrupt registers and SRAM via the AHB; Functional Description; A block diagram of the AHB Queue Manager is shown in; Figure 101. AHB Queue Manager
- Page 558 – AHB Interface; AHB Queue Manager Memory Map
- Page 559 – Queue Control; in internal SRAM. Configuration for each queue will consists of:
- Page 560 – will return zeroes in the data field on the AHB.; Queue Status; The following sections outline the queue status requirements.; Status Update
- Page 561 – considered nearly empty.; Flag Bus; Queue Status Flags
- Page 562 – Status Interrupts; register prior to computing the logical-OR.; Queue Access Word Registers 0 - 63; will perform the requested access to the queue in SRAM. See
- Page 563 – which contains the status.; Queue status register for the queues 0-31.
- Page 564 – Queues 32-63 Nearly Empty Status Register
- Page 565 – Interrupt 0 Status Flag Source Select Register 0 – 3
- Page 566 – Queue Interrupt Enable Register 0 – 1
- Page 567 – Word is shown in the QUECONFIG register.
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Order Number: 252480-006US
Intel
®
IXP42X Product Line of
Network Processors and IXC1100
Control Plane Processor
Developer’s Manual
September 2006
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Summary
Page 3 - Contents; Intel XScale
Intel ® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor September 2006 DM Order Number: 252480-006US 3 —Intel ® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Contents 1.0 Introduction .........................................................
Page 5 - ARM
Intel ® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor September 2006 DM Order Number: 252480-006US 5 —Intel ® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 3.6.11.2 SELDCSR JTAG Register.....................................................
Page 7 - Base Address Register, and PCI Memory Base Address
Intel ® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor September 2006 DM Order Number: 252480-006US 7 —Intel ® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 6.3 Initializing PCI Controller Configuration and Status Registers for Data Tran...
