Intel 82550 - Manual

Intel 82550

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Table of Contents:

  • Page 3 – Contents; Introduction
  • Page 4 – EEPROM Interface
  • Page 5 – Programming Recommendations; Appendices; Wake-up Functionality; Figures
  • Page 6 – Tables
  • Page 8 – Revision History
  • Page 9 – EtherExpress; Scope
  • Page 10 – Document Conventions; Device References; specific differences and exceptions will be documented.; Numbering; Decimal numbers will not be followed by a suffix.; Signal Name Representation; used for this purpose:
  • Page 13 – Adapter and Controller Overview; Adapters based on an Intel; Adapter Block Diagram; The main components of Intel Fast Ethernet adapters are:; Figure 1. 82557 Network Interface Card Block Diagram
  • Page 14 – Intel Fast Ethernet MAC Features; Early transmit complete indication.
  • Page 15 – Working with the Physical Layer; Mbps only connections, the 82557 can be interfaced to the Intel
  • Page 17 – Power Management Interface; Low Power Mode Requirements; PCI Bus Power Management Interface Specification, Revision 1.0.; Device Power States
  • Page 18 – Link Operation; and Revision ID” on page 13
  • Page 19 – PCI Interface; PCI Configuration Space; PCI configuration space of each individual PCI device.; Table 1. PCI Configuration Space
  • Page 20 – Figure 2. Command Register
  • Page 21 – Figure 3. Command Register; Table 2. Device and Revision ID
  • Page 23 – Figure 5. Base Address Register for Memory Mapping; Figure 6. Base Address Register for I/O Mapping
  • Page 24 – Expansion ROM Base Address Register (Offset 30); Table 3. Base Address Register Summary
  • Page 25 – Figure 7. Expansion ROM Base Address Register
  • Page 26 – Power Management PCI Configuration Registers; Power Management Capabilities (Offset DE); Table 4. Power Management Capabilities
  • Page 28 – Table 5. Power Management Control/Status Register
  • Page 29 – Ethernet Power Consumption Registers (Offset E2h); PCI Command Usage; Table 6. Power Consumption / Dissipation Reporting
  • Page 30 – Table 7. Generated PCI Commands; Memory Write and Invalidate; Configuration Space”
  • Page 31 – Read Align; If this bit is set, the device operates as follows:; Odd Byte Alignment Support
  • Page 33 – EEPROM and then read Flash memory or vice versa.
  • Page 35 – Host Software Interface; configurations only refer to the simplified memory mode.; The Shared Memory Architecture
  • Page 36 – Figure 8. 8255x Memory Architecture
  • Page 37 – Initializing the LAN Controller; LAN Controller Addressing Format; Table 8. Reset Commands
  • Page 38 – Table 9. Device Addressing Formats
  • Page 39 – Controlling the Device; Table 10. Alignment Requirements for 8255x Data Structures
  • Page 42 – SCB Status Word; Table 12. System Control Block; Figure 9. SCB Status Word
  • Page 43 – Table 13. SCB Status Word Bits Descriptions
  • Page 44 – Figure 10. SCB Command Word
  • Page 45 – Table 14. SCB Command Word Bits Descriptions
  • Page 47 – SCB General Pointer; for the different commands.
  • Page 48 – Statistical Counters; Table 16. SCB General Pointer for the RU Command; Table 17. Statistical Counters
  • Page 51 – PORT Interface; Port function selection code on AD3:AD0; Table 18. Port Register Location; Table 19. Port Selection Function
  • Page 52 – PORT Software Reset; command checks the following blocks:
  • Page 53 – Port Selective Reset; in; EEPROM Control Register; read from and enable writes to an external EEPROM component.
  • Page 54 – CPU Accesses to the EEPROM; EEPROM. There should be no other local bus activity at this time.; Table 21. EEPROM Control Register Locations; Figure 12. EEPROM Control Register
  • Page 55 – Software Determination of EEPROM Size
  • Page 56 – Software Read Access from the EEPROM; Figure 13. EEPROM Read Timing Diagram
  • Page 57 – Software Write Access to the EEPROM; Management Data Interface Control Register; Table 24. MDI Control Register Location
  • Page 58 – MDI Control Register; The sequence of events for a MDI write cycle is:; Table 25. Management Data Pins; Table 26. MDI Control Register Bits
  • Page 59 – MDI Read cycle; Receive Byte Count Register
  • Page 60 – Early Receive Interrupt; Table 27. Receive Byte Count Register Location; Table 28. Early Receive Interrupt Register Location
  • Page 61 – Flow Control Register; Table 29. Flow Control Registers Location
  • Page 62 – Power Management Driver Register; Table 30. Flow Control Threshold Values
  • Page 63 – Table 31. Power Management Driver Register Location; Table 32. Power Management Driver Register
  • Page 64 – General Control Register; Table 33. General Control Register Location; Table 34. General Control Register; Table 35. General Status Register Location
  • Page 65 – Shared Memory Structures; device while the CBL and RFA reside in main system memory.; Action Commands and Operating Modes; Table 10, “Alignment; Table 36. General Status Register
  • Page 66 – General Action Command Format; execution (also common to all action commands) is described below.; Beginning Execution; delayed by RU activity.; Completing Execution; Table 37. Operation Codes; Figure 14. General Action Command Format
  • Page 67 – Specific Action Commands; Figure 15. NOP Command Format
  • Page 68 – Figure 16. Individual Address Setup Command Format
  • Page 70 – Figure 17. Configure Command Format
  • Page 73 – Configuration Parameters
  • Page 80 – Table 45. Extended Statistics Functionality
  • Page 84 – Table 47. 82558 B-step Configuration Block ARP Frame IP Address
  • Page 85 – Table 48. 82558 B-step ARP Frame IP Address Mapping
  • Page 87 – Table 49. Full Duplex Functionality
  • Page 90 – Figure 18. Multicast Setup Command Format
  • Page 91 – Figure 19. Transmit Command Format
  • Page 93 – Figure 20. Transmit Buffer Descriptor
  • Page 94 – Dynamic TBD Mode; two features defined.
  • Page 95 – Transmit Command Operation
  • Page 96 – WILL NOT
  • Page 97 – Delayed CNA Interrupts; be beneficial for other systems as well.)
  • Page 98 – Figure 21. Load Microcode Command Format
  • Page 99 – Figure 22. Dump Command Format
  • Page 105 – Figure 23. Diagnose Command Format
  • Page 107 – Receive Operation; Receive Frame Area; Simplified RFA Structure
  • Page 108 – Receive Frame Descriptor Format; RECEIVE FRAME AREA
  • Page 109 – Table 52. RFD Status Bit Descriptions
  • Page 110 – Initial Receive Frame Area Structure; The link offset of each RFD in the list should point to the next RFD.; Operation of Frame Reception; discarded, they are still counted in the short frame counter.; Table 53. Actual Count in Header RFD
  • Page 111 – Configuring the Next RFD
  • Page 113 – Example 2. Numerical Calculation; Command Unit and Receive Unit Operation; Starting and Completing Control Commands; control command is accepted:; Generating and Acknowledging Interrupts
  • Page 114 – Command Unit Control; Completion of Execution.; CU Start Command
  • Page 115 – CU Resume Command; goes back to the suspended state.; CU Control Commands Response; and; Table 54. CU Control Commands: Actions at Acceptance Time
  • Page 116 – Receive Unit Control; initial RU state after reset.; Table 56. RU Control Commands: Actions at Acceptance Time
  • Page 117 – Completion of Reception.; RU Start Command; NOT
  • Page 118 – RU Resume Command; Updating SCB Status; Flow Control
  • Page 119 – PHY Based Flow Control; should not be used at the same time as frame based flow control.; Frame Based Flow Control; of frame based flow control and is described later in; Protocol Description; includes the following fields:
  • Page 120 – Pause Operation; The 82557 does not support flow control functionality.; Table 57. Flow Control Frame Format
  • Page 121 – Transmit Flow Control; defined in
  • Page 123 – Priority Aware Frame Based Flow Control; Priority Flow Control Operation; illustrates a flow control frame.; Table 58. Flow Control Configuration Bits
  • Page 124 – Half Duplex Flow Control; Modification in Switched Environments”; Collision Backoff Modification in Switched
  • Page 125 – Physical Layer Interface; different PHYs, including the 82555, are included in
  • Page 126 – MDI Register Set; The generic MDI register set is defined as follows:; Figure 26. Management Frame Structure
  • Page 127 – Control Register: Register 0; The Control register provides control over the PHY functions.
  • Page 128 – Status Register: Register 1
  • Page 129 – Identification Registers: Registers 2 and 3; Table 61. 24-bit OUI Identification Number
  • Page 130 – Auto-Negotiation Advertisement Register: Register 4
  • Page 131 – Auto-Negotiation Expansion Register: Register 6
  • Page 132 – Status and Control Register: Register 16
  • Page 133 – Special Control Register: Register 17
  • Page 134 – Clock Synthesis Test and Control Register: Register 18
  • Page 135 – 00BASE-TX Receive Error Frame Counter: Register 21
  • Page 136 – Equalizer Control and Status Register: Register 26; command, and bits 12:0 contain the data field for the command.
  • Page 137 – Special Control Register: Register 27
  • Page 138 – Auto-Negotiation Functionality; lists the priority of each of the technologies.; Table 63. LED Switch Control
  • Page 139 – Parallel Detection; Table 64. Technology Ability Field Bit Assignments; Table 65. Technology Priority
  • Page 140 – Vendor-Specific PHY Programming
  • Page 143 – Adapter Initialization; PHY Detection and Initialization
  • Page 144 – NOS Specific Initialization; Transmit Processing; For dynamic chaining:; Frame Reception; memory. Software cannot selectively disable these interrupts.
  • Page 145 – Interrupt Processing
  • Page 147 – This appendix applies only to the 82558 and subsequent devices.
  • Page 148 – Low Power Modes; D1, the PHY and CSMA units are always active.; Power Management Context After Reset; source. It is connected to the system auxiliary power good signal.; power source is used and wake up from D3
  • Page 149 – Auxiliary Power Support; reset. In this case wake up from D3; is not supported. Both the PME enable and status bits; Fixed Packet Filtering; without an active clock on the PCI bus.
  • Page 150 – Address Matching
  • Page 151 – Configuration Bits for Fixed Wake-up filters; Table 66. Fixed Wake-up Configuration Bits
  • Page 152 – Link Status Event
  • Page 153 – Flexible Filtering Terminology
  • Page 154 – Wake-up Packet Storage; controller may wake up the system without storing the packet.; 2559 and Later Generation Device Implementation; support Magic Packet.; Load Programmable Filter Command Structures; Programmable Filters Data Structure.; Programmable filters may have one of two types:; Figure 27. Command Block Structure
  • Page 158 – CRC Word calculation of a Flexible Filter; The 82559 Port commands are summarized in
  • Page 159 – Power Management Software Flow; the power down states.; Power Down without Wake-up Capabilities; Clear the PME enable bit in the PMCSR to the PME disable state.; Table 68. Dump Data Structure
  • Page 160 – Power Down with Wake-up Capabilities; required for the power down state, then this step is redundant.
  • Page 161 – Dummy Wake-up Sequence
  • Page 163 – This appendix applies to the Intel; IPCB; useful combinations of the IPCB fields.; Table 69. IPCB Structure
  • Page 164 – Table 72. IPCB Fields
  • Page 166 – Driver Interface; checksum operation are shaded.; Table 73. IPCB Structure Checksum Offload
  • Page 167 – IPCB Field Assignment; Hardware Parsing, or Scheduling modes are used.; Parameters; location of the checksum field.
  • Page 168 – IPCB usage is enabled only if the 82550 is in the Extended TxCB mode.; Data Flow; checksum is stored in the appropriate location.
  • Page 169 – Tunneling Support; Large Send; Rationale; Stack computes only one header per block.; Driver interface
  • Page 170 – IPCB Large Send; it will be less than or equal to the maximum TCP payload bytes).; Table 74. IPCB Structure Large Send
  • Page 171 – Headers Parsing
  • Page 172 – Intermediate Frames Processing
  • Page 173 – Handling the Last Frame
  • Page 174 – read access from the PCI will not affect anything.; Performance Considerations; to use the largest possible value for this parameter.; Features Co-existence; Large Send and Checksum; Large Send and checksum are orthogonal.; Large Send and Software Parsing; Large Send cannot be used with software parsing.; Large Send and Scheduling Assist; RCV Checksum Processing
  • Page 175 – Frame Types; right after the optional VLAN field.; Verification Types; Other protocols will not have a checksum.; VLAN Tagging
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Intel 8255x 10/100 Mbps Ethernet
Controller Family

Open Source Software Developer Manual

January 2006

Revision 1.3

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Summary

Page 3 - Contents; Introduction

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual iii Contents Contents 1 Introduction .................................................................................................................................... 1 1.1 Scope.................................

Page 4 - EEPROM Interface

iv Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents 5 EEPROM Interface ....................................................................................................................... 25 6 Host Software Interface ..................................

Page 5 - Programming Recommendations; Appendices; Wake-up Functionality; Figures

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual v Contents 7.3.6 100BASE-TX Receive Error Frame Counter: Register 21 ................................... 127 7.3.7 Receive Symbol Error Counter: Register 22 .........................................................

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