Page 2 - ii; Datasheet
ii Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSU...
Page 3 - iii; Revision History
Datasheet iii Networking Silicon — 82540EP Revision History Date Revision Notes Apr 2002 0.25 Initial Release Nov 2002 1.0 Changed document status to Intel Confidential. Jan 2003 1.1 Section 1.0. Replaced Block Diagram Section 2.6. Added Table footnote Section 4.1, 4.2, 4.3. Replaced tablesSection 5...
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82540EP — Networking Silicon iv Datasheet Note: This page is intentionally left blank.
Page 5 - Contents
Datasheet v Networking Silicon — 82540EP Contents 1.0 Introduction......................................................................................................................... 1 1.1 Document Scope ..............................................................................................
Page 7 - Introduction; The Intel
Networking Silicon — 82540EP Datasheet 1 1.0 Introduction The Intel ® 82540EP Gigabit Ethernet Controller is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with crit...
Page 8 - Ar
82540EP — Networking Silicon 2 Datasheet Figure 1. Gigabit Ethernet Controller Block Diagram Tx Arb PCI i/ f PCI I /F RX M A C TX MA C TX d e scri p to r e ngin e Data Alignment FI F O s PC I Core DM A MA C Co re 82540EP Ar chit ectu re P acke t Bu ff e r Targ et C ont ro l C o nt ro l, Stat us &...
Page 9 - Document Scope
Networking Silicon — 82540EP Datasheet 3 1.1 Document Scope This document contains datasheet specifications for the 82540EP Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information. 1.2 Reference Documents This application assumes that ...
Page 11 - Features of the 82540EP Gigabit Ethernet Controller; PCI Features
Networking Silicon — 82540EP Datasheet 5 2.0 Features of the 82540EP Gigabit Ethernet Controller 2.1 PCI Features 2.2 MAC Specific Features Features Benefits PCI Revision 2.3 support for 32-bit wide interface at 33 MHz and 66 MHz • Application flexibility for LAN on Motherboard (LOM) or embedded sol...
Page 12 - PHY Specific Features; Host Offloading Features
82540EP — Networking Silicon 6 Datasheet 2.3 PHY Specific Features 2.4 Host Offloading Features Features Benefits Integrated PHY for 10/100/1000 Mbps full and half duplex operation • Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions IEEE 802.3ab Auto-Negotiat...
Page 13 - Manageability Features
Networking Silicon — 82540EP Datasheet 7 2.5 Manageability Features Features Benefits Manageability features: SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE • Network management flexibility On-board SMB por t • Enables IPMI and ASF implementations • Allows packets routing to and from either LAN port ...
Page 14 - Additional Device Features
82540EP — Networking Silicon 8 Datasheet 2.6 Additional Device Features 2.7 Technology Features Features Benefits Four activity and link indication outputs that directly drive LEDs • Link and activity indications (10, 100, and 1000 Mbps) on each port Programmable LED functionality • Software definab...
Page 15 - Signal Descriptions; Signal Type Definitions; PCI Address, Data and Control Signals; Address and data signals are multiplexed on the same PCI pins. A
Networking Silicon — 82540EP Datasheet 9 3.0 Signal Descriptions Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 3.1 Signal Type Definitions The signals of the 82540EP con...
Page 16 - The Frame signal is driven by the
82540EP — Networking Silicon 10 Datasheet CBE[3:0]# TS Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, CBE[3:0]# define the bus command. In the data phase, CBE[3:0]# are used as byte enables. The byte ...
Page 17 - Arbitration Signals; is an input to the
Networking Silicon — 82540EP Datasheet 11 3.2.2 Arbitration Signals 3.2.3 Interrupt Signal 3.2.4 System Signals 3.2.5 Error Reporting Signals Symbol Type Name and Function REQ# TS Request Bus. The Request Bus signal is used to request control of the bus from the arbiter. This signal is point-to-poin...
Page 18 - Power Management Signals; EEPROM and Serial FLASH Interface Signals
82540EP — Networking Silicon 12 Datasheet 3.2.6 Power Management Signals 3.2.7 Impedance Compensation Signals 3.2.8 SMB Signals 3.3 EEPROM and Serial FLASH Interface Signals Symbol Type Name and Function LAN_PWR_GOOD I Power Good (Power-on Reset). The Power Good signal is used to indicate that stabl...
Page 19 - Miscellaneous Signals; LED Signals
Networking Silicon — 82540EP Datasheet 13 3.4 Miscellaneous Signals 3.4.1 LED Signals 3.4.2 Other Signals FL_CE# O FLASH Chip Enable Output. Used to enable FLASH device. FL_SCK O FLASH Serial Clock Output . The clock rate of the serial FLASH interface is approximately 1 MHz. FL_SI O FLASH Serial Dat...
Page 20 - PHY Signals; Crystal Signals
82540EP — Networking Silicon 14 Datasheet 3.5 PHY Signals 3.5.1 Crystal Signals 3.5.2 Analog Signals Symbol Type Name and Function XTAL1 I Crystal One . The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It can be connected to either an oscillator or crystal. If a crystal is used, Crystal Two ...
Page 21 - Test Interface Signals; Digital Supplies
Networking Silicon — 82540EP Datasheet 15 3.6 Test Interface Signals 3.7 Power Supply Connections 3.7.1 Digital Supplies 3.7.2 Analog Supplies Symbol Type Name and Function JTAG_TCK I JTAG Clock. JTAG_TDI I JTAG TDI. JTAG_TDO O JTAG TDO. JTAG_TMS I JTAG TMS. JTAG_TRST# I JTAG Reset. This is an activ...
Page 22 - Ground and No Connects
82540EP — Networking Silicon 16 Datasheet 3.7.3 Ground and No Connects 3.7.4 Control Signals Symbol Type Name and Function GND P Ground. NC P No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors should not be connected to these pins. Symbol Type Name and Function CT...
Page 23 - Voltage, Temperature, and Timing Specifications; Absolute Maximum Ratings; Table 1. Absolute Maximum Ratings
Networking Silicon — 82540EP Datasheet 17 4.0 Voltage, Temperature, and Timing Specifications Note: The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 4.1 Abs...
Page 24 - DC Specifications; Table 3. DC Characteristics; Table 2. Recommended Operating Conditions
82540EP — Networking Silicon 18 Datasheet 4.3 DC Specifications V AH Analog High VDD Range 3.3V ± 10% 3 3.3 3.6 V V D Core Digital Voltage Range 1.5V ± 5% 1.425 1.5 1.575 V V AL Analog Low VDD Range 2.5V ± 5% 2.375 2.5 2.625 V a. Sustained operation of the device at conditions exceeding these values...
Page 25 - Table 7. Power Specifications - Complete Subsystem
Networking Silicon — 82540EP Datasheet 19 Table 5. Power Specifications - D3cold D3cold - wake-up enabled D3cold - wake disabled - max power savings mode disabled D3cold - wake disabled - max power savings mode enabled a unplugged/no link @10 Mbps @100Mbps Typ Icc (mA) Max Icc (mA) Typ Icc (mA) Max ...
Page 27 - AC Characteristics; Table 10. 25 MHz Clock Input Requirements
Networking Silicon — 82540EP Datasheet 21 4.4 AC Characteristics Table 9. AC Characteristics: 3.3 V Interfacing Symbol Parameter Min Typ Max Unit PCICLK Clock frequency in PCI mode 66 MHz Table 10. 25 MHz Clock Input Requirements Symbol Parameter a Min Typ Max Unit fi_TX_CLK TX_CLK_IN frequency 25 -...
Page 28 - Timing Specifications; PCI Bus Interface Clock; Figure 1. AC Test Loads for General Output Pins; Figure 2. PCI Clock Timing
82540EP — Networking Silicon 22 Datasheet 4.5 Timing Specifications Note: Timing specifications are subject to change. Verify with your local Intel sales office that you have the latest information before finalizing a design. 4.5.1 PCI Bus Interface 4.5.1.1 PCI Bus Interface Clock Figure 1. AC Test ...
Page 29 - PCI Bus Interface Timing; Table 15. PCI Bus Interface Timing Parameters; Figure 3. PCI Bus Interface Output Timing Measurement
Networking Silicon — 82540EP Datasheet 23 4.5.1.2 PCI Bus Interface Timing NOTES: 1. Output timing measurements are as shown.2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ...
Page 30 - Table 16. PCI Bus Interface Timing Measurement Conditions
82540EP — Networking Silicon 24 Datasheet Figure 4. PCI Bus Interface Input Timing Measurement Conditions V TH V TL V TEST PCI_CLK T SU V TEST Input V MAX V TEST V TL V TH InputValid T H Table 16. PCI Bus Interface Timing Measurement Conditions Symbol Parameter PCI 66 MHz 3.3 v Unit VTH Input measur...
Page 32 - Link Interface Timing; Table 17. Rise and Fall Times; Table 19. Link Interface Clock Requirements
82540EP — Networking Silicon 26 Datasheet 4.5.2 Link Interface Timing 4.5.3 EEPROM Interface a. The EEPROM clock is derived from a 125 MHz internal clock. Table 17. Rise and Fall Times Symbol Parameter Condition Min Max Unit TR Clock rise time 0.8 V to 2.0 V 0.7 ns TF Clock fall time 2.0 V to 0.8 V ...
Page 33 - Package and Pinout Information; . The nominal ball pitch is; Device Identification; Figure 10. 82540EP Device Identification Markings
Networking Silicon — 82540EP Datasheet 27 5.0 Package and Pinout Information This section describes the 82540EP device, manufactured in a 196-lead ball grid array measuring 15mm X 15mm. External product identification is shown in Figure 10 . The nominal ball pitch is 1mm. The pin number-to-signal ma...
Page 34 - Package Information; dimensions are detailed in
82540EP — Networking Silicon 28 Datasheet 5.2 Package Information The 82540EP device is a 196-lead ball grid array (TFBGA) measuring 15 mm 2 . The package dimensions are detailed in Figure 11 . The nominal ball pitch is 1 mm. Figure 11. 82540EP Mechanical Specifications
Page 35 - Thermal Specifications; JA; Table 18. Thermal Characteristics
Networking Silicon — 82540EP Datasheet 29 5.3 Thermal Specifications The 82540EP device is specified for operation when the ambient temperature (TA) is within the range of 0 ° C to 70 ° C. TC (case temperature) is calculated using the equation: TC = TA + P ( θ JA - q JC) TJ (junction temperature) is...
Page 36 - Pinout Information; Table 20. PCI Arbitration Signals; Table 23. Error Reporting Signals
82540EP — Networking Silicon 30 Datasheet 5.4 Pinout Information Table 19. PCI Address, Data, and Control Signals Signal Pin Signal Pin Signal Pin PCI_AD[0] N7 PCI_AD[16] K1 CBE0# M4 PCI_AD[1] M7 PCI_AD[17] E3 CBE1# L3 PCI_AD[2] P6 PCI_AD[18] D1 CBE2# F3 PCI_AD[3] P5 PCI_AD[19] D2 CBE3# C4 PCI_AD[4]...
Page 38 - Table 32. Test Interface Signals; Table 33. Digital Power Signals
82540EP — Networking Silicon 32 Datasheet Table 31. PHY Signals Signal Pin Signal Pin Signal Pin XTAL1 K14 MDI0+ C13 MDI2+ F13 XTAL2 J14 MDI1- E14 MDI3- H14 REF B14 MDI1+ E13 MDI3+ H13 MDI0- C14 MDI2- F14 Table 32. Test Interface Signals Signal Pin Signal Pin Signal Pin JTAG_TCK L14 JTAG_TDO M14 JTA...
Page 45 - Visual Pin Reference
Networking Silicon — 82540EP Datasheet 39 5.5 Visual Pin Reference Figure 12. Ball Grid Array / Pin Reference for 196-TFBGA (thru-the-top view) • A B C D E F G H J K L M N P 14 NC PHY REF MDI- [0] NC MDI- [1] MDI- [2] VSS MDI- [3] XTAL2 XTAL1 JTCK JTDO SDP[0] NC 14 13 TEST CTRL 25 MDI+ [0] VSS MDI+ ...
