Toshiba TMP92CM22FG - Manuals

TMP92CM22 2007-02-16 92CM22-4 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CM22FG, their names and functions are as follows. 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92CM22FG. Figure 2.1.1 Pin Assignment Diagram (100-Pin QFP) TMP92CM22 QF...

TMP92CM22 2007-02-16 92CM22-5 2.2 Pin Names and Functions The following tables show the names and functions of the input/output pins. Table 2.2.1 Pin Names and Functions (1/2) Pin Names Number of Pins I/O Functions D0 to D7 8 I/O Data (Lower): Data bus D0 to D7. P10 to P17 D8 to D15 8 I/O I/O Port 1...

TMP92CM22 2007-02-16 92CM22-7 3. Operation This section describes the basic components, functions and operation of the TMP92CM22. 3.1 CPU The TMP92CM22 incorporates a high-performance 32-bit CPU (The TLCS-900/H1 CPU). For a description of this CPU’s operation, please refer to the section of this dat...

TMP92CM22 2007-02-16 92CM22-8 3.1.2 Reset Operation When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low for at least 20 system clocks...

TMP92CM22 2007-02-16 92CM22-9 Figure 3.1.1 Reset Timing Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to “10” to use 8-bit external bus, or set it to “01” to use 16-bit external bus. Table 3.1.2 Operation Mode Setup Table Mode Setting Input Pin Operation RESET AM1 AM0 16-bit external ...

TMP92CM22 2007-02-16 92CM22-10 3.2 Memory Map Figure 3.2.1 shows memory map of TMP92CM22. Figure 3.2.1 Memory Map Note 1: When use emulator, optional 64 Kbytes of 16-Mbyte area are used to control emulator. Therefore, don’t use this area. Note 2: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH)....

TMP92CM22 2007-02-16 92CM22-11 3.3 Clock Function and Standby Function TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reducing circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 Sys...

TMP92CM22 2007-02-16 92CM22-12 The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure. Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called...

TMP92CM22 2007-02-16 92CM22-13 3.3.1 Block Diagram of System Clock Figure 3.3.2 Block Diagram of Dual Clock and System Clock ÷ 4 ÷ 16 ÷ 8 ÷ 4 ÷ 2 X2 fc/16 fc/8 fc/4 fc/2 ÷ 8 φ T φ T0 f FPH ÷ 2 ÷ 2 f SYS f iO fc PLLCR<FCSEL> Clock gear High- frequency oscillator X1 PLLCR<PLLON> Warm-up ti...

TMP92CM22 2007-02-16 92CM22-17 3.3.4 Clock Doubler (PLL) PLL outputs the f PLL clock signal, which is four times as fast as f OSCH . A reset initializes PLL to stop status, setting to PLLCR register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the...

TMP92CM22 2007-02-16 92CM22-18 Example 2: PLL stopping PLLCR EQU 10E8H LD (PLLCR), 10XXXXXXB ; Changes fc from 40 MHz to10 MHz. LD (PLLCR), 00XXXXXXB ; Stop PLL. X: Don’t care Limitation point on the use of PLL 1. When PLL is started, don’t set fc from f OSCH to f PLL at same time. Don’t setting: LD...

TMP92CM22 2007-02-16 92CM22-19 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in for reduction EMI (Unnecessary radius noise) and reinforcement EMS (Measure of endure noise), allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (...

TMP92CM22 2007-02-16 92CM22-20 (2) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) (Setting method) The oscillator is disabled and starts operation as buffer by wr...

TMP92CM22 2007-02-16 92CM22-21 (3) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that is in the state which is fetch impossibility by stopping of c...

TMP92CM22 2007-02-16 92CM22-22 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1, or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: a. ...

TMP92CM22 2007-02-16 92CM22-25 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt ...

TMP92CM22 2007-02-16 92CM22-26 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<SELDRV, DRVE> register. Table 3.3.5, Table 3.3.6 shows the state of these pins in STOP mode. After...

TMP92CM22 2007-02-16 92CM22-29 3.4 Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and by the built-in interrupt controller. The TMP92CM22 has a total of 41 interrupts divided into the following types: Interrupts generated by CPU: 9 sources (Software i...

TMP92CM22 2007-02-16 92CM22-30 Figure 3.4.1 Interrupt and Micro DMA Processing Sequence Interrupt processing Interrupt vector “V” read Interrupt request F/F clear Interrupt specified by micro DMA start vector? PUSH PC PUSH SR SR<IFF2:0> ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 P...

TMP92CM22 2007-02-16 92CM22-31 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L, TLCS-900/H, and TLCS-900/L1. (1) The CPU reads the interrupt vector from the interrupt controlle...

TMP92CM22 2007-02-16 92CM22-34 3.4.2 Micro DMA In addition to general-purpose interrupt processing, the TMP92CM22 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless ...

TMP92CM22 2007-02-16 92CM22-35 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address a...

TMP92CM22 2007-02-16 92CM22-38 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circui...

TMP92CM22 2007-02-16 92CM22-39 Figure 3.4.3 Block Diagram of Interrupt Controller Interrup t request signal to CPU M icro DM A s tar t ve cto r set ting reg is ter During ST OP 36 3 3 3 1 6 2 2 4 6 34 4-input OR INT0 to I NT3 Micro DMA channel p ri ori ty encode r Priority encode r DMA0V DMA1V DMA2V...

TMP92CM22 2007-02-16 92CM22-40 (1) Interrupt priority setting registers Symbol Name Address 7 6 5 4 3 2 1 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W INTE12 INT1&INT2 enable D0H 0 0 0 0 0 0 0 0 − INT3 − − − − I3C I3M2 I3M1 I3M0 − − R R/W INTE3 INT3 enable D1H Note: Always write...

TMP92CM22 2007-02-16 92CM22-41 Symbol Name Address 7 6 5 4 3 2 1 0 INTAD INT0 IADC IADM2 IADM1 IADM0 I0C I0M2 I0M1 I0M0 R R/W R R/W INTE0AD INT0&INTAD enable F0H 0 0 0 0 0 0 0 0 INTTC1 (DMA1) INTTC0 (DMA0) ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 R R/W R R/W INTETC01 INTTC0& INT...

TMP92CM22 2007-02-16 92CM22-49 3.5 Port Function The TMP92CM22 features 50-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions ...

TMP92CM22 2007-02-16 92CM22-60 3.5.5 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O...

TMP92CM22 2007-02-16 92CM22-63 3.5.7 Port 9 (P90 to P92) Port 9 is 3-bit general-purpose I/O port. Each bit can be set individually for input or output. In addition to functioning as a general-purpose I/O port, port 9 can also function as a serial bus interface input (SCK (Clock signal in SIO mode),...

TMP92CM22 2007-02-16 92CM22-64 Port 9 Register 7 6 5 4 3 2 1 0 Bit symbol P92 P91 P90 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port 9 Control Register 7 6 5 4 3 2 1 0 Bit symbol P92C P91C P90C Read/Write W After reset 0 0 0 Function 0: Input 1: Output Po...

TMP92CM22 2007-02-16 92CM22-65 3.5.8 Port A (PA0 to PA2, PA7) Port A is 4-bit general-purpose input port with pull-up resistor. Figure 3.5.16 Port A Port A Register 7 6 5 4 3 2 1 0 Bit symbol PA7 PA2 PA1 PA0 Read/Write R R After reset Data from external port Data from external port Figure 3.5.17 Reg...

TMP92CM22 2007-02-16 92CM22-66 3.5.9 Port C (PC0, PC1, PC3, PC5, and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port C to input port. In addition to functioning as a general-purpose I/O port, port C can also function as a input...

TMP92CM22 2007-02-16 92CM22-69 Port C Register 7 6 5 4 3 2 1 0 Bit symbol PC6 PC5 PC3 PC1 PC0 Read/Write R/W R/W R/W After reset Data from external port (Note) Data from external port (Note) Data from external port (Note) Note: Output latch register is set to 1. Port C Control Register 7 6 5 4 3 2 1...

TMP92CM22 2007-02-16 92CM22-70 3.5.10 Port D (PD0 to PD3) Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port D to input port. In addition to functioning as a general-purpose I/O port, port D can also function as an input pin (INT4 and ...

TMP92CM22 2007-02-16 92CM22-71 (2) PD2 (TB1OUT0) and PD3 (TB1OUT1) In addition to function as I/O port, port PD0 and PD1 can also function as timer channel output pins TB1OUT0 and TB1OUT1. Figure 3.5.23 Port D (PD2 and PD3) Internal data bus Direction control (on bit basis) Reset PDCR write PD write...

TMP92CM22 2007-02-16 92CM22-75 (3) Port PF2 ( CTS0 , SCLK0) and port PF5 ( CTS1 , SCLK1) In addition to function as I/O port, port PF2 and PF5 can also function as CTS input pin of serial channel or SCLK I/O pin. Figure 3.5.27 Port F (PF2 and PF5) (4) Port PF6 and port PF7 These ports are general-pu...

TMP92CM22 2007-02-16 92CM22-78 3.6 Memory Controller 3.6.1 Function TMP92CM22 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area. (2) Connecting memory specificati...

TMP92CM22 2007-02-16 92CM22-79 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. • C...

TMP92CM22 2007-02-16 92CM22-80 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address area is specified...

TMP92CM22 2007-02-16 92CM22-84 (4) Wait control The external bus cycle completes a wait of two states at least (100 ns at f SYS = 20 MHz). Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as...

TMP92CM22 2007-02-16 92CM22-87 • External read/write bus cycle (0 waits at WAIT pin input mode) • External read/write bus cycle (n waits at WAIT pin input mode) CS WR RD Address Input Output Read Write CLKOUT (20 MHz) D7 to D0 D7 to D0 T1 T2 WAIT Sampling CS WR RD Address Output CLKOUT (20 MHz) D7 t...

TMP92CM22 2007-02-16 92CM22-89 (6) Connecting external memory Figure 3.6.1 shows an example of how to connect external memory to the TMP92CM22. This example connects ROM and SRAM in 16-bit width. Figure 3.6.1 Example of External Memory By resetting, TMP92CM22 function as output port. Output latch of...

TMP92CM22 2007-02-16 92CM22-90 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CM22 supports ROM access of the page mode. ROM access of th...

TMP92CM22 2007-02-16 92CM22-91 3.6.5 List of Registers The memory control registers and the settings are described as follows. For the addresses of the registers, see list of special function registers in section 5. (1) Control registers The control register is a pair of BnCSL and BnCSH. (“n” is a n...

TMP92CM22 2007-02-16 92CM22-93 BEXCSL 7 6 5 4 3 2 1 0 Bit symbol BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 Read/Write W W After reset 0 1 0 0 1 0 BEXWW[2:0] Specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 sta...

TMP92CM22 2007-02-16 92CM22-94 (1) Block address area specification register A start address and range in the block address are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start address similarly rega...

TMP92CM22 2007-02-16 92CM22-98 (2) The cautions at the time of the functional change of a CSn . A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset...

TMP92CM22 2007-02-16 92CM22-99 3.7 8-Bit Timers (TMRA) The TMP92CM22 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • 8-bit interval timer mode • 16-bit...

TMP92CM22 2007-02-16 92CM22-100 3.7.1 Block Diagrams Figure 3.7.1 TMRA01 Block Diagram φ T1 φ T16 φ T256 8-bit comparato r (CP1) 8-bit comparato r (CP0) 8-bit up counter (UC0 ) 2 n over flo w 8-bit up counter (UC1 ) Ti mer flip- flop TA1FF Match detect Match detect 8-bit timer regist er TA1REG φ T1 ...

TMP92CM22 2007-02-16 92CM22-102 3.7.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The prescaler’s operation can be controlled using TA01RUN<TA0PRUN> in the timer control register. Setting <TA0PRUN> to “1” starts the count; setting <TA...

TMP92CM22 2007-02-16 92CM22-106 7 6 5 4 3 2 1 0 Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode PWM cycle 00: Reserved 01: 2 6 10: ...

TMP92CM22 2007-02-16 92CM22-107 7 6 5 4 3 2 1 0 Bit symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode PWM cycle 00: Reserved 01: 2 6 10: ...

TMP92CM22 2007-02-16 92CM22-108 7 6 5 4 3 2 1 0 Bit symbol TA1FFC1 TA1FFC0 TA1FFCIE TA1FFCIS Read/Write R/W After reset 1 1 0 0 Function 00: Invert TA1FF 01: Set TA1FF to “1” 10: Clear TA1FF to “0” 11: Don’t care TA1FF control for inversion 0: Disable 1: Enable TA1FF Inversion signal select0: TMRA0 ...

TMP92CM22 2007-02-16 92CM22-109 TMRA3 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA3FFC1 TA3FFC0 TA3FFCIE TA3FFCIS Read/Write R/W After reset 1 1 0 0 Function 00: Invert TA3FF 01: Set TA3FF to “1” 10: Clear TA3FF to “0” 11: Don’t care TA3FF control for inversion 0: Disable 1: Enable TA3FF...

TMP92CM22 2007-02-16 92CM22-110 Symbol Address 7 6 5 4 3 2 1 0 − W TA0REG 1102H Undefined − W TA1REG 1103H Undefined − W TA2REG 110AH Undefined − W TA3REG 110BH Undefined Note: Read-modify-write instruction is prohibited for above registers. Figure 3.7.9 Register for TMRA Timer Register (TA0REG to T...

TMP92CM22 2007-02-16 92CM22-111 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. When set function and count data, TMRA0 and TMRA1 should be stopped. 1. Generating interrupts at a fixed interval (using TMRA1) To generate inter...

TMP92CM22 2007-02-16 92CM22-114 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up-counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counte...

TMP92CM22 2007-02-16 92CM22-119 Table 3.7.4 Relationship of PWM Cycle and 2 n Counter PWM cycle TAxxMOD<PWMx1:0> 2 6 (x64) 2 7 (x128) 2 8 (x256) TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> Clock gear SYSCR1 <GEAR2:0> System clock SYSCR0 <SYSCK> − φ T1...

TMP92CM22 2007-02-16 92CM22-121 3.8.1 Block Diagram Figure 3.8.1 Block Diagram of TMRB0 Capture, external interrupt control Ti mer flip- flop control Match detection Match detection 32 16 8 4 2 φ T1 φ T4 φ T16 Run/ clear φ T1 φ T4 φ T16 TB0MOD<TB0CLK1:0> Pr escaler clock: φ T0 Selecto r Regist...

TMP92CM22 2007-02-16 92CM22-123 3.8.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock ( φ T0) is a divided clock (Divided by 8) from selected clock by the register SYSCR1<GEAR1:0> of clock gear. This prescaler can be started or stopped usin...

TMP92CM22 2007-02-16 92CM22-126 (6) Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (IN...

TMP92CM22 2007-02-16 92CM22-128 TMRB0 Mode Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 TB0MOD (1182H) Read/Write R/W W R/W After reset 0 0 1 0 0 0 0 0 Function Always write “0”. Always write “0”. Software capture control 0: Software capturer 1: Undefined Ca...

TMP92CM22 2007-02-16 92CM22-129 TMRB1 Mode Register 7 6 5 4 3 2 1 0 Bit symbol TB1CT1 TB1ET1 TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0 TB1MOD (1192H) Read/Write R/W W R/W After reset 0 0 1 0 0 0 0 0 TB1FF1 Inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC12 is loade...

TMP92CM22 2007-02-16 92CM22-130 TMRB0 Flip-flop Control Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FFC1 TB0FFC0 TB0FFCR (1183H) Read/Write W R/W W * After reset 1 1 0 0 0 0 1 1 TB0FF0 inversion trigger 0: Trigger disable 1: Trigger enable Function Always write “11”. I...

TMP92CM22 2007-02-16 92CM22-131 TMRB1 Flip-flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TB1FF1C1 TB1FF1C0 TB1C1T1 TB1C0T1 TB1E1T1 TB1E0T1 TB1FFC1 TB1FFC0 TB1FFCR (1193H) Read/Write W * R/W W * After reset 1 1 0 0 0 0 1 1 TB1FF0 inversion trigger 0: Trigger disable 1: Trigger enable Function TB1F...

TMP92CM22 2007-02-16 92CM22-133 3.8.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals in this example, the interval time is set the timer register TB0RG1H/L to generate the interrupt INTTB01. 7 6 5 4 3 2 1 0 TB0RUN ← 0 0 X X − 0 X 0 Stop TMRB0. INTETB0 ...

TMP92CM22 2007-02-16 92CM22-138 Figure 3.8.13 One-shot Pulse Output (without delay) 2. Frequency measurement The frequency of the external clock can be measured in this mode. Frequency is measured by the 8-bit timers TMRA23 and the 16-bit timer/event counter. TMRA23 is used to setting of measurement...

TMP92CM22 2007-02-16 92CM22-141 3.9 Serial Channels (SIO) The TMP92CM22 includes 2 serial I/O channels. Each channel is called SIO0 and SIO1. For both channels either UART Mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. • I/O interface mode Mode 0 :...

TMP92CM22 2007-02-16 92CM22-145 3.9.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR1<GEAR2:0> is divided by 8 and input to the prescaler as φ T0. The prescaler can be run only case of selecting the baud rate ge...

TMP92CM22 2007-02-16 92CM22-147 • Integer divider (N divider) For example, when the f C = 39.3216 MHz, the input clock frequency = φ T2, the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows: ∗ Clock state Clock gear: 1/1 (f C ) f ...

TMP92CM22 2007-02-16 92CM22-148 Table 3.9.3 UART Baud Rate Selection (when using baud rate generater and BR0CR<BR0ADDE> = 0) Unit (kbps) f SYS [MHz] Input Clock Frequency Divider φ T0 (f SYS /4) φ T2 (f SYS /16) φ T8 (f SYS /64) φ T32 (f SYS /256) 9.8304 2 76.800 19.200 4.800 1.200 ↑ 4 38.400 ...

TMP92CM22 2007-02-16 92CM22-149 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate gene...

TMP92CM22 2007-02-16 92CM22-152 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt...

TMP92CM22 2007-02-16 92CM22-161 3.9.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous cloc...

TMP92CM22 2007-02-16 92CM22-164 3. Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to “0” and set enable the interrupt level (1 to 6) to the transfer interrupts. In the transfer interrupt program, the receiving operation should be d...

TMP92CM22 2007-02-16 92CM22-165 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting serial channel mode register SC0MOD0<SM1:0> to 01. In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR...

TMP92CM22 2007-02-16 92CM22-168 Example: To link two slave controllers serially with the master controller using the system clock f IO as the transfer clock. • Master controller setting Main routine PFCR ← − − − − − − 0 1 PFFC ← − − − − − − X 1 Set PF0 to TXD0, and set PF1 to RXD0 pin. INTES0 ← 1 1 ...

TMP92CM22 2007-02-16 92CM22-169 3.9.5 Support for IrDA Mode SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. Figure 3.9.24 Block Diagram of IrDA (1) Modulation of transmission data When the transmission data is 0, output “H” lev...

TMP92CM22 2007-02-16 92CM22-171 As the same reason, + (16 − K)/16 division function in the baud rate generator of SIO0 cannot be used to generate 115.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 division function cannot be used. Table 3.9.5 shows baud rate and pulse ...

TMP92CM22 2007-02-16 92CM22-172 3.10 Serial Bus Interface (SBI) The TMP92CM22 has a 1-channel serial bus interface. Serial bus interface (SBI0) include following 2 operation modes. • I 2 C bus mode (Multi master) • Clocked-synchronous 8-bit SIO mode The serial bus interface is connected to an extern...

TMP92CM22 2007-02-16 92CM22-173 3.10.2 Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface 0 control register 1 (SBI0CR1) • Serial bus interface 0 control register 2 (SBI0CR2) • Serial bus interface 0 data buffer regis...

TMP92CM22 2007-02-16 92CM22-174 3.10.4 I 2 C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I 2 C bus mode. Serial Bus Interface Control Register 1 7 6 5 4 3 2 1 0 Bit symbol BC2 BC1 BC0 ACK SCK2...

TMP92CM22 2007-02-16 92CM22-178 3.10.5 Control in I 2 C Bus Mode (1) Acknowledge mode specification Set the SBI0CR1<ACK> to 1 for operation in the acknowledge mode. The TMP92CM22 generates an additional clock pulse for an acknowledge signal when operating in master mode. In the transmitter mod...

TMP92CM22 2007-02-16 92CM22-183 (14) Software reset function The software reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. When write first “10” next “01” to SBI0CR2<SWRST1:0>, reset signal is inputted to serial bus interface circuit, and circui...

TMP92CM22 2007-02-16 92CM22-187 2. If <MST> = 0 (Slave mode) In the slave mode the TMP92CM22 operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBE0 interrupt request generate when the TMP92CM22 receives a slave address or a GENERAL CALL fr...

TMP92CM22 2007-02-16 92CM22-188 (4) Stop condition generation When SBI0SR<BB> = 1, the sequence for generating a stop condition is started by writing “111” to SBI0CR2<MST, TRX, PIN> and “0” to SBI0CR2<BB>. Do not modify the contents of SBI0CR2<MST, TRX, PIN, BB> until a stop ...

TMP92CM22 2007-02-16 92CM22-190 3.10.7 Clocked-synchronous 8-bit SIO Mode Control The following registers are used to control and monitor the operation status when the serial bus interface (SBI) is being operated in clocked synchronous 8-bit SIO mode. Serial Bus Interface 0 Control Register 1 7 6 5 ...

TMP92CM22 2007-02-16 92CM22-199 3.11 Analog/Digital Converter The TMP92CM22 incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are ...

TMP92CM22 2007-02-16 92CM22-201 AD Mode Control Register 1 7 6 5 4 3 2 1 0 Bit symbol VREFON I2AD − − − ADCH2 ADCH1 ADCH0 ADMOD1 (12B9H) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function VREF application control 0: OFF 1: ON IDLE2 0: Stop 1: Operate Always write “0”. Always write“0”. Always write ...

TMP92CM22 2007-02-16 92CM22-206 3.11.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VR...

TMP92CM22 2007-02-16 92CM22-209 (5) AD conversion time 84 states (8.4 μ s at f SYS = 20 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREG0H/L to ADREG7H/L) store the results of AD conve...

TMP92CM22 2007-02-16 92CM22-211 3.12 Watchdog Timer (Runaway detection timer) The TMP92CM22 contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as n...

TMP92CM22 2007-02-16 92CM22-213 3.12.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) 1. Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchd...

TMP92CM22 2007-02-16 92CM22-215 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Power supply voltage Vcc − 0.5 to 4.0 Input voltage VIN − 0.5 to Vcc + 0.5 V Output current (1 pin) IOL 2 Output current (1 pin) IOH − 2 Output current (Total) Σ IOL 80 Output curr...

TMP92CM22 2007-02-16 92CM22-217 DC Characteristics (2/2) Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = − 40 to 85°C Parameter Symbol Condition Min Typ. Max Unit Output low voltage V OL IOL = 1.6 mA 0.45 Output high voltage V OH IOH = − 400 μ A 2.4 V Input leakage current I LI 0.0 ≤ Vin ≤ VCC 0.02 5 Output...

TMP92CM22 2007-02-16 92CM22-218 4.2 AC Characteristics 4.2.1 Basis Bus Cycle Read cycle Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = − 40 to 85°C No. Parameter Symbol Min Max f SYS = 20 MHz (fc = 40 MHz) f SYS = 125 kHz (fc = 4 MHz) Unit 1 OSC period (X1/X2) t OSC 25 250 25 250 ns 2 System clock period (...

TMP92CM22 2007-02-16 92CM22-219 (1) Read cycle (0 waits, fc = f OSCH , f FPH = fc/1) Note: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. CLKOUT t CL t TK t AD t HA WAIT A0 to A23 X1 t OSC CSx t CYC t CH t KT t AR t RK t HR t RR D...

TMP92CM22 2007-02-16 92CM22-220 (2) Write cycle (0 waits, fc = f OSCH , f FPH = fc/1) Note: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. X1 CLKOUT A0 to A23 D0 to D31 WAIT RD Data output t OSC t CL t CH t CYC t TK t KT t AW t WK...

TMP92CM22 2007-02-16 92CM22-222 4.2.2 Page ROM Read Cycle (1) 3-2-2-2 mode Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = − 40 to 85°C No. Parameter Symbol Min Max f SYS = 20 MHz (fc = 40 MHz) f SYS = 125 kHz (fc = 4 MHz) Unit 1 System clock period ( = T) t CYC 50 8000 50 8000 ns 2 A0, A1 → D0 to D31 input...

TMP92CM22 2007-02-16 92CM22-223 4.3 AD Conversion Characteristics Parameter Symbol Min Typ. Max Unit Analog reference voltage ( + ) V REFH VCC − 0.2 VCC VCC Analog reference voltage ( − ) V REFL VSS VSS VSS + 0.2 AD converter power supply voltage A VCC VCC VCC VCC AD converter power supply ground A ...

TMP92CM22 2007-02-16 92CM22-225 4.6 Interrupt, Capture Note: Symbol “X” in the following table means the period of clock “f SYS ”, it’s same period of the system clock “f SYS ” for CPU core. The period of f SYS depends on the clock gear setting or changing high-speed oscillator/low-speed oscillator ...

TMP92CM22 2007-02-16 92CM22-226 4.7 Recommended Oscillation Circuit TMP92CM22 is evaluated by below oscillator vender. When selecting external parts, make use of this information. Note 1: Total loads value of oscillation is sum of external (or internal) loads (C1 and C2) and floating loads of actual...

TMP92CM22 2007-02-16 92CM22-227 (2) TMP92CM22 recommended ceramic oscillator: Murata Manufacturing Co., Ltd. Following table shows circuit parameter recommended. Parameter of Elements Running Condition IC Name Oscillation Frequency [MHz] Type Item of Oscillator (Old number) C1 [pF] C2 [pF] Rf [ Ω ] ...

TMP92CM22 2007-02-16 92CM22-228 5. Table of Special Function Registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 8 Kbytes address space from 000000H to 001FFFH. (1) I/O port (2) Interrupt controller (3) DMA controller (4) Memory controller (5) Clock gear...

TMP92CM22 2007-02-16 92CM22-229 Table 5.1 I/O Register Address Map [1] I/O port Address Name Address Name Address Name Address Name 0000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH P1 P1CR P1FC 0010H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH P4 P4CR P4FC P5 P5CR P5FC P6 P6CR P6FC P7 P7CR P7FC 0...

TMP92CM22 2007-02-16 92CM22-249 AD converter (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 ADR41 ADR40 ADR4RF R R ADREG4L AD result register 4 low 12A8H Undefined 0 ADR49 ADR48 ADR47 ADR46 ADR45 ADR44 ADR43 ADR42 R ADREG4H AD result register 4 high 12A9H Undefined ADR51 ADR50 ADR5RF R R ADREG5L AD resul...

TMP92CM22 2007-02-16 92CM22-251 6. Port Section Equivalent Circuit Diagram ■ Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active “1” when t...

TMP92CM22 2007-02-16 92CM22-255 7. Points to Note and Restrictions (1) Notation 1. The notation for built-in I/O registers is as follows register symbol <Bit symbol>. Example: TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN. 2. Read-modify-write instructions (RMW) An instruction i...

TMP92CM22 2007-02-16 92CM22-257 8. Package Dimensions P-LQFP100-144-0.50F Unit: mm