Toshiba TMP92CM22FG - Manual

Toshiba TMP92CM22FG

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Table of Contents:

  • Page 2 – Preface; Thank you very much for making use of Toshiba microcomputer LSIs.
  • Page 3 – CMOS 32-Bit Microcontrollers; Outline and Device Characteristics; which processes mass data.; SYS; RESTRICTIONS ON PRODUCT USE; or
  • Page 4 – NMI; OSCH
  • Page 6 – Pin Assignment and Functions; Assignment
  • Page 7 – Pin Names and Functions; Pin Names
  • Page 9 – data bus to process instructions more quickly.
  • Page 10 – Operation; s at fc
  • Page 11 – Outline of Operation Mode; Mode Setting Input Pin
  • Page 12 – Map; Note 3: On emulator; signal and; signal are asserted, when provisional
  • Page 13 – Clock Function and Standby Function; This chapter is organized as follows:
  • Page 14 – Figure 3.3.1 System Clock Block Diagram
  • Page 15 – Block Diagram of System Clock; Figure 3.3.2 Block Diagram of Dual Clock and System Clock
  • Page 19 – PLL outputs the f; PLL; clock signal, which is four times as fast as f; . A reset initializes; Be careful to judge an end of lockup time.
  • Page 20 – When PLL is started, don’t set fc from f; to f
  • Page 21 – Noise Reduction Circuits; (3) SFR protection of register contents; MHz to 10 MHz condition.
  • Page 22 – when the external oscillator is used.
  • Page 23 – executed with protection on state.
  • Page 24 – Controller; AD converter
  • Page 27 – mode halt state by an interrupt.
  • Page 28 – STOP; Table 3.3.4 Sample Warm-up Times after Rrelease of STOP Mode; at f
  • Page 31 – ) is identical to the EI7 instruction. DI
  • Page 32 – Figure 3.4.1 Interrupt and Micro DMA Processing Sequence
  • Page 33 – General-purpose Interrupt Processing; (4) The CPU increases the interrupt nesting counter INTNEST by 1 (
  • Page 36 – DMA; micro DMA burst function as below.
  • Page 37 – Figure 3.4.2 Timing for Micro DMA Cycle
  • Page 40 – Interrupt Controller Operation; The flag is cleared to 0 in the following cases:
  • Page 41 – Figure 3.4.3 Block Diagram of Interrupt Controller
  • Page 42 – (1) Interrupt priority setting registers
  • Page 43 – Function
  • Page 51 – Port Function
  • Page 62 – Don’t use this setting
  • Page 65 – output latch are set to “1”.
  • Page 66 – Port 9 ODE Register
  • Page 67 – Port A Register
  • Page 68 – output. Resetting sets port C to input port.
  • Page 71 – Port C Register; Port C Control Register
  • Page 72 – output. Resetting sets port D to input port.
  • Page 73 – channel output pins TB1OUT0 and TB1OUT1.
  • Page 77 – input
  • Page 80 – Specifies a start address and a block size for 4-block address area.
  • Page 81 – Control Register and Operation after Reset Release; release and necessary settings.
  • Page 82 – Basic Functions and Register Setting; (i) Setting memory start address register
  • Page 86 – pin input mode; input pins. It continuously samples the
  • Page 89 – External read/write bus cycle (0 waits at; External read/write bus cycle (n waits at
  • Page 91 – This example connects ROM and SRAM in 16-bit width.
  • Page 92 – mode is specified only in block address area 2.
  • Page 93 – List of Registers; BnCSL
  • Page 95 – BEXCSL; BEXCSH
  • Page 96 – (1) Block address area specification register
  • Page 100 – (2) The cautions at the time of the functional change of a; Prohibition of use of an NMI function; CSn
  • Page 101 – Timers; -bit interval timer mode
  • Page 102 – Diagrams
  • Page 104 – Operation of Each Circuit; Table 3.7.2 Prescaler Output Clock Resolution
  • Page 108 – TMRA01 Mode Register
  • Page 109 – TMRA23 Mode Register
  • Page 110 – TMRA1 Flip Flop Control Register
  • Page 111 – TMRA3 Flip-Flop Control Register
  • Page 112 – Symbol Address
  • Page 113 – Operation in Each Mode
  • Page 116 – TA1REG
  • Page 121 – Table 3.7.5 Timer Mode Setting Registers
  • Page 123 – Diagram
  • Page 125 – As the input clock, one of the prescaler internal clocks
  • Page 128 – After a reset the values of TB0FF0 and TB0FF1 are undefined. If “00” is
  • Page 130 – TMRB0 Mode Register
  • Page 131 – TMRB1 Mode Register
  • Page 132 – TMRB0 Flip-flop Control Register
  • Page 133 – TMRB1 Flip-flop Control Register
  • Page 135 – timer register TB0RG1H/L to generate the interrupt INTTB01.
  • Page 140 – measurement
  • Page 143 – operation of channel 0 is explained below.; This chapter contains the following sections:
  • Page 147 – SYSCR1 is divided by 8 and input to the prescaler as; Clock Resolution; T32 among the prescaler outputs.
  • Page 149 – In I/O interface mode
  • Page 150 – Input Clock; trigger of timer
  • Page 151 – IO
  • Page 154 – then
  • Page 163 – data to or receiving data from an external shift register.
  • Page 166 – Baud rate
  • Page 167 – set as described below. This explanation applies to channel 0
  • Page 170 – clock f; as the transfer clock.
  • Page 171 – Support for IrDA Mode; Figure 3.9.25 Example of Modulation of Transmission Data
  • Page 173 – Output Pulse
  • Page 174 – P9ODE
  • Page 175 – C Bus Mode
  • Page 176 – C Bus Mode Control Register; Serial Bus Interface Control Register 1
  • Page 180 – Set the SBI0CR1 to 1 for operation in the acknowledge mode. The; LOW
  • Page 185 – register, the start condition is generated.
  • Page 189 – processes according to conditions listed in the next table.
  • Page 190 – , the sequence for generating a stop condition is started by
  • Page 192 – Serial Bus Interface 0 Control Register 1; Serial Bus Interface 0 Data Buffer Register
  • Page 201 – Converter; instruction is executed.
  • Page 203 – Figure 3.11.3 Register for AD Converter
  • Page 208 – To turn off the switch between VREFH and VREFL, program a 0 to; Table 3.11.1 Analog Input Channel Selection
  • Page 211 – s at f; 0 MHz) are required for the AD conversion of one channel.
  • Page 213 – Figure 3.12.1 Block Diagram of Watchdog Timer
  • Page 215 – Registers; when detecting runaway.; Disable control; Enable control
  • Page 217 – Characteristics; Absolute Maximum Ratings; Parameter Symbol
  • Page 219 – Parameter; Symbol; Condition
  • Page 220 – Basis Bus Cycle
  • Page 221 – The timing chart above is an example.; CLKOUT; Data input
  • Page 222 – Data output
  • Page 224 – Page ROM Read Cycle; Unit
  • Page 225 – AD Conversion Characteristics
  • Page 227 – Capture; and INT0 to INT3 interrupts
  • Page 228 – Recommended Oscillation Circuit; use of this information.; (1) Example of oscillation connection circuit; Rd
  • Page 229 – Following table shows circuit parameter recommended.
  • Page 230 – Table of Special Function Registers (SFRs)
  • Page 231 – Address; Address; Name; Address; Name; Address; Name
  • Page 251 – Symbol Name
  • Page 253 – Port Section Equivalent Circuit Diagram; Reading the circuit diagram
  • Page 257 – Points to Note and Restrictions; same memory location by using one instruction.
  • Page 259 – Dimensions
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TOSHIBA Original CMOS 32-Bit Microcontroller

TLCS-900/H1 Series

TMP92CM22FG
















Semiconductor Company

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Summary

Page 2 - Preface; Thank you very much for making use of Toshiba microcomputer LSIs.

Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”.

Page 3 - CMOS 32-Bit Microcontrollers; Outline and Device Characteristics; which processes mass data.; SYS; RESTRICTIONS ON PRODUCT USE; or

TMP92CM22 2007-02-16 92CM22-1 CMOS 32-Bit Microcontrollers TMP92CM22FG 1. Outline and Device Characteristics TMP92CM22 is high-speed advanced 32-bit microcontroller developed for controlling equipment, which processes mass data. TMP92CM22FG is a microcontroller, which has a high-performance CPU (900...

Page 4 - NMI; OSCH

TMP92CM22 2007-02-16 92CM22-2 (4) External memory expansion • Expandable up to 16 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus ･･･ Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output: 4 channels (6) 8-bit timers...

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