Page 2 - Technology Information; Technology features of FEPS are as follows:; Ethernet core
2 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP terface (CEI) for slave and DMA transfers with the SBus (via SBA). The SBAprovides buffering and bus conversion between the SBus and the channel en-gine interface. Interrupts from the channel engine go directly ...
Page 4 - Sun Microelectronics; Figure 1. STP2002QFP Block Diagram
4 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 1. STP2002QFP Block Diagram SBus SBA Channel Engine Interface SCSI_IRQ ENET_IRQ PP_IRQ SCSI DVMA ENET DMA PP DMA FAS366 BigMac PP Core SCSI_Channel ENET_Channel PP_Channel SCSI Bus MII Interface Parallel ...
Page 5 - Pin Descriptions; The signal pins are grouped by function in the following tables.
5 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 1.6 Pin Descriptions The signal pins are grouped by function in the following tables. Table 1: SBus Signals Signal Name Type Pin Count Description SB_D[31:0] I/O 32 SBus data SB_A[27:0] I/O 28 SBus address SB_SEL I...
Page 7 - Table 4: Parallel Port Signals
7 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Table 4: Parallel Port Signals Signal Name Type Pin Count Description PP_DATA[7:0] I/O 8 Parallel port data bus PP_STB I/O 1 Parallel port data strobe PP_BSY I/O 1 Parallel port busy PP_ACK I/O 1 Parallel port ackn...
Page 8 - Signal Name
8 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Table 6: Power/Ground/Other Signals Signal Name Type Pin Count Description VDD_CORE 4 VSS_CORE 4 V DD 21 V SS 52 Reserved 1 MODE 1 Mode select (stand alone/chipset) Total 83
Page 9 - SB; US; SBus Capabilities
9 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, SB US A DAPTER 2 2.1 Introduction The SBus Adapter (SBA) is the layer between the Channel Engine Interface(CEI) and the SBus. It provides one master port on the SBus side to funnelthree DMA channel engines (CE) ont...
Page 10 - Theory of Operation
10 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP slave accesses from SBus. The physical address is decoded to select a targetCE to respond to the access. A physical address that cannot be resolved to theselection of any channel engine will cause SBus Adapter ...
Page 12 - SCSI C; HANNEL; The following are some of the features of the FAS366 core:
12 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP SCSI C HANNEL 3 3.1 Introduction The SCSI channel consists of SCSI DVMA (also referred to as SCSI channelengine) and FAS366, a “Fast and Wide” SCSI controller core. The SCSIDVMA provides two 64-byte buffers use...
Page 14 - ARALLEL; Parallel Port FIFO Operation
14 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP P ARALLEL P ORT C HANNEL 4 4.1 Introduction The parallel port interface implementation of FEPS is almost identical to theone on the STP2000 Master I/O controller chip to leverage the existing devicedriver. The ...
Page 15 - Bidirectional Parallel Port Interface; Bidirectional signal configuration
15 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, None of these conditions will cause draining if P_ERR_PEND = 1, indi- cating that a memory error has occurred. If condition 4 or 5 occurs when theP_ERR_PEND bit is 1, the P_FIFO will be invalidated and all dirty d...
Page 17 - OCR; ). The function of these bits is defined as; SBus Clock
17 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, The desired handshake protocol can be selected using the ACK_OP (acknowledge operation) and BUSY_OP (busy operation) bits of the opera- tions configuration register ( OCR ). The function of these bits is defined a...
Page 20 - transfer control register; DIR
20 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 4.3.1.2 Bidirectional Operation Bidirectional data transfer over the parallel port can be accomplished by theuse of either of two master/slave protocols. The “master write” protocol or the“master read/write” pr...
Page 21 - DSW; The; Signal
21 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, When DIR is set to 1, the pins configured as bidirectional change direction and their corresponding direction control pins are set accordingly. Note thatthe input status pins (ERR, SLCT, PE), which are readable in...
Page 22 - plus 3 to 4 SBus clocks, due to synchronization delays. The width of
22 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP These two bits allow selection of one of four possible handshake protocols. The following table summarizes the protocol definitions for transfers to theparallel port from the peripheral device. For all protocol...
Page 23 - =1. The configuration of P_ACK as an input will not hinder the
23 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, as required to gate further transfers but not as a handshake signal. The oper-ation of the interface as defined assumes the bidirectional sense of each signalhas been configured as follows: DIR =1, DS_DSEL =1, ACK...
Page 24 - has a tolerance of; =1. Reference the data transfer diagram in
24 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 7. 4.3.1.3.4 Handshake with ACK and BUSY: (BUSY_OP=1, ACK_OP=1) Both P_ACK (PP_ACK) and P_BSY (PP_BSY) are generated in response toa data strobe. P_BSY (PP_BSY) will be generated off of the leading edge ...
Page 25 - is used to define the
25 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 4.3.1.4 Master Read/Write Protocol (Xerox Mode) This section describes the parallel port operation while master read cycles areperformed. Operation while master write cycles are performed is the same asis describe...
Page 28 - THERNET; Functional Description
28 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP E THERNET C HANNEL 5 5.1 Introduction The Ethernet channel is a dual-channel intelligent DMA controller on the sys-tem side, and an IEEE 802.3 Media Access Control (MAC) on the networkside. It is designed as a ...
Page 29 - • Host interface buffer
29 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, For TCP packets, hardware support is provided for TCP checksum compu- tation. On transmit, it is assumed that the entire packet is loaded into the localFIFO before its transmission begins. The checksum is computed...
Page 33 - Receive Clock Domain
33 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Receive Clock Domain This clock is used to drive the receive protocol engine in the BigMAC core.It is sourced by the MII and has the operating frequency of 2.5/25 MHz 100ppm. The 2.5/25 MHz version of this clock (...
Page 34 - Receive Free Buffer Descriptor Ring; the software, except for diagnostic purposes.
34 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP The size of the descriptor ring is programmable, and it can be varied in the range of 16–256 in increments of 16 descriptors: 16, 32, 48, ..., 240, 256. 5.2.6 Receive Free Buffer Descriptor Ring For receive ope...
Page 36 - Error Conditions and Recovery
36 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 5.3 Error Conditions and Recovery There are two types of error conditions that can be encountered during thenormal operation of the Ethernet channel: fatal errors and non-fatal errors. Fa-tal errors are errors ...
Page 39 - Programmer’s Reference; Descriptor layout; The pointers to descriptor ring base addresses
39 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 5.4 Programmer’s Reference 5.4.1 Overview During normal operation, the software-to-hardware interaction is primarilyperformed via the host memory data structures, with a minimal command/sta-tus handshake (less tha...
Page 41 - nearest burst boundary and execute a full DVMA burst read.; Figure 10. Transmit Host Data Structures
41 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, nearest burst boundary and execute a full DVMA burst read. Figure 10. Transmit Host Data Structures Control Word Data Buffer Pointer Control Word Data Buffer Pointer Control Word Data Buffer Pointer Control Word D...
Page 44 - Figure 11. Receive Host Data Structure; Table 14: TxFIFO Data Structures: Control Word Layout; Field
44 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 11. Receive Host Data Structure The software has the capability to read and write the FIFOs (including tags) at any time, using programmed I/O instructions. This feature should beused for diagnostic purp...
Page 46 - Figure 12. TxFIFO Organization
46 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 12. TxFIFO Organization 5.4.8 Other User Accessible Resources Besides the host and local memory data structures, the hardware provides aprogrammed I/O path to a variety of hardware resources for initiali...
Page 47 - less specified otherwise.; Figure 13. RxFIFO Organization
47 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, less specified otherwise. Figure 13. RxFIFO Organization junk junk junk junk Frame #1 Data Frame #1 Data Frame #1 Control 32-Bit Mode Wrap- Around FIFO 64-Bit Mode 0 31 32 Tag_1 63 Tag_0 Addr_0 junk 0 .... 001 0 ....
Page 48 - ESTABILITY
48 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP T ESTABILITY 6 6.1 Introduction This section describes the features of the JTAG Test Access Port (TAP) andother testability structures for the FEPS. The JTAG macro which implementsthe IEEE Standard 1149.1-1990 ...
Page 49 - The following sections describe each of these blocks.
49 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, The above signals describe the I/O signals of the JTAG macro. The JTAG macro is composed of the following blocks: TAP controller, instruction reg-ister, instruction decode logic, bypass register, internal register...
Page 56 - Special JTAG Instructions
56 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 23. 6.3 Special JTAG Instructions In addition to the mandatory instructions, the FEPS JTAG implements somespecial instructions. 6.3.1 Debug Modes 6.3.1.1 Dumping Internal State Using the DEBUG instructio...
Page 57 - Int_Scan_Enable shifts the clock between the SBus_CLK and the
57 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 6.4 Clock Stop Pin This pin can deterministically stop the clocks in FEPS. After the instructionregister is updated with the SEL_CCR instruction, an initializing pattern isloaded into the CCR scan data register. I...
Page 58 - ROGRAMMING; Parallel Port Channel Registers; Table 18: Control/Status Register Address
58 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP P ROGRAMMING M ODEL 7 7.1 Introduction Refer to the FEPS application note (STB0106) for programming notes and acomplete address map for the registers for all interfaces. 7.2 Parallel Port Channel Registers 7.2....
Page 59 - Table 19: Control/Status Register Definition
59 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, The RESET state of this register is as follows: P_ERR_PEND = 0 P_INT_EN = 0 P_INVALIDATE = 0 P_SLAVE_ERR = 0 P_RESET = 0 P_EN_DMA = 0 P_EN_CNT = 0 P_TC = 0 P_BURST_SIZE = 0 P_TCI_DIS = 0 P_EN_NEXT = 0 P_DMA_ON = 0...
Page 61 - FEPS minor revision number.
61 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, P_BURST_SIZE: This field defines the sizes of SBus read and write bursts used by the FEPSfor parallel port transfers. All reads from memory will be one size, either 4,8, or 1 word (in “no burst mode). SBus writes ...
Page 62 - DMA Address and Next Address Register; A write to the P_ADDR register will invalidate the P_FIFO. A; Table 21: DMA Address and Next Address Register Address; Table 22: DMA Address and Next Address Register Definition
62 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.2 DMA Address and Next Address Register This 32-bit read/write register contains the virtual address for parallel portDMA transfers. It is implemented as a 32-bit loadable counter which pointsto the next by...
Page 63 - ferred before it expires.; Table 23: Byte Count Register Address; Table 24: Byte Count Register Definition
63 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.2.3 Byte Count Register This register is implemented as a 24-bit down counter. When reading this reg-ister as a word, bits 31:24 will read as 0s. The register should be loaded witha 24-bit byte count which, if e...
Page 64 - Register
64 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.4 Test Control/Status Register Table 25: Test Control/Status Register Address Register Physical Address Access Size Test control/Status register (P_TST_CSR) 0xC80_000C 4 bytes
Page 65 - Table 26: Test Control/Status Register Definition
65 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Note:The P_TST_CSR is intended for diagnostic and test use only and should never be written while a DMA transfer is active 7.2.5 Hardware Configuration Register Table 26: Test Control/Status Register Definition Fi...
Page 66 - Data setup to data strobe.; This 7-bit quantity is used to define data strobe and ac-; IDLE; Table 28: Hardware Configuration Register Definition
66 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP DSS : Data setup to data strobe. This 7-bit quantity is used to define several differ- ent timing specifications for the interface. The contents of this field of the reg-ister are used to load a hardware timer ...
Page 67 - Table 29: Operation Configuration Register Address
67 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, IDLE : When this bit is set, it indicates that the parallel port data transfer state ma-chines are in their idle states. The state machines should be idle when chang-ing direction and/or configuring operational mo...
Page 70 - Table 31: Parallel Data Register Address
70 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.7 Parallel Data Register The data register is an 8-bit read/write port used to transfer data to and from the external device. In programmed I/O mode data written to this register ispresented to the I/O pins...
Page 71 - Table 33: Transfer Control Register Address
71 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Table 33: Transfer Control Register Address Register Physical Address Access Size Transfer Control register (P_TCR) 0xC80_0015 1 byte
Page 72 - DS; Table 34: Transfer Control Register Definition
72 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP DS : Reading this bit reflects the state of the bidirectional PP_STB pin. Writingthis bit with DS_DSEL=0 or with DS_SEL=1 and DIR=0 will cause the valuewritten to be driven onto PP_STB. The reset state of the o...
Page 73 - Table 37: Input Register Address
73 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, DMA direction. The state of the DIR bit is reflected in the P_WRITE bit ofthe P_CSR. Reset state of this bit is 1. 7.2.9 Output Register The output register is an 8-bit read/write register whose contents are drive...
Page 74 - Table 39: Interrupt Control Register Address
74 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.11 Interrupt Control Register This 16-bit read/write register is used to specify operation of the parallel portinterrupts. Interrupt enables, polarity, and IRQ pending bits are contained inthis register. Th...
Page 76 - SCSI Channel Registers; Table 41: Control/Status Register Address; Table 42: Control/Status Register Definition
76 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP ing a 0 to these locations leaves the bit(s) unchanged. ACK_IRQ : When set, an interrupt is pending due to the receipt of PP_ACK. The interruptis set on the 0 to 1 transition of PP_ACK. This interrupt is intend...
Page 78 - This bit must be asserted at the end of each DMA transfer. In; This bit is set when a DVMA read or write request is pend-
78 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP This bit is set to indicate that FAS366 has asserted its interrupt signal. OnceFAS366 asserts its interrupt signal, all the bytes in prefetch buffers aredrained to the host memory, before setting this bit or ge...
Page 79 - Table 44: SCSI Address Register Address; Table 45: SCSI Address Register Definition; Table 46: SCSI Byte Count Register Address; Table 47: SCSI Byte Count Register Definition
79 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, place. Note: To determine the exact address at which an error occurred, two cases have to be dealt with. These are the following: Case 1: The error occurs on the SCSI Bus For this case, the starting address of the...
Page 83 - For the case of SCSI read (data-in phase only) when FAS366 is; Table 50: FAS366 Transfer Counter Low Register (Read Only) Address
83 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.4 FAS366 (SCSI Controller Core) Registers The FAS366 registers are used by the CPU to control the operation of theSCSI bus. Through these registers, the CPU configures, commands, and mon-itors data, command, and...
Page 87 - Table 64: FAS366 Select/Reselect Bus ID Register Address; Table 65: FAS366 Select/Reselect Bus ID Register Definition; Table 66: FAS366 Interrupt Register Address
87 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, s 7.4.8 FAS366 Select/Reselect Bus ID Register The select/reselect bus ID register is an eight-bit, write-only register thatstores encoded values for the SCSI bus ID and the selection/reselection ID. 7.4.9 FAS366 ...
Page 88 - Table 69: FAS366 Select/Reselect Time-Out Register Definition; Table 71: FAS366 Sequence Step Register Definition
88 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.10 FAS366 Select/Reselect Time-Out Register The select/reselect time-out register is an eight-bit, write-only register thatspecifies the amount of time to wait for a response during selection or rese-lectio...
Page 89 - 2 FAS366 Synchronous Transfer Period Register; Table 72: FAS366 Synchronous Transfer Period Register Address; Table 74: FAS366 FIFO Flags Register Address; Table 75: FAS366 FIFO Flags Register Definition
89 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.4.12 FAS366 Synchronous Transfer Period Register The synchronous transfer period register is an eight-bit, write-only register.This register specifies the minimum time, in input clock cycles, between lead-ing ed...
Page 90 - 6 FAS366 Clock Conversion Factor Register; Table 76: FAS366 Synchronous Offset Register Address; Table 77: FAS366 Synchronous Offset Register Definition; Table 78: FAS366 Configuration #1 Register Address; Table 79: FAS366 Configuration #1 Register Definition; Table 80: FAS366 Clock Conversion Factor Register Address
90 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.15 FAS366 Configuration #1 Register The configuration #1 register is an eight-bit, read/write register that specifiesdifferent operating options for the FAS366. 7.4.16 FAS366 Clock Conversion Factor Registe...
Page 91 - Table 81: FAS366 Clock Conversion Factor Register Definition; Table 82: FAS366 Status #2 Register Address; Table 84: FAS366 Test Register Address; Table 85: FAS366 Test Register Definition
91 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.4.17 FAS366 Status #2 Register The status #2 register is a read-only register that indicates detailed status in-formation about the FIFO, the DMA interface, the sequence counter, thetransfer counter, the recomma...
Page 92 - Table 87: FAS366 Configuration #2 Register Definition; Table 88: FAS366 Configuration #3 Register Address; Table 89: FAS366 Configuration #3 Register Definition
92 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.19 FAS366 Configuration #2 Register Configuration #2 is an eight-bit read/write register that specifies different op-erating options for the FAS366. 7.4.20 FAS366 Configuration #3 Register This eight-bit, r...
Page 93 - Ethernet Channel Registers; To ensure proper operation of the hardware after a software reset; Table 90: FAS366 Recommand Counter Register Address
93 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, After power-up or a chip reset, and until the recommand counter register is loaded, the FAS366 part-unique ID code is readable from the recommandcounter low register. This part-unique ID indicates FAS366 family co...
Page 94 - Table 95: Global Configuration Register Definition
94 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP When both bits read back as 0s, the software is allowed to continue toprogram the hardware. 7.5.2 Global Configuration Register This five-bit register is used to determine the system-related parameters thatcont...
Page 97 - Table 99: ETX Transmit Pending Command Address; Table 100: ETX Configuration Register Address; Table 98: Global Status Register Definition
97 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.5 ETX Transmit Pending Command This one-bit command must be issued by the software for every packet thatthe driver posts to the hardware. The bit is set to 1 using a programmed I/Owrite to the defined address....
Page 98 - The transmit descriptor pointer must be initialized to a 2K byte-; Table 101: ETX Configuration Register Definition
98 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP The default value of this register is set to 0x3FE 7.5.7 ETX Transmit Descriptor Pointer (RW) This 29-bit register points to the next descriptor in the ring. The 21 most sig-nificant bits are used as the base a...
Page 99 - ETX Transmit Data Buffer Base Address; Table 103: ETX Transmit Descriptor Ring Size Register Address
99 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Default: 0xF; 256 descriptor entries. 7.5.9 ETX Transmit Data Buffer Base Address 7.5.10 ETX Transmit Data Buffer Displacement (RO) This 10-bit counter keeps track of the next DVMA read burst address. It isused as...
Page 100 - Table 109: ETX Transmit Data Pointer Register Definition; Table 110: ETX TxFIFO Packet Counter Register Address
100 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.11 ETX Transmit Data Pointer This 32-bit register points to the next DVMA read burst address. Its contentsis the sum of the transmit data buffer base address and the transmit data bufferdisplacement. 7.5.1...
Page 101 - Table 111: ETX TxFIFO Packet Counter Register Definition; Table 112: ETX TxFIFO Write Pointer Register Address; Table 113: ETX TxFIFO Write Pointer Register Definition
101 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.13 ETX TxFIFO Write Pointer This nine-bit loadable counter points to the next location in the FIFO that willbe loaded with SBus data, the checksum, or the frame control word. Thecounter increments by 1 or 2 (...
Page 104 - The TxFIFO should never be accessed using PIOs during nor-; Table 122: ETX TxFIFO Address
104 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP • Writing to the lower aperture will load 32 bits of data and clear the tag bit to 0 at the addressed location • Writing to the higher aperture will load 32 bits of data and set the tag bit to 1 at the address...
Page 105 - Table 124: ERX Configuration Register Definition; Table 125: ERX Receive Descriptor Pointer Register Address
105 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.20 ERX Receive Descriptor Pointer Table 124: ERX Configuration Register Definition Field Bits Description Type Rx_DMA_Enable 0 When set to 1’, the DMA operation of thechannel is enabled. The load control stat...
Page 106 - The receive descriptor pointer must be initialized to a 2K byte-; Table 126: ERX Receive Descriptor Pointer Register Definition; Table 127: ERX Receive Data Buffer Pointer Register Address; Table 128: ERX Receive Data Buffer Pointer Register Definition
106 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Note: The receive descriptor pointer must be initialized to a 2K byte- aligned value after power-on or software reset. 7.5.21 ERX Receive Data Buffer Pointer This 28-bit loadable counter keeps track of the nex...
Page 107 - Table 129: ERX RxFIFO Write Pointer Register Address
107 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Table 129: ERX RxFIFO Write Pointer Register Address Register Physical Address Access Size ERX RxFIFO Write Pointer register 0x8C0_400C 4 bytes
Page 108 - Table 132: ERX RxFIFO Shadow Write Pointer Register Definition
108 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.23 ERX RxFIFO Shadow Write Pointer This nine-bit register points to the first word of the packet that is either cur-rently being loaded or is about to be loaded into the FIFO. The register isloaded with th...
Page 109 - Table 136: ERX RxFIFO Packet Counter Definition
109 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.25 ERX RxFIFO Packet Counter This eight-bit up/down counter keeps track of the number of frames that cur-rently reside in the RxFIFO. The counter increments when a frame is loadedinto the FIFO, and decrements...
Page 110 - The RxFIFO should never be accessed using PIOs during nor-; Table 138: ERX State Machine Register Definition
110 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.27 ERX RxFIFO For diagnostic purposes, a PIO path has been provided into the RxFIFO.When using PIOs, the configuration of the RxFIFO will be 512 × 33bits. In order to be able to access all the bits in the ...
Page 111 - Table 140: XIF Configuration Register Address; Table 141: XIF Configuration Register Definition
111 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.28 XIF Configuration Register This 10-bit register determines the parameters that control the operation ofthe transceiver interface. Table 140: XIF Configuration Register Address Register Physical Address Acc...
Page 112 - To ensure proper operation of the hardware, when a loop-back; Table 142: TX_MAC Software Reset Command Address; Table 143: TX_MAC Configuration Register Address
112 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Default: 0x140. Note: To ensure proper operation of the hardware, when a loop-back configuration is entered or exited, a global initialization sequenceshould be performed. 7.5.29 TX_MAC Software Reset Command ...
Page 113 - Table 144: TX_MAC Configuration Register Definition
113 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Table 144: TX_MAC Configuration Register Definition Field Bits Description Type TX_MAC_Enable 0 When set to 1, the TX_MAC will start requestingpacket data from the ETX, and the transmitEthernet protocol execution...
Page 114 - Table 146: TX_MAC InterPacketGap1 Register Definition
114 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Note: To ensure proper operation of the TX_MAC, the TX_MAC_En bit must always be cleared to 0 and a delay imposed before a PIO writeto any of the other bits in the TX_MAC Configuration register or anyof the MA...
Page 120 - Table 174: TX_MAC Excessive Collision Counter Definition; Table 175: TX_MAC Late Collision Counter Address
120 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.45 TX_MAC Excessive Collision Counter 7.5.46 TX_MAC Late Collision Counter This eight-bit loadable counter increments for every transmit frame that hasexperienced a late collision. It indicates the number ...
Page 123 - Table 183: RX_MAC Configuration Register Definition
123 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Note: To ensure proper operation of the RX_MAC, the RX_MAC_En bitmust always be cleared to 0 and a delay of 3.2 msec imposed before aPIO write to any of the other bits in the RX_MAC configuration regis-ter or any...
Page 124 - Table 185: RX_MAC RxMaxFrameSize Register Definition; Table 187: RX_MAC RxMinFrameSize Register Definition
124 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP may be polled, and when this bit reads back as a 0, all the registersmentioned above may be written. 7.5.51 RX_MAC RxMaxFrameSize Register Default value: 0x05EE. 7.5.52 RX_MAC RxMinFrameSize Register Default v...
Page 125 - Table 188: RX_MAC MAC Address 2 Register Address
125 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.53 RX_MAC MAC Address 2 Register Table 188: RX_MAC MAC Address 2 Register Address Register Physical Address Access Size RX_MAC MAC Address2 register 0x8C0_6318 4 bytes
Page 126 - Table 191: RX_MAC MAC Address 1 Register Definition; Table 193: RX_MAC MAC Address 0 Register Definition
126 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.54 RX_MAC MAC Address 1 Register 7.5.55 RX_MAC MAC Address 0 Register Table 189: RX_MAC MAC Address 2 Register Definition Field Bits Description Type 15:0 16 most significant bits of the MAC address.These ...
Page 133 - Table 224: MIF Bit-Bang Output Enable Address; Table 225: MIF Frame/Output Register Address; Table 226: MIF Frame/Output Register Definition
133 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.73 MIF Frame/Output Register This 32-bit register serves as an “instruction register” when the MIF is pro-grammed in the frame mode. In order to execute a read/write operationfrom/to a transceiver register, t...
Page 135 - Table 228: MIF Configuration Register Definition
135 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.75 MIF Mask Register This 16-bit register is used to determine which bits in the poll status portionof the MIF status register will cause an interrupt. If a mask bit is cleared to 0,the corresponding bit of t...
Page 136 - Table 230: MIF Mask Register Definition; Table 232: MIF Status Register Definition
136 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Default value: 0xFFFF. 7.5.76 MIF Status Register This 32-bit register is used in conjunction with the poll mode in the MIF. Itcontains two portions: poll data and poll status. The poll data field will alwaysc...
Page 138 - IN
138 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP P IN A SSIGNMENTS 8 8.1 Pin Assignments The Table 235 describes the pin assignments for the 240-pin PQFP FEPSpackage. Table 235: STP2002QFP Pin Assignments Pin No. Signal Name Dual Function (FAS366 Test Mode O...
Page 146 - RRATA; Description of Errata in FEPS Rev 2.2; Symptom; This problem shows up only under the following conditions.; Root Cause
146 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP E RRATA 9 9.1 Description of Errata in FEPS Rev 2.2 The following are some known problems and workarounds for Rev 2.2. of theFEPS. The device driver for the SCSI channel has software workarounds forall of thes...
Page 147 - Work Around; So for a burst size of 16 bytes, the addresses will be
147 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, byte count must become 1 before it can initiate the padding. So byte count notdecrementing all the way to 1 makes the SCSI CE not write the last one byteto the FAS366 (when all of the conditions described above a...
Page 149 - When the D_ADDR register has an odd number, and D_BCNT register is; Don’t stack set ATN command.
149 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, operation. After power-on, the D_ADDR register does not get self initialized.Even software reset to SCSI CE does not initialize the D_ADDR register. Atsuch a time, or in a case where the previous transfer was sta...
Page 152 - A Sun Microsystems Inc. Business
A Sun Microsystems Inc. Business 2550 Garcia Avenue, Mountain View, CA, U.S.A. 94043 (408) 774-8545 Fax (408) 774-8537 © 1996 Sun Microsystems Incorporated All rights reserved. This publication contains information considered proprietary by Sun Microsystems Incorporated. No part of this documentmay ...
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