Sun Microsystems STP2002QFP - Manual

Sun Microsystems STP2002QFP

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Table of Contents:

  • Page 2 – Technology Information; Technology features of FEPS are as follows:; Ethernet core
  • Page 4 – Sun Microelectronics; Figure 1. STP2002QFP Block Diagram
  • Page 5 – Pin Descriptions; The signal pins are grouped by function in the following tables.
  • Page 7 – Table 4: Parallel Port Signals
  • Page 8 – Signal Name
  • Page 9 – SB; US; SBus Capabilities
  • Page 10 – Theory of Operation
  • Page 12 – SCSI C; HANNEL; The following are some of the features of the FAS366 core:
  • Page 14 – ARALLEL; Parallel Port FIFO Operation
  • Page 15 – Bidirectional Parallel Port Interface; Bidirectional signal configuration
  • Page 17 – OCR; ). The function of these bits is defined as; SBus Clock
  • Page 20 – transfer control register; DIR
  • Page 21 – DSW; The; Signal
  • Page 22 – plus 3 to 4 SBus clocks, due to synchronization delays. The width of
  • Page 23 – =1. The configuration of P_ACK as an input will not hinder the
  • Page 24 – has a tolerance of; =1. Reference the data transfer diagram in
  • Page 25 – is used to define the
  • Page 28 – THERNET; Functional Description
  • Page 29 – • Host interface buffer
  • Page 33 – Receive Clock Domain
  • Page 34 – Receive Free Buffer Descriptor Ring; the software, except for diagnostic purposes.
  • Page 36 – Error Conditions and Recovery
  • Page 39 – Programmer’s Reference; Descriptor layout; The pointers to descriptor ring base addresses
  • Page 41 – nearest burst boundary and execute a full DVMA burst read.; Figure 10. Transmit Host Data Structures
  • Page 44 – Figure 11. Receive Host Data Structure; Table 14: TxFIFO Data Structures: Control Word Layout; Field
  • Page 46 – Figure 12. TxFIFO Organization
  • Page 47 – less specified otherwise.; Figure 13. RxFIFO Organization
  • Page 48 – ESTABILITY
  • Page 49 – The following sections describe each of these blocks.
  • Page 56 – Special JTAG Instructions
  • Page 57 – Int_Scan_Enable shifts the clock between the SBus_CLK and the
  • Page 58 – ROGRAMMING; Parallel Port Channel Registers; Table 18: Control/Status Register Address
  • Page 59 – Table 19: Control/Status Register Definition
  • Page 61 – FEPS minor revision number.
  • Page 62 – DMA Address and Next Address Register; A write to the P_ADDR register will invalidate the P_FIFO. A; Table 21: DMA Address and Next Address Register Address; Table 22: DMA Address and Next Address Register Definition
  • Page 63 – ferred before it expires.; Table 23: Byte Count Register Address; Table 24: Byte Count Register Definition
  • Page 64 – Register
  • Page 65 – Table 26: Test Control/Status Register Definition
  • Page 66 – Data setup to data strobe.; This 7-bit quantity is used to define data strobe and ac-; IDLE; Table 28: Hardware Configuration Register Definition
  • Page 67 – Table 29: Operation Configuration Register Address
  • Page 70 – Table 31: Parallel Data Register Address
  • Page 71 – Table 33: Transfer Control Register Address
  • Page 72 – DS; Table 34: Transfer Control Register Definition
  • Page 73 – Table 37: Input Register Address
  • Page 74 – Table 39: Interrupt Control Register Address
  • Page 76 – SCSI Channel Registers; Table 41: Control/Status Register Address; Table 42: Control/Status Register Definition
  • Page 78 – This bit must be asserted at the end of each DMA transfer. In; This bit is set when a DVMA read or write request is pend-
  • Page 79 – Table 44: SCSI Address Register Address; Table 45: SCSI Address Register Definition; Table 46: SCSI Byte Count Register Address; Table 47: SCSI Byte Count Register Definition
  • Page 83 – For the case of SCSI read (data-in phase only) when FAS366 is; Table 50: FAS366 Transfer Counter Low Register (Read Only) Address
  • Page 87 – Table 64: FAS366 Select/Reselect Bus ID Register Address; Table 65: FAS366 Select/Reselect Bus ID Register Definition; Table 66: FAS366 Interrupt Register Address
  • Page 88 – Table 69: FAS366 Select/Reselect Time-Out Register Definition; Table 71: FAS366 Sequence Step Register Definition
  • Page 89 – 2 FAS366 Synchronous Transfer Period Register; Table 72: FAS366 Synchronous Transfer Period Register Address; Table 74: FAS366 FIFO Flags Register Address; Table 75: FAS366 FIFO Flags Register Definition
  • Page 90 – 6 FAS366 Clock Conversion Factor Register; Table 76: FAS366 Synchronous Offset Register Address; Table 77: FAS366 Synchronous Offset Register Definition; Table 78: FAS366 Configuration #1 Register Address; Table 79: FAS366 Configuration #1 Register Definition; Table 80: FAS366 Clock Conversion Factor Register Address
  • Page 91 – Table 81: FAS366 Clock Conversion Factor Register Definition; Table 82: FAS366 Status #2 Register Address; Table 84: FAS366 Test Register Address; Table 85: FAS366 Test Register Definition
  • Page 92 – Table 87: FAS366 Configuration #2 Register Definition; Table 88: FAS366 Configuration #3 Register Address; Table 89: FAS366 Configuration #3 Register Definition
  • Page 93 – Ethernet Channel Registers; To ensure proper operation of the hardware after a software reset; Table 90: FAS366 Recommand Counter Register Address
  • Page 94 – Table 95: Global Configuration Register Definition
  • Page 97 – Table 99: ETX Transmit Pending Command Address; Table 100: ETX Configuration Register Address; Table 98: Global Status Register Definition
  • Page 98 – The transmit descriptor pointer must be initialized to a 2K byte-; Table 101: ETX Configuration Register Definition
  • Page 99 – ETX Transmit Data Buffer Base Address; Table 103: ETX Transmit Descriptor Ring Size Register Address
  • Page 100 – Table 109: ETX Transmit Data Pointer Register Definition; Table 110: ETX TxFIFO Packet Counter Register Address
  • Page 101 – Table 111: ETX TxFIFO Packet Counter Register Definition; Table 112: ETX TxFIFO Write Pointer Register Address; Table 113: ETX TxFIFO Write Pointer Register Definition
  • Page 104 – The TxFIFO should never be accessed using PIOs during nor-; Table 122: ETX TxFIFO Address
  • Page 105 – Table 124: ERX Configuration Register Definition; Table 125: ERX Receive Descriptor Pointer Register Address
  • Page 106 – The receive descriptor pointer must be initialized to a 2K byte-; Table 126: ERX Receive Descriptor Pointer Register Definition; Table 127: ERX Receive Data Buffer Pointer Register Address; Table 128: ERX Receive Data Buffer Pointer Register Definition
  • Page 107 – Table 129: ERX RxFIFO Write Pointer Register Address
  • Page 108 – Table 132: ERX RxFIFO Shadow Write Pointer Register Definition
  • Page 109 – Table 136: ERX RxFIFO Packet Counter Definition
  • Page 110 – The RxFIFO should never be accessed using PIOs during nor-; Table 138: ERX State Machine Register Definition
  • Page 111 – Table 140: XIF Configuration Register Address; Table 141: XIF Configuration Register Definition
  • Page 112 – To ensure proper operation of the hardware, when a loop-back; Table 142: TX_MAC Software Reset Command Address; Table 143: TX_MAC Configuration Register Address
  • Page 113 – Table 144: TX_MAC Configuration Register Definition
  • Page 114 – Table 146: TX_MAC InterPacketGap1 Register Definition
  • Page 120 – Table 174: TX_MAC Excessive Collision Counter Definition; Table 175: TX_MAC Late Collision Counter Address
  • Page 123 – Table 183: RX_MAC Configuration Register Definition
  • Page 124 – Table 185: RX_MAC RxMaxFrameSize Register Definition; Table 187: RX_MAC RxMinFrameSize Register Definition
  • Page 125 – Table 188: RX_MAC MAC Address 2 Register Address
  • Page 126 – Table 191: RX_MAC MAC Address 1 Register Definition; Table 193: RX_MAC MAC Address 0 Register Definition
  • Page 133 – Table 224: MIF Bit-Bang Output Enable Address; Table 225: MIF Frame/Output Register Address; Table 226: MIF Frame/Output Register Definition
  • Page 135 – Table 228: MIF Configuration Register Definition
  • Page 136 – Table 230: MIF Mask Register Definition; Table 232: MIF Status Register Definition
  • Page 138 – IN
  • Page 146 – RRATA; Description of Errata in FEPS Rev 2.2; Symptom; This problem shows up only under the following conditions.; Root Cause
  • Page 147 – Work Around; So for a burst size of 16 bytes, the addresses will be
  • Page 149 – When the D_ADDR register has an odd number, and D_BCNT register is; Don’t stack set ATN command.
  • Page 152 – A Sun Microsystems Inc. Business
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Revision 1.0–April 1996

STP2002QFP

STP2002QFP

Fast Ethernet, Parallel Port, SCSI
(FEPS)

USER’S GUIDE

O

VERVIEW

1

1.1 Introduction

The STP2002QFP FEPS (Fast Ethernet

®

, Parallel, SCSI) is an ASIC that pro-

vides integrated high-performance SCSI, 10/100 Base-T Ethernet, and a Cen-
tronics compatible parallel port.

1.2 Features

FEPS features include the following:

1.3 Overview

FEPS contains four major blocks: SBus Adapter (SBA), SCSI_Channel,
ENET_Channel, and PP_Channel. Each channel uses the Channel Engine In-

• IEEE 1496 SBus master interface with support for 64-bit mode access

• IEEE 1496 SBus slave interface, 32-bit mode only

• 20 MB/s fast and wide single-ended SCSI using a QLogic FAS366 core

• 10/100-Mb/sec Ethernet on the motherboard

• MII (Media Independent Interface) interface to support external transceivers

• DMA2-compatible Centronics parallel port with a maximum throughput of 4

MB/s

• Supports use on an SBus card device

• Provides a path to an FCode PROM for use on SBus boards

• JTAG support for boundary and internal scan testing

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Summary

Page 2 - Technology Information; Technology features of FEPS are as follows:; Ethernet core

2 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP terface (CEI) for slave and DMA transfers with the SBus (via SBA). The SBAprovides buffering and bus conversion between the SBus and the channel en-gine interface. Interrupts from the channel engine go directly ...

Page 4 - Sun Microelectronics; Figure 1. STP2002QFP Block Diagram

4 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 1. STP2002QFP Block Diagram SBus SBA Channel Engine Interface SCSI_IRQ ENET_IRQ PP_IRQ SCSI DVMA ENET DMA PP DMA FAS366 BigMac PP Core SCSI_Channel ENET_Channel PP_Channel SCSI Bus MII Interface Parallel ...

Page 5 - Pin Descriptions; The signal pins are grouped by function in the following tables.

5 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 1.6 Pin Descriptions The signal pins are grouped by function in the following tables. Table 1: SBus Signals Signal Name Type Pin Count Description SB_D[31:0] I/O 32 SBus data SB_A[27:0] I/O 28 SBus address SB_SEL I...

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