SMC Networks ARM720T_LH79520 - Manuals

SMC Networks ARM720T_LH79520 – Manual in PDF format online.

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Manual

Manual SMC Networks ARM720T_LH79520

Summary

Page 2 - RISC Processor Background; History; One instruction per clock cycle execution time; : The RISC design philosophy typically uses a large; Separate Data Memory and Instruction Memory access paths; : Different stages of the pipeline perform simultaneous; “Soft” FPGA Processors; Field Reconfigurable Hardware

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Computer, is a term that is conventionally used to describe a type of microprocessor architecture that employs a small but highly-optimized set of instructions, rather th...

Page 3 - Wishbone Bus Interfaces; Revision B.3 Specification; Knowledge Center

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Improving and Extending Product Life-Cycles Fast time to market is usually synonymous with a weaker feature set – a traditional trade-off. With FPGA-based system designs you can have the best of both worlds. You can get your prod...

Page 4 - RISC Processor; MicroBlaze; MicroBlaze 32-bit RISC Processor; Nios; Nios II 32-bit RISC Processor; CoreMP7; – 32-bit RISC processor targeted to Actel FPGA platforms.

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and peripherals, each of the 32-bit processors supported in Altium Designer has a Wishbone OpenBUS-based FPGA core that 'wraps' around the processor. This enable...

Page 5 - Architectural Overview; Symbol; Control signals from the LH79520's Static Memory Controller (SMC)

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Architectural Overview Symbol Figure 1. Symbols used for the ARM720T_LH79520 in both schematic (left) and OpenBus System (right). As can be seen from the schematic symbol in Figure 1, the ARM720T_LH79520 wrapper that is placed in...

Page 6 - Pin Description; Interrupts

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Pin Description The following pin description is for the processor when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces...

Page 8 - Configuring the Processor; In the Schematic document; Component Properties; In the OpenBus System document

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Name Type Polarity/Bus size Description PER_RESET I Low Reset signal from the LH79520. ARM7_SYS_RESET O Low Reset signal to the LH79520 (internally connected from the RST_I line). PER_CLK I Rise Clock signal from the LH79520 ARM7...

Page 9 - The following memory sizes are available to choose from:; Current Configuration; region of the processor’s; Note; : There are no options to remove MDU or Debug Hardware for the

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Speed-critical (or latency-sensitive) parts of an application should also be placed in this memory space. The following memory sizes are available to choose from: • 1KB (256 x 32-bit Words) • 2KB (512 x 32-bit Words) • 4KB (1K x ...

Page 10 - Division of Memory Space; Defining the Memory Map; Building the Bridge between the Hardware and Software; Place the peripheral or memory

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Memory & I/O Management The ARM720T_LH79520 uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into...

Page 12 - Dedicated System Interconnect Components; CR0150 WB_INTERCON Configurable Wishbone Interconnect; Configure

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The adjacent flow chart shows the process that was followed to build this memory map in a schematic-based FPGA design. This flow chart is only a guide, during the course of development it is likely that you will jump back and for...

Page 13 - Internal Memory

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • cs0 (Bank 0) – 4000_0000h to 43FF_FFFFh • cs1 (Bank 1) – 4400_0000h to 47FF_FFFFh The bank select signals arrive at the processor's wrapper component in the FPGA on the PER_CS bus. • cs2 (Bank 2) – 4800_0000h to 4BFF_FFFFh • cs...

Page 14 - Internal Processor Memory; region of the; External Memory; External Memory Interface Time-out

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The size of the RAM can vary between 1KB and 16MB, dependent on the availability of embedded block RAM in the target FPGA device used. Memory size is configured in the Internal Processor Memory region of the Configure (32-bit Pro...

Page 15 - Connecting Memory and Peripheral Devices to a 32-bit Processor; Data Organization; BIG ENDIAN; ARM720T Technical Reference Manual; Physical Interface to Memory and Peripherals

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor clock signal (CLK_I), an acknowledge signal fails to appear from the addressed slave peripheral device, the wait request to the ARM720T is dropped, the processor times out normally and the current data transfer cycle is forcibly ...

Page 16 - for a byte load/store, the processor will sign-extend from bit 8

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • for an unsigned read, the processor will pad-out the remaining 24 or 16 bits respectively with zeroes • for a byte load/store, the processor will sign-extend from bit 8 • for a half-word load/store, the processor will sign-exte...

Page 17 - Hardware Description; ARM; Clocking; Noncritical

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Hardware Description For detailed information about the hardware and functionality of the ARM720T_LH79520 processor, including internal registers, refer to the following reference guide, available from the ARM website: • ARM720T ...

Page 18 - Wishbone Communications; Writing to a Slave Wishbone Peripheral Device; output. It then asserts its IO_WE_O output to specify a Write cycle; Reading from a Slave Wishbone Peripheral Device; to specify a Read cycle; Writing to a Slave Wishbone Memory Device

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone Communications The following sections detail the standard handshaking that takes place when the processor communicates to a slave peripheral or memory device connected to the relevant Wishbone interface port. Both of the...

Page 19 - Reading from a Slave Wishbone Memory Device; location; Wishbone Timing

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Reading from a Slave Wishbone Memory Device Data is read by the host processor (Wishbone Master) from a Wishbone-compliant memory device or memory controller (Wishbone Slave) in accordance with the standard Wishbone data transfer...

Page 20 - Design using a Schematic only

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Placing an ARM720T_LH79520 in an FPGA design How the ARM720T_LH79520 is placed and wired within an FPGA design depends on the method used to build that design. The main processor-based system can be defined purely on the schemati...

Page 21 - Design Featuring an OpenBus System; An OpenBus System is defined on an OpenBus System Document (

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Design Featuring an OpenBus System Figure 11 illustrates identical use of the ARM720T_LH79520 within a design where the main processor system has been defined as an OpenBus System. Peripherals (and memory) are connected to the pr...

Page 22 - Processor-based FPGA design with the OpenBus System; Facilitating Communications; Devices

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 12. Wiring the OpenBus System-based ARM720T_LH79520 to the physical pins of the FPGA device. For more information on the concepts and workings of the OpenBus System, refer to the article AR0144 Streamlining Processor-based...

Page 23 - AR0130 PC to NanoBoard Communications; Additional 'Soft' Devices in Your Design; view. The Soft Devices chain is determined when; Enabling the Soft Devices JTAG Chain; ) on the top schematic sheet of the design, as shown in Figure 15.; These devices can be found in the FPGA NB2DSK01 Port-Plugin (; Downloading Your Design

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor As the physical ARM720T processor does not reside within an FPGA, communications between the host computer and the ARM720T are carried out through the Hard Devices JTAG chain. This is a departure from the normal way of communicat...

Page 24 - Accessing the Debug Environment; Downloading your design

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • Download of the embedded code targeted to the discrete ARM720T device. Click on the LH79520 device in the Hard Devices chain to access the process flow required to download the embedded software to the processor, as illustrated...

Page 26 - Hard Devices; region of the view. The; Instrument Rack –

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 17. Workspace panels offering code-specific information and controls Figure 18. Workspace panels offering information specific to the parent processor. Full-feature debugging is of course enjoyed at the source code level –...

Page 27 - The; Nexus Debugger; when the cursor is over one of these

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 19. Accessing debug features from the processor's instrument panel The Nexus Debugger button provides access to the associated debug panel (Figure 20), which in turn allows you to interrogate and to a lighter extent contro...

Page 28 - Instruction Set; Revision History

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Instruction Set The ARM7TDMI-S core processor – on which the ARM720T is based – is an implementation of the ARM architecture v4T. For an overview of the ARM instructions available for this processor, refer to the following docume...