Quatech MPAP-100 - Manuals

1 Introduction The Quatech MPAP-100 is a PCMCIA Type II (5 mm) card and is PCMCIA PC Card Standard Specification 2.1 compliant. It provides a single-channel RS-232 synchronouscommunication port. The base address and IRQ are configured through the PCMCIA hardwareand software using utility programs pr...

2 Hardware Installation Hardware installation for the MPAP-100 is a very simple process: 1. Insert the MPAP-100 into a vacant PCMCIA Type II adapter socket. 2. If PCMCIA Card and Socket Services and a Quatech MPAP-100 Client Driver are installed, the MPAP-100 will be configured for use automatically...

3.1 MPAP-100 Client Driver for DOS In order to use the MPAP-100 client driver, the system must be configured with Card and Socket Services software. Card and Socket Services software is not provided with theMPAP-100 but is available from Quatech. 3.1.1 DOS client driver installation The MPAP-100 cli...

S# The PCMCIA socket into which the MPAP-100 must be inserted for thisconfiguration to be used. This value is a decimal number ranging from 0 to 15. Ifthis parameter is not used, the configuration can apply to any socket. B# The base I/O address of the MPAP-100. This number must be a three-digithexa...

3.2 DOS Client Driver examples Example: Attempt to configure an MPAP-100 inserted into any socket with a base address andIRQ automatically assigned by Card Services. DEVICE=C:\MPAP-100\MPAP1CL.SYS Example: Attempt to configure an MPAP-100 inserted into any socket with a base address of300 hex and an...

3.3 MPAP-100 Enabler for DOS For systems that are not using PCMCIA Card and Socket Services software, the MPAP-100 DOS enabler may be used to enable and configure the card. The enabler will operateon any DOS system using an Intel 82365SL (PCIC) or PCIC-compatible PCMCIA socket adapterincluding the C...

If configuration is successful, the enabler will display a message showing the configuration on the screen. If the MPAP-100 is not successfully configured, then theinformation in this section along with the Troubleshooting chapter of this manual should beconsulted to determine the cause of the probl...

3.4 DOS Enabler Examples Example: Configure the MPAP-100 in socket 0 with a base address of 300H and IRQ 5. Software control of SYNCA will be enabled . MPAP1EN.EXE (s0,b300,i5,c) Example: Configure the MPAP-100 in socket 1 with a base address of 300H and IRQ 3 using aconfiguration memory window at s...

4.2 Viewing Resources with Device Manager The following instructions provide step-by-step instructions on viewing resources used by the MPAP-100 in Windows 95/98 using the "Device Manager" utility. 1. Double click the "System" icon inside the Control Panel folder. This opens up the S...

6. If changes to the automatic configuration are necessary for compatibility with existing programs, uncheck the "Use Automatic Settings" box and doubleclick on the ResourceType that needs to be changed. Caution should be used to avoid creating device conflictswith other hardware in the syst...

5 OS/2 Software Installation An OS/2 client driver is provided with the MPAP-100. This client driver works with OS/2's Card and Socket Services to allow operation of the MPAP-100 under OS/2. 5.1 System Requirements OS/2 2.1 or later. OS/2 PCMCIA Card and Socket Services support must be installed. Se...

6 Using the MPAP-100 with Syncdrive Syncdrive is a synchronous communications software driver package designed to aid users of Quatech synchronous communication hardware in the development of their applicationsoftware. Syncdrive is included free of charge with all Quatech MPA-series synchronouscommu...

7 Addressing The MPAP-100 occupies a continuous 16-byte block of I/O addresses. For example, if the base address is set to 300 hex, then the MPAP-100 will occupy address locations 300 hex to30F hex. If the computer in which the MPAP-100 is installed is running PCMCIA Card andSocket Services, the bas...

8 Interrupts The MPAP-100 will operate using the interrupt level (IRQ) assigned by the PCMCIA system. Interrupts can come from the SCC, the external FIFOs or RS-232 test mode. Theinterrupt source is selected by bits 4 and 5 of the Configuration Register (see page 41). When using interrupts with the ...

9 SCC General Information The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPAP-100 provides a single channel for communications,however, portions of the second channel can be utilized to support some special circumstances.The SCC can b...

9.1 Accessing the registers The mode of communication desired is established and monitored through the bit values of the internal read and write registers. The register set of the SCC includes 16 write registersand 9 read registers. These registers only occupy four address locations, which start at ...

9.2 Baud Rate Generator Programming The baud rate generator (hereafter referred to as the BRG) of the SCC consists of a 16-bit down counter, two 8-bit time constant registers, and an output divide-by-two. The time constantfor the BRG is programmed into WR12 (least significant byte) and WR13 (most si...

The MPAP-100 is a single-channel device. Portions of SCC channel B are used to augment channel A. Channel B cannot be used for transmit, but may be used for receive, subjectto certain limitations. 9.4.1 Receive data and clock signals The receive data signals RXDA and RXDB are tied together. The rece...

9.5 SCC Incompatibility Warnings Due to the SCC implementation used by the MPAP-100, there are two minor incompatibilities that the software programmer must avoid. 9.5.1 Register Pointer Bits In a Zilog 85230, the control port register pointer bits can be set in either channel. With the implementati...

10.2.2 Receive FIFO The receive FIFO can service the receiver of either channel A or channel B of the SCC. If RXSRC (bit 1) of the Configuration Register (see page 41) is logic 1, the receive FIFO willservice SCC channel B. If RXSRC is logic 0, the receive FIFO will service SCC channel A. If the FIF...

10.3.1 Using channel A for both transmit and receive This is the mode in which most applications will run. Set RXSRC (bit 1) in the Configuration Register to logic 0. This will configure the MPAP-100 to use W/REQA forreceive DMA and DTR/REQA for transmit DMA. In addition to any other desired SCCconf...

10.4 FIFO status and control Several registers are used to control the FIFOs and monitor their status. These registers are detailed in other chapters of this manual. 10.4.1 Interrupt status Three interrupt statuses, listed in Table 8, can be generated by four events related to FIFO activity. In each...

10.4.2 Resetting the FIFOs The FIFOs are automatically disabled and reset at powerup or when the MPAP-100 is inserted into a PCMCIA socket. The transmit and receive FIFOs can also be independently resetby setting and clearing the appropriate bits in the FIFO Control Register. Resetting a FIFO setsth...

To make the external FIFOs more useful in byte-synchronous modes, the MPAP-100 can watch for a given character to be transferred consecutively a specific number of times from theSCC into the receive FIFO. When this occurs, the RX_PAT bit in the Interrupt Status Register(see page 43) is set. For inst...

10.7 Receive FIFO timeout With asynchronous operational modes, the same problem exists. Namely, how is one to determine when a reception is complete? While the receive pattern detection may be useful here,the MPAP-100 also offers a timeout feature on the external receive FIFO. If the external FIFO i...

11 Communications Register The Communications Register is used to set options pertaining to the clocks. The source and type of clock to be transmitted or received can be specified. External synchronization andRS-232 DTE test modes and can also be controlled with this register. The address of theComm...

receive unformatted serial data, as it allows the SCC receiver to be manuallyplaced into sync under program control. This bit is ignored if bit 6 is set (logic 1). Bit 3: RCKEN --- Receive Clock Source: When set (logic 1), this bit allows the receive clock (RCLK) signal to be generated bythe TRxC pi...

12 Configuration Register The Configuration Register is used to set the interrupt source and enable the interface between the SCC and the external FIFOs. The address of this register is Base+5. Table 10details the bit definitions of the register. 0 RXSRC FIFOEN 0 INTS0 INTS1 0 1 Bit 0 Bit 1 Bit 2 Bi...

13 Interrupt Status Register The Interrupt Status Register is used to determine the cause of an interrupt generated by the MPAP-100. The address of this register is Base+8. Table 11 details the bit definitions of theregister. The interrupt source in the Configuration Register (see page 41) must be s...

14 FIFO Status Register The FIFO Status Register is used to return current status information about the external FIFOs. The address of this read-only register is Base+9. Table 12 details the bit definitions ofthe register. This register can be ignored if the external FIFOs are not being used. TXE TX...

15 FIFO Control Register The FIFO Control Register is used to control the external data FIFOs. The address of this register is Base+A (hex). Table 13 details the bit definitions of the register. This register can beignored if the external FIFOs are not being used. TX_RESET 0 0 0 RX_RESET EN_TO EN_PA...

16 Receive Pattern Character Register The Receive Pattern Character Register is used to set the character value to be used in receive pattern detection. The address of this register is Base+B (hex). This register can beignored if the external FIFOs are not being used. character value (0-255) Bit 0 B...

17 Receive Pattern Count Register The Receive Pattern Count Register is used to set the counter value to be used in receive pattern detection. The address of this register is Base+C (hex). This register can be ignored ifthe external FIFOs are not being used. counter value (0-255) Bit 0 Bit 1 Bit 2 B...

18 Receive FIFO Timeout Register The Receive FIFO Timeout Register is used to control the operation of the external receive FIFO timeout feature. The address of this register is Base+D (hex). This register can beignored if the external FIFOs are not being used. See page 38 for details on the receive...

19 External Connections The MPAP-100 is configured as a Data Terminal Equipment (DTE) device, meeting the RS-232-D standard using a DB-25 male connector. There is no DCE version available. The control signals the DTE can generate are Request To Send (RTS) and Data Terminal Ready (DTR). It can receiv...

20 DTE Interface Signals CIRCUIT AB - SIGNAL GROUND CONNECTOR NOTATION: DGND DIRECTION: Not applicable This conductor directly connects the DTE circuit ground to the DCE circuit ground. CIRCUIT BA - TRANSMITTED DATA CONNECTOR NOTATION: TXD DIRECTION: To DCE This signal transfers the data generated b...

21 Specifications Bus interface: PCMCIA PC Card Standard 2.1 Physical Dimensions: Type II (5 mm) PCMCIA card Controller: 85230-compatible 16-MHz SerialCommunications Controller (SCC) DTE Interface: Male D-25 connector Transmit drivers: RS-232 compatible,600 kbps typical maximum data rate Receive buf...

22 Software Troubleshooting This appendix discusses how to resolve some common problems sometimes encountered when using the MPAP-100 configuration software. 22.1 DOS Client Driver 22.1.1 Generic "SuperClient" Drivers Many Card and Socket Services packages include a generic client driver (or...

22.2.1 With Card and Socket Services The enabler should NOT be used if any Card and Socket Services are present on the system. If Card and Socket Services is installed, the enabler may interfere with its operation andwith the device(s) it controls. The client driver should be used to configure the M...