IBM PD78081(A) - Manuals

Major Revision in This Edition Page Description Throughout The following products have been already developed µ PD78081CU- ××× , 78081GB- ××× -3B4, 78082CU- ××× , 78082GB- ××× -3B4, 78P083CU, 78P083DU, 78P083GB-3B4 The following products have been added µ PD78081GB- ××× -3BS-MTX, 78082GB- ××× -3BS-M...

PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD78083 subseries and design and develop its application systems and programs. Caution In the µ PD78083 Subseries, the µ PD78P083DU is not designed to maintain the reliability required for ...

To know application examples of the functions provided in the µ PD78083 Subseries: → Refer to Application Note separately provided. Legend Data representation weight : High digits on the left and low digits on the right Active low representations : ××× (line over the pin and signal names) Note : Des...

Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for µ PD78054 subseries Document name Document No. Japanese English µ PD78083 Subseries User’s Manual U12176J This Manual µ ...

– i – CONTENTS CHAPTER 1 OUTLINE ..................................................................................................................... 1 1.1 Features ............................................................................................................................. 1 1.2 Ap...

– ii – 3.2.3 Special Function Register (SFR) ......................................................................................... 37 3.3 Instruction Address Addressing ..................................................................................... 40 3.3.1 Relative Addressing ...............

– iii – 6.4 8-Bit Timer/Event Counters 5 and 6 Operations ............................................................ 90 6.4.1 Interval timer operations ...................................................................................................... 90 6.4.2 External event counter operation ....

– iv – 12.4 Interrupt Servicing Operations ........................................................................................ 181 12.4.1 Non-maskable interrupt request acknowledge operation .................................................... 181 12.4.2 Maskable interrupt request acknowledge o...

– vi – FIGURE (1/4) Fig. No. Title Page 2-1 Pin Input/Output Circuit of List ............................................................................................ 23 3-1 Memory Map ( µ PD78081) .................................................................................................. ...

– vii – FIGURE (2/4) Fig. No. Title Page 6-10 8-Bit Timer Mode Control Register Setting for External Event Counter Operation ............. 93 6-11 External Event Counter Operation Timings (with Rising Edge Specification) .................... 93 6-12 8-Bit Timer Mode Control Register Settings for Squ...

– viii – FIGURE (3/4) Fig. No. Title Page 11-6 Baud Rate Generator Control Register Format (2/2) ......................................................... 145 11-7 Asynchronous Serial Interface Transmit/Receive Data Format .......................................... 157 11-8 Asynchronous Serial Inter...

– ix – FIGURE (4/4) Fig. No. Title Page 15-6 PROM Read Timing ........................................................................................................... 213 A-1 Development Tool Configuration ........................................................................................ 23...

– xi – TABLE (2/2) Table. No. Title Page 12-1 Interrupt Source List ........................................................................................................... 172 12-2 Various Flags Corresponding to Interrupt Request Sources .............................................. 175 12-3 Ti...

1 CHAPTER 1 OUTLINE CHAPTER 1 OUTLINE 1.1 Features On-chip ROM and RAM Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS). Instruction execution time changeable from high speed (0.4 µ s: In main system clock 5.0 MHz op...

2 CHAPTER 1 OUTLINE 1.2 Applications µ PD78081, 78082, 78P083: Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan heaters, dashboards, etc. µ PD78081(A), 78082(A), 78P083(A), 78081(A2): Automobile electrical control devices, gas detector cutoff devices, various sa...

3 CHAPTER 1 OUTLINE 1.4 Quality Grade Part number Package Quality grade µ PD78081CU- ××× 42-pin plastic shrink DIP (600 mil) Standard µ PD78081GB- ××× -3B4 44-pin plastic QFP (10 × 10 mm) Standard µ PD78081GB- ××× -3BS-MTX 44-pin plastic QFP (10 × 10 mm) Standard µ PD78082CU- ××× 42-pin plastic shri...

4 CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) (1) Normal operating mode 42-pin plastic shrink DIP (600 mil) µ PD78081CU- ××× , 78082CU- ××× , 78P083CU, 78P083CU(A) 42-pin ceramic shrink DIP (with window) (600 mil) µ PD78P083DU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 V SS P54 P53...

5 CHAPTER 1 OUTLINE • 44-pin plastic QFP (10 × 10 mm) µ PD78081GB- ××× -3B4, 78081GB- ××× -3BS-MTX µ PD78082GB- ××× -3B4, 78082GB- ××× -3BS-MTX µ PD78P083GB-3B4, 78P083GB-3BS-MTX µ PD78081GB(A)- ××× -3B4, 78082GB(A)- ××× -3B4 µ PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX Note µ PD78P081GB(A2)- ××× -3B4 N...

6 CHAPTER 1 OUTLINE Pin Identifications ANI0 to ANI7 : Analog Input P100, P101 : Port 10 ASCK : Asynchronous Serial Clock PCL : Programmable Clock AV DD : Analog Power Supply RESET : Reset AV REF : Analog Reference Voltage RxD : Receive Data AV SS : Analog Ground SCK2 : Serial Clock BUZ : Buzzer Clo...

7 CHAPTER 1 OUTLINE (2) PROM programming mode • 42-pin plastic shrink DIP (600 mil) µ PD78P083CU, 78P083CU(A) • 42-pin ceramic shrink DIP (with window) (600 mil) µ PD78P083DU Cautions 1. (L) : Individually connect to V SS via a pull-down resistor. 2. V SS : Connect to the ground. 3. RESET : Set to t...

8 CHAPTER 1 OUTLINE Note Under development Cautions 1. (L) : Connect individually to V SS via a pull-down resistor. 2. V SS : Connect to the ground. 3. RESET : Set to the low level. 4. Open : Do not connect anything. A0 to A14 : Address Bus RESET : Reset CE : Chip Enable V DD : Power Supply D0 to D7...

10 CHAPTER 1 OUTLINE The following table shows the differences among subseries functions. Function ROM Timer 8-bit 10-bit 8-bit Serial interface I/O External Subseries name capacity 8-bit 16-bit Watch WDT A/D A/D D/A expansion Control µ PD78075B 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART:...

11 CHAPTER 1 OUTLINE 1.7 Block Diagram Remarks 1. The internal ROM and high-speed RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P083. P100/TI5/TO5 P101/TI6/TO6 SI2/R X D/P70 SO2/T X D/P71 SCK2/ASCK/P72 ANI0/P10- ANI7/P17 AV DD AV SS AV REF INTP1/P01...

12 CHAPTER 1 OUTLINE 1.8 Outline of Function Part Number µ PD78081 µ PD78082 µ PD78083 Item Internal memory ROM Mask ROM PROM 8 Kbytes 16 Kbytes 24 Kbytes Note High-speed RAM 256 bytes 384 bytes 512 bytes Note Memory space 64 Kbytes General register 8 bits × 32 registers (8 bits × 8 registers × 4 ba...

13 CHAPTER 1 OUTLINE 1.9 Differences between the µ PD78081, 78082 and 78P083, the µ PD78081(A), 78082(A) and 78P083(A), and the µ PD78081(A2) Table 1-1 Differences between the µ PD78081, 78082 and 78P083, the µ PD78081(A), 78082(A) and 78P083(A), and the µ PD78081(A2) Part Number µ PD78081 µ PD78081...

15 CHAPTER 2 PIN FUNCTION CHAPTER 2 PIN FUNCTION 2.1 Pin Function List 2.1.1 Normal operating mode pins (1) Port pins Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode. The on-chip pull-up resistor is automatically disabled. Pin Na...

17 CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input. The following operating modes can be specified bit-wise. (1) Port mode P00 functions a...

19 CHAPTER 2 PIN FUNCTION 2.2.5 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise. (1) Port mode Port 7 funct...

21 CHAPTER 2 PIN FUNCTION 2.2.15 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µ PD78083 Subseries at delivery. Connect it directly to the V SS with the shortest possible wire in the normal operating mode. When a voltage difference is prod...

25 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces Figures 3-1 to 3-3 shows memory maps. Figure 3-1. Memory Map ( µ PD78081) Data memory space General Registers 32 × 8 bits Internal ROM 8192 × 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Are...

28 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory is mask ROM with a 8192 × 8-bit configuration in the µ PD78081, and a 16384 × 8-bit configuration in the µ PD78082, and PROM with a 24576 × 8-bit configuration in the µ PD78P083. The internal program memory...

29 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space The internal high speed RAM configuration is 256 × 8-bit in the µ PD78081, 384 × 8-bit in the µ PD78082 and 512 × 8-bit in the µ PD8P083. In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are a...

33 CHAPTER 3 CPU ARCHITECTURE 7 0 IE Z RBS1 AC RBS0 0 ISP CY PC 15 0 3.2 Processor Registers The µ PD78083 subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consi...

34 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgme...

35 CHAPTER 3 CPU ARCHITECTURE RETI and RETB Instruction PSW PC15-PC8 PC15-PC8 PC7-PC0 Register Pair Lower SP SP + 2 SP Register Pair Upper RET Instruction POP rp Instruction SP + 1 PC7-PC0 SP SP + 2 SP SP + 1 SP + 2 SP SP + 1 SP SP + 3 Interrupt andBRK Instruction PSW PC15-PC8 PC15-PC8 PC7-PC0 Regis...

36 CHAPTER 3 CPU ARCHITECTURE BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEE0H HL DE BC AX H 15 0 7 0 L D E B C A X 16-Bit Processing 8-Bit Processing FEF0H FEE8H BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R2 R1 R0 16-Bit Processing 8-Bit Processing FEF0H FEE8H 3.2.2 ...

39 CHAPTER 3 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FFEAH Priority order specify flag register 1L PR1L R/W √ √ — FFH FFECH External interrupt mode register 0 INTM0 — √ — 00H FFEDH External interrupt mode register 1 INTM1 — √ — FFF0H Memory size switching...

40 CHAPTER 3 CPU ARCHITECTURE 15 0 PC + 15 0 8 7 6 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start addressof the instructionafter the BR instruction. ... 3.3 Instruction Address Addressing An instruction address is determined by program cou...

41 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr...

43 CHAPTER 3 CPU ARCHITECTURE 7 0 rp 0 7 A X 15 0 PC 8 7 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustrat...

44 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and ...

45 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing...

46 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !add...

48 CHAPTER 3 CPU ARCHITECTURE 15 0 Short Direct Memory Effective Address 1 1 1 1 1 1 1 8 7 0 7 OP code saddr-offset α [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 ...

49 CHAPTER 3 CPU ARCHITECTURE 15 0 SFR Effective Address 1 1 1 1 1 1 1 8 7 0 7 OP code sfr-offset 1 3.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied ...

51 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [ F u n c t i o n ] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the...

53 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD78083 Subseries units incorporate an input port and thirty-two input/output ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied con...

55 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration A port consists of the following hardware: Table 4-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 1, 3, 5, 7, 10) Pull-up resistor option register (PUOH, PUOL) Port Total: 33 ports (1 input, 32 inputs/outpu...

56 CHAPTER 4 PORT FUNCTIONS Figure 4-2. P00 Block Diagram Figure 4-3. P01 to P03 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal P00 RD Internal bus P-ch WR PM WR PORT RD WR PUO V DD P01/INTP1 P03/INTP3 Selector PUO0 Outpu...

57 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units wi...

63 CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10) • Pull-up resistor option register (PUOH, PUOL) (1) Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10) These registers are us...

66 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has b...

67 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are...

69 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is available. Main system clock oscillator This circuit oscillates at frequenc...

70 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Main SystemClock Oscillator X2 X1 STOP PCC2 PCC1 Internal Bus Standby Control Circuit 2 f XX 2 2 f XX 2 3 f XX 2 4 f XX Prescaler Clock to PeripheralHardware Prescaler Oscillation ModeSelection Register f XX CPU Clock (f CPU )...

71 CHAPTER 5 CLOCK GENERATOR 5.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock s...

72 CHAPTER 5 CLOCK GENERATOR Write to OSMS (MCS 0) f XX Max. 2/f X Operating at f XX = f X /2 (MCS = 0) Operating at f XX = f X /2 (MCS = 0) MCS Main System Clock Scaler Control 0 1 Scaler used Scaler not used 0 0 0 0 OSMS FFF2H 7 6 5 4 3 2 Symbol 1 0 MCS 0 0 Address After Reset R/W 00H W 0 (2) Osci...

73 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillato...

74 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Oscillator with Bad Connection (1/2) (a) Wiring of connection circuits (b) Signal conductors intersect is too long with each other (c) Changing high current is too near a (d) Current flows through the grounding line signal conductor of the ocsilla...

75 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Oscillator with Bad Connection (2/2) (c) Signals are fetched 5.4.2 Scaler The scaler divides the main system clock oscillator output (f XX ) and generates various clocks. IC X2 X1

76 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f XX • CPU clock f CPU • Clock to peripheral hardware The following clock generator func...

77 CHAPTER 5 CLOCK GENERATOR 5.6 Changing CPU Clock Settings 5.6.1 Time required for CPU clock switchover The CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing t...

78 CHAPTER 5 CLOCK GENERATOR 5.6.2 CPU clock switching procedure This section describes CPU clock switching procedure. Figure 5-7. CPU Clock Switching (1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high ...

79 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 The timers incorporated into the µ PD78083 subseries are outlined below. (1) 8-bit timers/event counters 5 and 6 (TM5 and TM6) This can be used to serve as an interval timer, an external event counter, squar...

80 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.1 8-Bit Timer/Event Counters 5 and 6 Functions The 8-bit timer/event counters 5 and 6 (TM5 and TM6) have the following functions. • Interval timer • External event counter • Square-wave output • PWM output (1) 8-bit interval timer Interrupt requests ...

85 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-3. Timer Clock Select Register 5 Format Note The timer output (PWM output) cannot be used in cases where the clock is being input from an external source. Caution When rewriting TCL5 to other data, stop the timer operation beforehand. Remarks ...

86 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) Timer clock select register 6 (TCL6) This register sets count clocks of 8-bit timer register 6. TCL6 is set with an 8-bit memory manipulation instruction. RESET input sets TCL6 to 00H. Figure 6-4. Timer Clock Select Register 6 Format Note When cloc...

87 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) 8-bit timer mode control register 5 (TMC5) This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register 5 and controls operation of 8-bit timer/event counter 5 output control circuit. It sets R-S ...

88 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (4) 8-bit timer mode control register 6 (TMC6) This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register 6 and controls operation of 8-bit timer/event counter 6 output control circuit. It sets R-S ...

89 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (5) Port mode register 10 (PM10) This register sets port 10 input/output in 1-bit units. When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101, and output latches of P100 and P101 to 0. PM10 is set with a 1-bit or 8-bit m...

90 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4 8-Bit Timer/Event Counters 5 and 6 Operations 6.4.1 Interval timer operations By setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-8, it can be operated as an interval timer. The 8-bit timer/event counters ...

91 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Count Clock TMn Count Value INTTMn TCEn CRn0 TOn Interval Time Interval Time Interval Time Interrupt Request Acknowledge Interrupt Request Acknowledge N N N N Clear Count start Clear t 00 01 N 00 01 N 00 01 N Figure 6-9. Interval Timer Operation Timing...

93 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5/PI00/TO5 and TI6/ P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6). TM5 and TM6 are incremented each time ...

94 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.3 Square-wave output This makes the value set in advance in the 8-bit conveyor register 50, 60 (CR50, CR60) to be the interval. It operates as a square wave output at the desired frequency. The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reve...

95 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 6-6. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 — 1/f X — 2 8 × 1/f X — 1/f X (200 ns) (51.2 µ s) (200 ns) 1/f X 2 × 1/f X 2 8 × ...

100 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6 (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start. This is because 8-bit timer registers 5 and 6...

103 CHAPTER 7 WATCHDOG TIMER CHAPTER 7 WATCHDOG TIMER 7.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and ...

104 CHAPTER 7 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 7-2. Interval Times Interval Time MCS = 1 CS = 0 2 11 × 1/f XX 2 11 × 1/f X (410 µ s) 2 12 × 1/f X (819 µ s) 2 12 × 1/f XX 2 12 × 1/f X (819 µ s) 2 13 × 1/f X (1.64 ms) 2 13 × 1/...

105 CHAPTER 7 WATCHDOG TIMER Prescaler f XX 2 4 f XX 2 5 f XX 2 6 f XX 2 7 f XX 2 8 f XX 2 9 Selector Watchdog Timer Mode Register Internal Bus Internal Bus TCL22 TCL21 TCL20 f XX /2 3 f XX 2 11 Timer Clock Select Register 2 3 WDTM4 WDTM3 8-Bit Counter TMMK4 RUN TMIF4 INTWDTMaskable InterruptRequest...

106 CHAPTER 7 WATCHDOG TIMER 7.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer c...

107 CHAPTER 7 WATCHDOG TIMER Figure 7-2. Timer Clock Select Register 2 Format TCL27 7 TCL26 6 TCL25 0 4 0 3 2 1 0 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R / W R / W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 f XX / 2 3 f XX / 2 4 f XX / 2 5 f XX / 2 6 f ...

108 CHAPTER 7 WATCHDOG TIMER RUM 7 0 6 0 WDTM4 4 WDTM3 3 2 1 0 FFF9H Address WDTM Symbol 0 0 0 5 00H After Reset R / W R / W RUN 0 1 Watchdog Timer Operation Mode Selection Note 3 Count stop Counter is cleared and counting starts. WDTM3 × 0 1 Watchdog Timer Operation ModeSelection Note 1 Interval ti...

109 CHAPTER 7 WATCHDOG TIMER 7.4 Watchdog Timer Operations 7.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detecti...

110 CHAPTER 7 WATCHDOG TIMER 7.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time)...

111 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT CLOE PCL/P35 Pin Output * * CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI...

112 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 8-1. Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figu...

113 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets P...

114 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT PM37 7 PM36 6 PM35 PM34 4 PM33 3 2 1 0 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R / W R / W PM3n 0 1 P3n Pin Input/Output Mode Selection (n=0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) (2) Port mode register 3 (PM3)...

115 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT Internal Bus f XX /2 9 f XX /2 10 f XX /2 11 TCL27 TCL26 TCL25 3 PM36 Selector Timer Clock Select Register 2 Port Mode Register 3 BUZ / P36 P36 Output Latch CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT 9.1 Buzzer Output Control Circuit Functions The buzzer outp...

116 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT 9.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register set...

117 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT Figure 9-2. Timer Clock Select Register 2 Format TCL27 7 TCL26 6 TCL25 0 4 0 3 2 1 0 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R / W R / W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 f XX / 2 3 f XX / 2 4 f XX / 2 ...

119 CHAPTER 10 A/D CONVERTER CHAPTER 10 A/D CONVERTER 10.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result ...

120 CHAPTER 10 A/D CONVERTER Figure 10-1. A/D Converter Block Diagram Notes 1. Selector to select the number of channels to be used for analog input. 2. Selector to select the channel for A/D conversion. 3. External interrupt mode register 1 (INTM1) bits 0 and 1. ANI0/P10ANI1/P11ANI2/P12ANI3/P13ANI4...

122 CHAPTER 10 A/D CONVERTER 10.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) • External interrupt mode register 1 (INTM1) (1) A/D converter mode registe...

123 CHAPTER 10 A/D CONVERTER Figure 10-2. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 µ s. Cautions 1. The following sequence is recommended for power consumption reduction of...

124 CHAPTER 10 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit me...

125 CHAPTER 10 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 10-4. External Interrupt Mode Register 1 Format 0 7 0 6 0 0 4 0 3 2 1 0 FFEDH Add...

126 CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D conv...

127 CHAPTER 10 A/D CONVERTER SAR ADCR INTAD A/ D ConverterOperation Sampling Time Sampling A / D Conversion Conversion Time Undefined 80H C0H or 40H ConversionResult ConversionResult Figure 10-5. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of A...

128 CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. ADCR = ...

129 CHAPTER 10 A/D CONVERTER ADM Rewrite CS=1, TRG=1 StandbyState ANIn INTP3 A /D Conversion ADCR INTAD ANIn ANIn ANIn ANIm ANIm ANIn ANIn StandbyState StandbyState ADM Rewrite CS=1, TRG=1 ANIm ANIm ANIm 10.4.3 A/D converter operating mode Using the A/D converter input select register (ADIS) and the...

130 CHAPTER 10 A/D CONVERTER Conversion Start CS=1, TRG=0 A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIn ANIm ANIm ANIn ANIn ADM Rewrite CS=1, TRG=0 ADM Rewrite CS=0, TRG=0 Conversion suspendedConversion results arenot stored Stop (2) A/D conversion operation in software start When bit 6 (TRG) and b...

131 CHAPTER 10 A/D CONVERTER 10.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode. As a current still flows in the AV REF pin at this time, this current must be cut in order to minimize the ...

132 CHAPTER 10 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV REF and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected ...

133 CHAPTER 10 A/D CONVERTER A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADM Rewrite (Start of ANIn Conversion) ADM Rewrite (Start of ANIm Conversion) ADIF is set but ANImconversion has not ended (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleare...

135 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This ...

136 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 11-1. Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register (TXS) Receive shift register (RXS) Receive b...

137 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Internal Bus Asynchronous Serial Interface Mode Register AsynchronousSerial InterfaceStatus Register Receive Buffer Register (RXB/SIO2) Direction Control Circuit Receive Shift Register (RXS) Reception Control Circuit RxD/SI2/ P70 TxD/SO2/ P71 INTSR/INTCSI2 C...

138 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Counter Selector Selector Decoder 1/2 Selector Transmit Clock 1/2 Selector Receive Clock Match Match MDL0-MDL3 5-Bit Counter RXE Start Bit Detection S...

139 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writi...

140 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status...

141 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 6 5 4 3 2 1 0 7 Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock Selection in Asynchronous Serial InterfaceMode Input clock from off-chip to ASCK pin Dedicated baud rate generator output Note ISRM 0 1 Control of ...

142 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Table 11-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode (2) 3-wire Serial I/O Mode (3) Asynchronous Serial Interface Mode Notes 1. Can be used freely as port function. 2. Can be used as P70 (CMOS input/output) when only transmi...

143 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 PE 6 5 4 3 2 1 0 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated Note 1 (When next receive operation is completed beforedata from receive buffer register is rea...

144 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f SCK /16 f SCK /17 f SCK /18 f SCK /19 f SCK /20 f SCK /21 f SCK /2...

146 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...

147 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with ...

148 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 11.4.1 Operation stop mode In the operation stop mode, serial trans...

149 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 SL 6 5 4 3 2 1 0 7 Symbol ASIM TXE RXE PS1 PS0 CL ISRM SCK FF70H 00H R/W Address After Reset R/W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit oper...

150 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 CSCK 0 1 Clock Selection in 3-wire Serial I/O Mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output CSIM22 0 1 First Bit Specification MSB LSB CSIE2 0 1 Operation Control in ...

152 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 PE 6 5 4 3 2 1 0 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated Note 1 (When next receive operation is completed beforedata from receive buffer register is rea...

153 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 f SCK /16 f SCK /17 f SCK /18 f SCK /19 f SCK /20 f SCK /21 f SCK /22 f SCK ...

155 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...

157 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 11-7. Figure 11-7. Asynchronous Serial Interface Transmit/Receive Data Format 1 Data frame is configured from the following bits. • Start bits ...................

158 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) erro...

160 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 D1 D2 D6 D7 Parity D0 RxD (Input) INTSR STOP START (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is p...

161 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. When a data reception results error flag is set in the asynchronous serial interface register (ASIS), a reception error interrupt ...

162 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) In cases where bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) has been cleared and a transmit operation has been terminated during transmission, be sure to set 1 in TXE after setting FFH in the transmit shift...

168 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 SI2 SCK2 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SRIF Transfer Start at the Falling Edge of SCK2 End of Transfer (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed i...

169 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Figure 11-13. Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writi...

171 CHAPTER 12 INTERRUPT FUNCTION CHAPTER 12 INTERRUPT FUNCTION 12.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt prio...

172 CHAPTER 12 INTERRUPT FUNCTION 12.2 Interrupt Sources and Configuration There are a total of 13 interrupts, combining non-maskable interrupts, maskable interrupts and software interrupts (see Table 12-1). Table 12-1. Interrupt Source List Interrupt Source Name Trigger Non- — INTWDT Watchdog timer...

175 CHAPTER 12 INTERRUPT FUNCTION 12.3 Interrupt Function Control Registers The following five types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L...

176 CHAPTER 12 INTERRUPT FUNCTION Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0. 2. Set 0 to the bits 1, 5 to 7 of IF0L and bits 0, 1, 5 to 7 of IF0H and IF1L. (1) Interrupt req...

177 CHAPTER 12 INTERRUPT FUNCTION Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value becomes undefined. 2. Because port 0 has a dual function as the external interrupt request input, when the output level is changed by specifying the output mode of th...

178 CHAPTER 12 INTERRUPT FUNCTION Cautions 1. If a watchdog timer is used in watchdog timer mode 1, set TMPR4 flag to 1. 2. Set 1 to the bits 1, 5 to 7 of PR0L and bits 0, 1, 5 to 7 of PR0H and PR1L. (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set ...

179 CHAPTER 12 INTERRUPT FUNCTION (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP1 to INTP3. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 12-5. External Interrupt Mode Register 0 For...

180 CHAPTER 12 INTERRUPT FUNCTION (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing ...

181 CHAPTER 12 INTERRUPT FUNCTION 12.4 Interrupt Servicing Operations 12.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control...

182 CHAPTER 12 INTERRUPT FUNCTION WDTM4=1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3=0 (with non-maskable interrupt selected)? Interrupt request generation WDT interrupt servicing? Interrupt control register unaccessed? Interrupt service start Interrupt request held pending Reset pr...

183 CHAPTER 12 INTERRUPT FUNCTION Figure 12-10. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) If two non-maskable interrupt requests are generated during non-maskable interru...

184 CHAPTER 12 INTERRUPT FUNCTION 12.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt ena...

185 CHAPTER 12 INTERRUPT FUNCTION Figure 12-11. Interrupt Request Acknowledge Processing Algorithm Start × × IF=1? × × MK=0? × × PR=0? Any Simultaneously generated ×× PR=0 interrupt requests? Any Simultaneously generated high-priority interrupt requests? IE=1? ISP=1? Vectored interruptservicing Inte...

187 CHAPTER 12 INTERRUPT FUNCTION 12.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt request is acknowledged, the contents are saved to the stack in the orde...

189 CHAPTER 12 INTERRUPT FUNCTION Main Processing INTxxServicing INTyyServicing INTxx(PR=0) 1 InstructionExecution IE=0 INTyy(PR=1) EI IE=0 EI RETI RETI Main Processing EI INTxx(PR=1) INTyy(PR=0) IE=0 EI RETI INTxxServicing INTzz(PR=0) IE=0 EI RETI INTyyServicing IE=0 RETI INTzzServicing Figure 12-1...

190 CHAPTER 12 INTERRUPT FUNCTION Main Processing INTxxServicing INTyyServicing INTxx(PR=0) 1 InstructionExecution IE=0 INTyy(PR=0) IE=0 RETI RETI EI Figure 12-14 Multiple Interrupt Example (2/2) Example 3. Example of when a multiple interrupt is not generated because interrupts are not enabled. Bec...

192 CHAPTER 12 INTERRUPT FUNCTION The interrupt request reserve timing is shown in Figure 12-15. Figure 12-15. Interrupt Request Hold Remarks 1. Instruction N: Instruction that holds interrupts requests 2. Instruction M: Instructions other than instruction N 3. The operation of ×× IF (interrupt requ...

193 CHAPTER 13 STANDBY FUNCTION CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode...

194 CHAPTER 13 STANDBY FUNCTION Address FFFAH 04H After Reset R/W R/W 0 0 0 0 1 Selection of Oscillation StabilizationTime when STOP Mode is Released 2 12 /f xx 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx OSTS2 7 0 Symbol OSTS 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 0 0 1 1 0 Other than above OSTS1 ...

195 CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operations 13.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 13-1. HALT Mode Operating Status Item HALT Mode Operating S...

196 CHAPTER 13 STANDBY FUNCTION HALTInstruction Wait StandbyRelease Signal OperatingMode Clock HALT Mode Wait Oscillation Operating Mode (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request...

197 CHAPTER 13 STANDBY FUNCTION (c) Clear upon RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 13-3. HALT Mode Release by RESET Input Remarks 1. f X : main system clock oscillation frequency 2. Values in parentheses when ...

198 CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V DD via a pull-up resistor to minimize the leakage current at the crystal osci...

199 CHAPTER 13 STANDBY FUNCTION STOPInstruction Wait (Time set by OSTS) Oscillation Stabilization Wait Status OperatingMode Oscillation OperationgMode STOP Mode Oscillation Stop Oscillation StandbyRelease Signal Clock (2) STOP mode release The STOP mode can be cleared with the following two types of...

200 CHAPTER 13 STANDBY FUNCTION RESETSignal OperatingMode Clock ResetPeriod STOP Mode Oscillation Stop Oscillation StabilizationWait Status OperatingMode Oscillation Wait (2 17 /f x : 26.2 ms) STOPInstruction Oscillation (b) Release by RESET input The STOP mode is cleared and after the lapse of osci...

201 CHAPTER 14 RESET FUNCTION RESET Count Clock Reset Control Circuit Watchdog Timer Stop Over-flow ResetSignal InterruptFunction CHAPTER 14 RESET FUNCTION 14.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Interna...

202 CHAPTER 14 RESET FUNCTION RESET InternalReset Signal Port Pin Delay Delay Hi-Z X1 Normal Operation Reset Period(Oscillation Stop) OscillationStabilizationTime Wait Normal Operation(Reset Processing) Stop Status(Oscillation Stop) STOP Instruction Execution RESET InternalReset Signal Port Pin Dela...

204 CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Status after Reset (2/2) Hardware Status after Reset Interrupt Request flag register (IF0L, IF0H, IF1L) 00H Mask flag register (MK0L, MK0H, MK1L) FFH Priority specify flag register (PR0L, PR0H, PR1L) FFH External interrupt mode register (INTM0, INTM...

206 CHAPTER 15 µ PD78P083 Caution If using mask ROM versions, do not specify any values in the IMS other than when resetting. The IMS settings to give the same memory map as mask ROM versions are shown in Table 15-2. Table 15-2. Examples of Memory Size Switching Register Settings Relevant Mask ROM V...

207 CHAPTER 15 µ PD78P083 RESET V PP V DD CE OE PGM D0-D7 15.2 PROM Programming The µ PD78P083 incorporate a 24-Kbyte PROM as program memory, respectively. To write a program into the µ PD78P083 PROM, make the device enter the PROM programming mode by setting the levels of the V PP and RESET pins as...

209 CHAPTER 15 µ PD78P083 15.2.2 PROM write procedure Figure 15-2. Page Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.1-ms program pulse Verify 4 Bytes Pass Address = N?...

211 CHAPTER 15 µ PD78P083 Figure 15-4. Byte Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Verify Address = N? V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified? End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X =...

212 CHAPTER 15 µ PD78P083 Figure 15-5. Byte Program Mode Timing Cautions 1. Be sure to apply V DD before applying V PP , and remove it after removing V PP . 2. V PP must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is...

213 CHAPTER 15 µ PD78P083 15.2.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin. Unused pins are handled as shown in paragraph, (2) “PROM programming mode” in section 1.5...

214 CHAPTER 15 µ PD78P083 15.3 Erasure Procedure ( µ PD78P083DU Only) With the µ PD78P083DU, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the window to light with a wavelength of appr...

215 CHAPTER 16 INSTRUCTION SET CHAPTER 16 INSTRUCTION SET This chapter describes each instruction set of the µ PD78083 subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 series USER’S MANUAL—Instruction (IEU-1372).”

216 CHAPTER 16 INSTRUCTION SET 16.1 Legends Used in Operation List 16.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications ...

217 CHAPTER 16 INSTRUCTION SET 16.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register L : L register AX : AX register pair; 16-bit accumulator BC : BC register pair DE : DE register pair HL ...

218 CHAPTER 16 INSTRUCTION SET 16.2 Operation List Clock Flag Note 1 Note 2 Z AC CY r, #byte 2 4 – r ← byte saddr, #byte 3 6 7 (saddr) ← byte sfr, #byte 3 – 7 sfr ← byte A, r Note 3 1 2 – A ← r r, A Note 3 1 2 – r ← A A, saddr 2 4 5 A ← (saddr) saddr, A 2 4 5 (saddr) ← A A, sfr 2 – 5 A ← sfr sfr, A ...

219 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY rp, #word 3 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX MOVW AX, sfrp 2 – 8 AX ← sfrp sfrp, AX 2 – 8 sfrp ← AX AX, rp Note 3 1 4 – AX ← ...

220 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY A, #byte 2 4 – A, CY ← A – byte × × × saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte × × × A, r Note 3 2 4 – A, CY ← A – r × × × r, A 2 4 – r, CY ← r – A × × × A, saddr 2 4 5 A, CY ← A – (saddr) × × × A, !addr16 3 8 9 A, CY ← A – (addr...

221 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY A, #byte 2 4 – A ← A byte × saddr, #byte 3 6 8 (saddr) ← (saddr) byte × A, r Note 3 2 4 – A ← A r × r, A 2 4 – r ← r A × A, saddr 2 4 5 A ← A (saddr) × A, !addr16 3 8 9 A ← A (addr16) × A, [HL] 1 4 5 A ← A (HL) × A, [HL + byte] 2 8 9 A ...

226 CHAPTER 16 INSTRUCTION SET 16.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ

231 APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD78083 subseries. Figure A-1 shows the configuration of the development tools.

232 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Embedded software • Real-time OS, OS • Fuzzy inference development support system PROM programmer control software • PG-1500 controller Language processing software • Assembler package • C compiler package • C library source...

233 APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K/0 This assembler converts a program written in mnemonics into an object code executable with a Assembler Package microprocontroller. Further, this assembler is provided with functions capable of automatically creating symbol tab...

234 APPENDIX A DEVELOPMENT TOOLS A.2 PROM Programming Tools A.2.1 Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller with on-chip PROM programmer PROM by manipulating from the stand-alone or host machine through connection of the separately available pr...

239 APPENDIX A DEVELOPMENT TOOLS A.4 OS for IBM PC As the OS for IBM PC, the following is supported. To run SM78K0, ID78K0, or FE9200 (refer to B.2 Fuzzy Inference Development Support System), Windows (Ver. 3.0 to Ver. 3.1) is necessary. OS Version PC DOS Ver. 5.02 to 6.3 J6.1/V Note to J6.3/V Note ...

240 APPENDIX A DEVELOPMENT TOOLS A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator If you already have an in-circuit emulator for the 78K series or the 75X/XL series, you can use that in-circuit emulator as the equivalent of the 78K/0 series in-circuit emu...

241 APPENDIX A DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200G-44) Figure A-2. EV-9200G-44 Drawing (For Reference Only) A F D 1 E EV-9200G-44 B C M N O L K R Q I H P J G EV-9200G-44-G0E I T E M M I L L I M E T E R S I N C H E S A B C D E F G H I J K L M N O P Q R 1 5 . 0 1 0 ...

243 APPENDIX B EMBEDDED SOFTWARE APPENDIX B EMBEDDED SOFTWARE This section describes the embedded software which are provided for the µ PD78083 subseries to allow users to develop and maintain the application program for these subseries.

244 APPENDIX B EMBEDDED SOFTWARE B.1 Real-time OS MX78K0 µ ITRON-specification subset OS. Nucleus of MX78K0 is supplied. OS This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. P...

245 APPENDIX B EMBEDDED SOFTWARE B.2 Fuzzy Inference Development Support System FE9000/FE9200 This program supports input of fuzzy knowledge data (fuzzy rule and membership function), Fuzzy Knowledge Data editing (edit), and evaluation (simulation) Creation Tool FE9200 operations on Windows. Part Nu...

247 APPENDIX C REGISTER INDEX APPENDIX C REGISTER INDEX C.1 Register Index 8-bit timer mode control register (TMC5) ............................................................................................................ 87 8-bit timer register 5 (TM5) ..............................................

249 APPENDIX D REVISION HISTORY APPENDIX D REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major revisions from previous version Revised Chapter 2nd The following products have been already developed Throughout µ PD78081CU- ××× , 78081GB- ××× -3B4, 78082CU- ...

250 APPENDIX D REVISION HISTORY Edition Major revisions from previous version Revised Chapter 2nd Figure A-1. Development Tool Configuration has been changed . APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following Development Tools have been added: IE-78000-R-A, IE-70000-98-IF-B, I...

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