IBM DS-2000 - Manuals

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Manual IBM DS-2000

Summary

Page 2 - T A B L E O F C O N T E N T S

T A B L E O F C O N T E N T S WARRANTY INFORMATION . . . . . . . . . . . . i LIST OF FIGURES . . . . . . . . . . . . . iii I. INTRODUCTION . . . . . . . . . . . . . . . . 1 II. BOARD DESCRIPTION . . . . . . . . . . . . . 1 III. 16550 FUNCTIONAL DESCRIPTION . . . . . . . . 3 A. INTERRUPT ENABLE REGIS...

Page 3 - L I S T O F F I G U R E S; iii

L I S T O F F I G U R E S Figure 1. DS-2000 board layout . . . . . . . . . 2Figure 2. 16550 internal registers . . . . . . . 3Figure 3. Interrupt enable register . . . . . . 4Figure 4. Interrupt identification register . . 5Figure 5. Interrupt source identification . . . 6Figure 6. FIFO control regi...

Page 5 - F U N C T I O N A L D E S C R I P T I O N; F i g u r e 1 . D S - 2 0 0 0 b o a r d l a y o u t .

F U N C T I O N A L D E S C R I P T I O N F i g u r e 1 . D S - 2 0 0 0 b o a r d l a y o u t . iii

Page 7 - Figure 3. Interrupt enable register bit definitions.

F U N C T I O N A L D E S C R I P T I O N A . I N T E R R U P T E N A B L E R E G I S T E R +-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmitter hol...

Page 8 - F i g u r e 4 . I n t e r r u p t i d e n t i f i c a t i o n r e g i s t e r b i t

F U N C T I O N A L D E S C R I P T I O N B . I N T E R R U P T I D E N T I F I C A T I O N R E G I S T E R +------+ D7 | FFE |----- FIFO enable (FIFO only) +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1...

Page 10 - Figure 6. FIFO control register bit definitions.

F U N C T I O N A L D E S C R I P T I O N C . F I F O C O N T R O L R E G I S T E R +------+ D7 | RXT1 |--+ +------+ +-- Receiver trigger D6 | RXT0 |--+ +------+ D5 | x |--+ +------+ +-- Reserved D4 | x |--+ +------+ D3 | DMAM |----- DMA mode select +------+ D2 | XRST |----- Transmit FIFO reset +---...

Page 11 - Figure 8. Line Control Register bit definitions.

F U N C T I O N A L D E S C R I P T I O N RRST - Receive FIFO Reset: W h e n s e t ( l o g i c 1 ) , a l l b y t e s i n t h e r e c e i v e rF I F O a r e c l e a r e d a n d t h e c o u n t e r i s r e s e t . T h es h i f t r e g i s t e r i s n o t c l e a r e d . R R S T i s s e l f -c l e a r ...

Page 13 - Figure 11. MODEM control register bit definitions.

F U N C T I O N A L D E S C R I P T I O N E . M O D E M C O N T R O L R E G I S T E R +------+ D7 | 0 | +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | LOOP |----- Loopback enable +------+ D3 | OUT2 |----- Output 2 +------+ D2 | OUT1 |----- Output 1 +------+ D1 | RTS |----- Request to send +------...

Page 14 - Figure 12. Line status register bit definitions.

Page 21 - Figure 17. Available base addresses.

P R O G R A M M A B L E O P T I O N S E L E C T +-------------------------+-------------------+ | ADSx3 ADSx2 ADSx1 ADSx0 | Base address | +-------------------------+-------------------+ | 0 0 0 0 | 3F8H (Serial 1) | | 0 0 0 1 | 2F8H (Serial 2) | | 0 0 1 0 | 3220H (Serial 3) | | 0 0 1 1 | 3228H (Ser...

Page 22 - I X . O U T P U T C O N F I G U R A T I O N S

O U TP U T C O N F I G U R A T I O N S I X . O U T P U T C O N F I G U R A T I O N S T w o s e t s o f j u m p e r s a r e i m p l e m e n t e d o n t h e D S - 2 0 0 0t o c o n t r o l t h e a u x i l i a r y d r i v e r / r e c e i v e r s e t . J u m p e r s J 2a n d J 3 p e r f o r m i d e n t i...

Page 23 - O U T P U T C O N F I G U R A T I O N S

O U T P U T C O N F I G U R A T I O N S T h e o t h e r f u n c t i o n o f J 2 a n d J 3 i s t o c o n f i g u r e t h ec o m m u n i c a t i o n c h a n n e l i n h a l f o r f u l l d u p l e x m o d e . H a l fd u p l e x o p e r a t i o n i s a c h i e v e d b y c o n n e c t i n g p i n s 4 a ...

Page 24 - Figure 19. Output control block diagram.

O U T P U T C O N F I G U R A T I O N S +-----------+| RI +-+ +------+| DCD +-+ +-+ inv. +-+| DSR +-+ | +------+ | (4,5,6 for channel 1,| DTR +-+----+----o o o 1,2,3 for channel 2)| | J4 | +----------+| RCLK +-----------+ | AUXIN | RS-422 +--- +| | +--+--+---------+ Receiver +--- -| | 5 6| 7| 8| +--...

Page 25 - J2 _ Channel 1 J3 _ Channel 2

O U T P U T C O N F I G U R A T I O N S AUXIN ------+ +------ RCLK CTS --+ | | +-- DTR +-------------------+ 5 | o---o o+ o | 8 1 | o---o o+ o | 4 +-------------------+ RTS --+ | | +-- driver enable AUXOUT ------+ +------ XCLK J2 _ Channel 1 J3 _ Channel 2 Figure 21. Jumper configuration showing: (1...

Page 26 - X . E X T E R N A L C O N N E C T I O N S

E XT E R N A L C O N N E C T I O N S X . E X T E R N A L C O N N E C T I O N S C o n n e c t i o n s t o p e r i p h e r a l e q u i p m e n t a r e m a d e v i a af e m a l e D - 9 c o n n e c t o r . A p i n - o u t o f t h e D - 9 c o n n e c t o ra n d a d e t a i l e d d e s c r i p t i o n o f...

Page 27 - I N S T A L L A T I O N

I N S T A L L A T I O N X I . I N S T A L L A T I O N M a k e s u r e t h e r e i s a c o p y o f t h eo r i g i n a l r e f e r e n c e d i s k e t t e a v a i l a b l e .T h i s d i s k e t t e m u s t b e m o d i f i e d t oaccept any option adapters. 1. Turn unit off. 2. Remove system cover as i...