IBM 272 - Manuals - manualsarea.com

Page 2 - Willamette; Intel

PC Processors (Celeron - Willamette) Code nameMicro-architectureMMX ™ / Streaming SIMD SSE2 L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data path Frontside busMemory addressabilityFrontside bus - width Execution units Out-of-order instructionsBranch predictionSpeculativ...

Page 3 - Celeron Northwood

PC Processors (Celeron - Northwood) Code nameMicro-architectureMMX ™ / Streaming SIMD SSE2 L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data path Frontside busMemory addressabilityFrontside bus - width Execution units Out-of-order instructionsBranch predictionSpeculative...

Page 4 - 6KB data 16KB instruction

PC Processors (Mobile Celeron) - Fall 2001 VendorPositioningInstruction architectureMMX ™ / Streaming SIMD L1 cache - sizeL1 cache - write policyL1 cache - organizationL1 cache - busL1 cache - parity L2 cache - sizeL2 cache - data pathL2 cache - buffering L2 cache - organizationL2 cache - controller...

Page 5 - Northwood; Mobile Intel

PC Processors (Mobile Celeron - Northwood) Code nameMicro-architectureMMX ™ / Streaming SIMD SSE2Power mgmt technology L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data path System busMemory addressabilitySystem bus - width Execution units Out-of-order instructionsBranch...

Page 6 - 00MHz Ultra Low Voltage

PC Processors (Intel Celeron M) Code nameMessaging Micro-architectureMMX ™ / Streaming SIMD SSE2Power mgmt technology L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data pathL3 cache System busMemory addressabilitySystem bus - width Execution unitsOut-of-order instructions...

Page 9 - Mobile Northwood

PC Processors (Mobile Intel Pentium 4-M) Code nameMicro-architectureMMX ™ / Streaming SIMD SSE2Hyper-ThreadingPower mgmt technology L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data path L3 cache System busMemory addressabilitySystem bus - width Execution units Out-of-or...

Page 11 - used with RDRAM-based 850 chipset

PC Processors (Pentium 4) Code nameMicro-architectureMMX ™ / Streaming SIMD SSE2 L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data path Front Side BusMemory addressabilityFront Side Bus - width Execution units Out-of-order instructionsBranch predictionSpeculative executi...

Page 13 - Prescott

PC Processors (Pentium 4 - Prescott) Code nameMicro-architectureMMX ™ / Streaming SIMD SSE2SSE3Hyper-Threading L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data path L3 cache System bus Memory addressabilitySystem bus - width Execution units Out-of-order instructionsBran...

Page 14 - PC Processors (Pentium 4 Extreme Edition); Intel Pentium 4 Processor with HT Technology Extreme Edition

PC Processors (Pentium 4 Extreme Edition) Code nameFormal nameMicro-architectureMMX ™ / Streaming SIMD SSE2Hyper-Threading L1 cache - busL1 data cacheL1 instruction cache L2 cache - sizeL2 cache - data path L3 cacheL3 cache - data path System bus Memory addressabilityFrontside bus - width Execution ...

Page 15 - IBM

This publication could include technicalinaccuracies or typographical errors.References herein to IBM products andservices do not imply that IBM intendsto make them available in othercountries. IBM PROVIDES THISPUBLICATION AS IS WITHOUTWARRANTY OF ANY KIND, EITHEREXPRESS OR IMPLIED, INCLUDINGTHE IMP...