IBM 25CPC710 - Manuals

IBM 25CPC710 – Manual in PDF format online.

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Manual IBM 25CPC710

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Summary

Page 2 - This is a change from the previous revision.; I/O Signal New Functionality

Page 2 of 8 Version 1.0 11/08/01 Processor Interface: v Voltage Level and Bus Speed Differences Ø The CPC710 DD3.x revision supports 60x bus operation at speeds of up to 133MHz, at an I/O voltage of 2.5V. This interface voltage level is supported on the PPC750L, 750CX, and 750CXe processors. This is...

Page 3 - Refer to the CPC710-133 User’s Manual for more information.; Supported Memory Types

Page 3 of 8 Version 1.0 11/08/01 Memory Interface: v Extended SDRAM Addressing Ø The signal MADDR13 has been added to support the following additional SDRAM organizations: § 13-12-2, 14-9-2, 14-10-2, 14-11-2, 14-12-2 § Register SDRAM0_MCER [26:29] is used to select the SDRAM organization; refer to t...

Page 4 - PCI-32 Interface Now Supports External Arbiter Usage; This is a change from the

Page 4 of 8 Version 1.0 11/08/01 v Extended Addressing of PCI Memory Ø System memory addressing range increased from 2GB to 4GB. The standard addressing capability is 2GB; with the size defined by bits 24-31 of PCI local registers PCILx_PSSIZE. The address extension is implemented by setting bit 27 ...

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