Agilent HDMP-3001 - Manuals

6 • Implemented in 0.25 micronCMOS with 1.8 V core, 3.3 V I/Opower and LVCMOScompatible I/Os. • Provides a 16-bit general pur-pose I/O (GPIO) register. • Device power-up initializationoptionally through 2-wireEEPROM interface. • Configurable by hardware tobe connected to either a PHYor a MAC from th...

17 3. Functional Description 3.1 Introduction The HDMP-3001 performs full-duplex mapping of Ethernetframes into a SONET STS-3c /SDH STM-1 payload using theLAPS or GFP protocol. AllSONET/SDH framing functionsare included. A TOHinterface provides direct add/dropcapability for E1, E2, F1, and bothSecti...

18 3.2.5 SONET/SDH Interface This interface is 8 bits wide andruns at 19.44 MHz. The SerialSONET/SDH overhead channelsare clocked in and out of the ICthrough low-speed serial ports. 3.3 Initialization 3.3.1 Hardware reset The HDMP-3001 hardware reset,RSTB, is asynchronous and mustbe active for at le...

19 3.4.2 LAPS Mode In LAPS mode the FCS is calcu-lated LSB first and the FCS sum istransmitted in reversed bit orderwithin each byte. See Figure 6 andFigure 7. 3.5 Performance Monitoring For performance monitoring pur-poses, the HDMP-3001 contains anumber of delta bits, event bitsand error counters....

22 EOS_D_SUM group indicates that at least one of the delta sig-nals below is unmasked and set.NEW_RX_MIN_ERR,NEW_RX_MAX_ERR,NEW_RX_OOS_ERR,NEW_RX_FORM_DEST_ERR,NEW_RX_FIFO_UR_ERR,NEW_RX_FIFO_OF_ERR,NEW_RX_FCS_HEC_ERR,NEW_TX_FIFO_UR_ERR,NEW_TX_FIFO_OF_ERR,NEW_TX_ER_ERR,NEW_TX_MII_ALIGN_ERR 3.7.4 APS...

24 MSB PLI '+' 0xB6 NUMBER OF BYTES IN THE GFP PAYLOAD LSB PLI '+' 0xAB MSB cHEC '+' 0x31 LSB cHEC '+' 0xE0 MSB TYPE PROGRAMMABLE LSB TYPE PROGRAMMABLE MSB tHEC LSB tHEC MSB eHEC LSB eHEC MSB FCS[31:24] 1) 32-BIT CRC POLYNOMIAL FCS[23:16] 2) ON PRE-SCRAMBLED DATA FCS[15:8] 3) COVERS THE GFP PAYLOAD ...

25 • Pointer Bytes, H1, H2, H3 • BIP-96/24, B2 • APS bytes, K1, K2 • Synchronization Status, S1 • Line/MS REI, M1 • Transmits undefined TOH/SOHas fixed all zeros. • Scrambles payload usingSONET/SDH framesynchronous descrambler,polynomial (X 7 + X 6 +1). 3.9.2 Receive SONET/SDH Process-ing Overview T...

26 3.9.3.2 POH There are nine bytes of path over-head. The first byte of the pathoverhead is the path trace byte,J1. Its location with respect to theSONET/SDH TOH/SOH is indi-cated by the associated STS/AUpointer. The following sectionsdefine the transmitted values ofthe POH bytes. Where the bytenam...

27 PRDI_AUTO PRDI_ENH RX_PAIS RX_UNEQ RX_PLM G1 Bits 5, 6, and 7 RX_LOP 0 x x x x TX_G1[2:0] 1 0 1 x x 100 0 x x 000 1 1 x x 101 0 1 x 110 0 0 1 010 0 0 0 001 Table 11. Path RDI bit values 3.9.3.2.9 POH AIS Generation Normal generation of SONET/SDH payload is suspended duringtransmission of the Line...

28 Row Column 1 2-3 4 5-6 7 8-9 1 A1[1] A1[2,3] A2[1] A2[2,3] J0[1] Z0[2,3] 2 B1 E1 F1 3 D1 D2 D3 4 H1[1] H1[2,3] H2[1] H2[2,3] H3[1] H3[2,3] 5 B2[1] B2[2,3] K1 K2 6 D4 D5 D6 7 D7 D8 D9 8 D10 D11 D12 9 S1 Z1[2,3] 1 Z2[1] 1 Z2[2] 1 , M1 E2 Table 12. STS-3c/STM-1 TOH/SOH 3.9.3.3.4 Section Growth/Spare...

29 Non-AIS Generation. The first H1-H2 byte pair is transmitted asa normal pointer with: • NDF = 0110 • SS (SONET/SDH) = 0 • Pointer Value = 10_0000_1010 All other H1-H2 byte pairs aretransmitted as concatenation indi-cation bytes, with • NDF =1001 • SS = 0 • Pointer Value = 11_1111_1111. See Figure...

32 • If PTR_STATE[1:0] = 00and {LOP2,AIS2} = 11 and{LOP3,AIS3} = 11, which is thenormal case, then RX_PAIS = 0and RX_LOP = 0. • If PTR_STATE[1:0] = 01and {LOP2,AIS2} = 01 and{LOP3,AIS3} = 01, thenRX_PAIS = 1 and RX_LOP = 0. • If PTR_STATE[1:0] = 10and {LOP2,AIS2} = 01 and{LOP3,AIS3} = 10, thenRX_PAI...

33 cates that the VC-4 starts threebytes after the K2 byte. In addition, 8-bit counters are pro-vided for counting positive andnegative justification events, aswell as NDF events. Status bitsare provided for indicating the de-tection of negative justification,positive justification, NDF, invalid LOP...

34 Norm_point: Normal NDF AND match of ss bits AND offset value in range. NDF_enable: NDF enabled AND match of ss bits AND offset value in range. AIS_ind: 11111111 11111111. Incr_ind: Normal NDF AND match of ss bits AND majority of I bits inverted AND no majority ofD bits inverted AND previous NDF_e...

35 can result in from 0 to 8 mis-matches (B3 bit errors). Thisvalue can be inserted into theTransmit Side G1 byte from bitone to bit four as a Path REI. The HDMP-3001 contains a 16-bitB3 error counter that counts everyB3 bit error. When the perfor-mance monitoring counters arelatched (LATCH_EVENT tr...

36 high-speed device that locatesframe, does byte de-interleaving,and performs serial-to-parallelconversion of an STS-3c/STM-1signal. 3.9.4.11 Framer Enabled Details If the framer is enabled(RX_FRMR_INH = 0), theHDMP-3001 device performs theframer processing as follows. When the framer state machine...

38 4. Application Information 4.1 Chip setup and configuration 4.1.1 EEPROM Detection After reset, HDMP-3001 will probethe SDA pin. If tied to ground, noboot EEPROM is present and nor-mal operation will resume. Ifconnected to an EEPROM, SDA ispulled high by an internal resistorand HDMP-3001 will sta...

40 4.3 Firmware and System DesignInformation 4.3.1 Board level pull-ups andpull-downs Many of the HDMP-3001 input andtristateable outputs have internalpull-ups. Refer to the pin descrip-tion for detailed information onwhere external pull-ups are re-quired. 4.3.2 Motorola MPC860Microprocessor Interfa...

42 5. Register Definitions The HDMP-3001 contains two reg-ister maps. One is the MIIManagement (MDIO) registermap, which can only be accessedthrough the MDIO port. The otherregister map is the chip registermap which can be accessedthrough the MDIO, microproces-sor and EEPROM ports. 5.1 MII Managemen...

48 Address Register Name 0x1CF Receive Spare Field Byte 0x1D0 Receive Pre-Sync States 0x1D1-0x1D2 Receive SAPI Field 0x1D3 Reserved 0x1D4-0x1D7 Receive MII Frames Transmitted OK 0x1D8-0x1DB Receive FCS and HEC Error Counter 0x1DC-0x1DF Receive Format and Destination Error Counter 0x1E0-0x1E3 Receive...

52 ADDR=0x007: Event Summary Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TOH_D_SUM Reserved PTR_D_SUM POH_D_SUM Reserved EOS_D_SUM Reserved Reserved R/W R — R R R R — — Value 0 0 0 0 0 0 0 0 afterreset Bit 7: TOH_D_SUM is set to indicate at least one of the TOH/SOH delta bits (RX_LOS_D,...

54 ADDR=0x00B: SONET/SDH Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved TX_UNEQ Reserved Reserved TX_SONET RX_SONET_DSCR Reserved _SCR_INH _INH R/W — — R/W — — R/W R/W — Value 0 0 0 0 0 0 0 0 afterreset Bits 7-6: Reserved Bit 5: TX_UNEQ is set to generate al...

57 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_J0[0]_[7:0] • • • TX_J0[15]_[7:0] R/W R/W Value 0 0 0 0 0 0 0 0 afterreset ADDR=0x09F –0x0AE: Transmit J0 Bytes 1 – 16 Bits 7-0: TX_J0[0:15]_[7:0]: Transmit J0 (Section Trace) – When enable, the HDMP-3001 will continuously transmit in th...

66 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_J0 [0]_[7:0] • • • RX_J0 [15]_[7:0] R/W R Value 0 afterreset ADDR=0x104 –0x113: Receive J0 Bytes 0 – 15 Bits 7-0: RX_J0 [0:15]_[7:0]: (Section Trace) The received 16 J0 bytes. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Rese...

67 Bits 7-0: RX_K1[7:0]: (APS Signaling) The received K1 byte. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_K1 [7:0] R/W R Value 0 0 0 0 0 0 0 0 afterreset ADDR=0x117: Receive K1 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B1_ERRCNT[7:0] R/W R Value 0 0 0 0 0 0 0 0 a...

68 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B2_ERRCNT[7:0] R/W R Value 0 0 0 0 0 0 0 0 afterreset ADDR=0x11B: Receive B2 Error Count Bits 7-0: B2_ERRCNT[15:8] Bits 7-0: B2_ERRCNT[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B2_ERRCNT[15:8] R/W R Value 0 0 0 0 0 0 0 0...

71 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved P_STATE[1:0] RX_LOP RX_PAIS R/W — — — — R R R Value 0 0 0 0 0 0 1 1 afterreset ADDR=0x128: Receive Pointer Status(1) Bits 7-3: Reserved Bits 3-2: P_STATE_[1:0]: These bits are used to monitor the first pa...

76 ADDR=0x174: Receive Path Delta Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved RX_C2_D RX_G1_D RX_UNEQ_ RX_PLM_D Reserved D R/W — — — W1C W1C W1C W1C — Value 0 0 0 0 0 0 0 — afterreset Bits 7-5: Reserved Bit 4: RX_C2_D: RX_C2 delta bit. It is set when a new val...

77 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved RX_G1[2:0] RX_UNEQ RX_PLM Reserved R/W — — R R R — Value 0 0 0 0 0 0 afterreset ADDR=0x178: Receive UNEQ Monitor Bits 7-6: Reserved Bits 5-3: RX_G1[2:0]: When a consistent G1 monitor is received, bits 5,6, and 7 of G1 are ...

78 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B3_ERRCNT[15:8] R/W R Value 0x00 afterreset ADDR=0x17C: B3 Error Count Bits 7-0: B3_ERRCNT [15:8]: A 16-bit counter that counts every BIP-8 (B3) error. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name G1_ERRCNT[7:0] R/W R Value 0x00...

80 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_CNT_TYPE_L[7:0] R/W R/W Value 0x03 afterreset ADDR = 0x182: Transmit Control/Type_L Byte Bits 7-0: TX_CNT_TYPE_L[7:0] specifies the Control Byte for LAPS mode and the LSB of the TYPE field for GFP mode, which is the Payload Identifier. T...

81 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_FIFO_THRESHOLD[7:0] (LSB) R/W R/W Value 0x88 afterreset ADDR = 0x184: Transmit FIFO Threshold[7:0] (LSB) TX_FIFO_THRESHOLD[7:0] specifies the LSB of the TX FIFO Threshold which is used by the INFO FIELD TX FIFO Controller to determine wh...

83 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_SAPI_L_SPARE[7:0] R/W R/W Value 0x01 afterreset ADDR = 0x188: Transmit SAPI LSB / Spare Byte Bits 7-0: TX_SAPI_L_SPARE[7:0] is the LSB of the SAPI field in LAPS mode and the spare field byte in GFP frame. In LAPS mode it is sent as part ...

84 TX_MII_FRAMES_REC_OK[23:0] is the Transmit MII Frames Received OK counter. It is non-resetable except that a hard or soft reset will clear it. After reaching its max value the counter starts over from zeroagain. This counter is incremented for each frame that was properly byte aligned, did not ca...

87 ADDR = 0x1A1: Ethernet Transmit Interrupt Mask Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved NEW_TX_ NEW_TX_ NEW_TX_ NEW_TX_ FIFO_UR_ FIFO_OF_ ER_MASK MII_ALIGN MASK MASK _MASK R/W — — — — R/W R/W R/W R/W Value 0 0 0 0 1 1 1 1 afterreset Bits 7-4: Re...

89 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved RX_FIFO_THRESHOLD[10:8] R/W — — — — — R/W Value 0 0 0 0 0 0x1 afterreset ADDR = 0x1C3: RX FIFO Transmit Threshold[10:8] Bits 7-3: Reserved Bits 2-0: RX_FIFO_THRESHOLD[10:8] are the three MSBs of ...

90 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved HI_IFG_WATER_MARK[10:8] R/W — — — — — R/W Value 0 0 0 0 0 0x6 afterreset ADDR = 0x1C5: High Inter-Frame-Gap Water Mark Bits 7-3: Reserved Bits 2-0: HI_IFG_WATER_MARK[10:8] are the three MSBs of t...

92 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved LOW_IFG[4:0] R/W — — — R/W Value 0 0 0 0x0A afterreset ADDR = 0x1C9: Low Inter-Frame-Gap Bits 7-5: Reserved Bits 4-0: LOW_IFG[4:0] specifies the Low Inter-Frame-Gap which is used by the MII RX interface to insert ...

93 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_CNT_TYPE_H [7:0] R/W R/W Value 0x03 afterreset ADDR = 0x1CB: Receive Control/TYPE_H Bits 7-0: RX_CNT_TYPE_H [7:0] specifies the expected Control when in LAPS mode or the expected MSB of the Type field when in GFP mode, which consists of ...

94 ADDR = 0x1CD: LAPS Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved RX_ADR_ RX_CNT_ RX_SAPI_ RX_ADR_ RX_CNT_ RX_SAPI_ REM_INH REM_INH REM_INH CHECK_ CHECK_ CHECK_ INH INH INH R/W — — R/W R/W R/W R/W R/W R/W Value 0 0 0 0 0 0 0 0 afterreset Bits 7-6: Reserved Bit 5: ...

96 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved RX_PRESYNC[3:0] R/W — — — — R/W Value 0 0 0 0 0x1 afterreset ADDR = 0x1D0: Receive Pre-Sync States Bits 7-4: Reserved Bits3-0: RX_PRESYNC specifies the number of Pre-Sync states the GFP RX Processor perfo...

104 6. Package Specification Package marking and outline drawings for the HDMP-3001 28x28mm, 160 pin PQFP. Figure 25. Top View of Package HDMP-3001 LLLLLLLLL-NNN G YYWW R.RCCCCC LLLLLLLLL - WAFER LOT NUMBER NNN - WAFER NUMBER G - SUPPLIER CODE YY - LAST TWO DIGITS OF YEAR WW - TWO DIGIT WORK WEEK R....

107 Table 23. Absolute Maximum Ratings Parameter Min Max Units Supply Voltage (VDD) -0.5 2.5 Volts Supply Voltage (DVDD) -0.5 4.5 Volts Junction Temperature 0.0 110 ° C Storage Temperature -40 125 ° C ESD 2 KV Caution: Exceeding the values stated above could permanently damage the device.Prolonged e...

110 8. Timing Diagrams 8.1 Microprocessor Bus Timing - Write Cycle Figure 29. Microprocessor Write Cycle Timing. * RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. Thisadds an additional delay of between one and two microprocessor clock cycles. VALID VALID NEW VA...

111 8.2 Microprocessor Bus Timing - Read Cycle. Figure 30. Microprocessor Read Cycle Timing. * RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. Thisadds an additional delay of between one and two microprocessor clock cycles. VALID t 7 t 10 t 9 INVALID VALID CAPTU...

112 8.3 Microprocessor Bus Timing Table Table 30. Timing of microprocessor bus Parameter Description Min (ns) Max (ns) t 1 CS_N active to RDYB driven to inactive state 0 15 t 2 CS_N, WRB and RDB valid to A and D captured 90 270 t 3 1 CS_N, WRB and RDB valid to RDYB active 140 1 220 1 t 4 BUSMODE 0: ...

113 RX_SONETCLK RX_DATA[7:0] RX_FRAME_IN t HRDFC t HFIFC t SRDTC t SFITC Label Parameter Min Max Units RX_SONETCLK RX_SONETCLK frequency 19.44-20ppm 19.44+20ppm MHz t SRDTC Setup RX_DATA to RX_CLK high 5 ns t HRDFC Hold RX_DATA from RX_CLK high 5 ns t SFITC Setup RX_FRAME_IN to RX_CLK high 5 ns t HF...

114 8.6 TOH Interface E1/E2/F1 Receive Timing RX_E1E2F1_CLK RX_E1_DATARX_E2_DATA RX_F1_DATA t VE1FC t HE2FC t HF1FC Label Parameter Min Typ. Max Units RX_E1E2F1_CLK TX_E1E2F1_CLK frequency 64 kHz t VE1FC Transition RX_E1_DATA from RX_E1E2F1_CLK low 30 70 ns t HE2FC Transition RX_E2_DATA from RX_E1E2...

115 RX_SDCC_CLK RX_LDCC_CLK RX_SDCC_DATA RX_LDCC_DATA t VSDCFC t VLDCFC Label Parameter Min Typ. Max Units RX_SDCC_CLK RX_SDCC_CLK frequency 192 kHz t VSDCFC Transition RX_SDCC_DATA from RX_SDCC_CLK low 30 70 ns RX_LDCC_CLK RX_LDCC_CLK frequency 576 kHz t VLDCFC Transition RX_LDCC_DATA from RX_LDCC_...

116 8.10 Reset specification The HDMP-3001 reset pin (RSTB)is an asynchronous pin that mustbe active for at least 200 SONETclock cycles (>10 µ s) with stable power. TX_CLK TX_D[3:0], TX_EN, TX_ER RX_D[3:0], RX_DV, RX_ER RX_CLK t TX 0 ns MIN., 25 ns MAX. t RXS 10 ns MIN. t RXH 10 ns MIN. VALID VAL...

118 8.13 EEPROM Port Timing Table 32. EEPROM Interface Timing Parameters Parameter MIN MAX UNITS SCL clock frequency 97.2 kHz SCL high period 4.9 µ s SCL low period 4.9 µ s Setup time for reSTART 4.9 µ s Hold time for START/reSTART 4.9 µ s Setup time for STOP 4.9 µ s Bus free between STOP & STAR...

119 FOUR CONSECUTIVE FRAMES CONTAINING FRAMING PATTERN ERRORS A1 A1 A1 A2 A2 A2 A1 A1 A1 A2 A2 A2 A1 A1 A1 A2 A2 A2 A1 A1 A1 A2 A2 A1/A2 ERROR A1/A2 ERROR A1/A2 ERROR A1/A2 ERROR A2 C1 C1 C1 RX_DATA[7:0] RX_SONETCLK OOF The out of frame declaration timing diagram (Figure 40) illustrates the declarat...

120 Figure 43. Transmit Overhead Clock and Data Alignment The transmit overhead clock and data alignment timing diagram (Figure 43) shows the relationshipbetween the TX_E1_DATA, TX_E2_DATA and TX_F1_DATA serial data inputs and their associated clockTX_E1E2F1_CLK. It is a 72 kHz 50% duty cycle clock ...

121 APPROX. 750 ns E1, E2, F1 B1 B2 B3 B4 B5 B6 B7 B8 RX_FRAME_SFP RX_SONETCLK RX_E1E2F1_CLK Figure 44. Receive Overhead Clock and Data Alignment The receive overhead alignment timing diagram (Figure 44) shows the relationship between theRX_E1_DATA, RX_E2_DATA and RX_F1_DATA serial data outputs and ...

122 APPROX. 2M TX_LDCC_CLK BURSTS ROW 1 BYTES ROW 2 BYTES ROW 3 BYTES ROW 4 BYTES ROW 5 BYTES ROW 6 BYTES ROW 7 BYTES ROW 8 BYTES ROW 9 BYTES B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 TX_FRAME_SFP T...

123 ROW 1 BYTES ROW 2 BYTES ROW 3 BYTES ROW 4 BYTES ROW 5 BYTES ROW 6 BYTES ROW 7 BYTES ROW 8 BYTES ROW 9 BYTES B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 RX_FRAME_SFP RX_SDCC_CLK RX_SDCC_DATA RX_LDC...

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