Agilent HDMP-3001 - Manual

Agilent HDMP-3001

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Table of Contents:

  • Page 3 – List of Figures
  • Page 4 – List of Tables
  • Page 5 – provides GFP (Generic Framing; Internal Functional Blocks; See the Figure 1 block diagram.; Figure 1. Functional Block Diagram; Packaged in a 160 pin PQFP.
  • Page 6 – +1 scrambling of the
  • Page 17 – Functional Description; Interface Descriptions
  • Page 18 – Figure 4. GFP Payload Bit Order
  • Page 19 – Performance Monitoring; Figure 6. LAPS Payload Bit Order
  • Page 22 – group indicates; Figure 9. An Ethernet MAC frame
  • Page 24 – Figure 11. The GFP frame; • Section User Channel, F1
  • Page 25 – • Synchronization Status, S1
  • Page 26 – Path RDI; . Bit 5 of G1 can be used
  • Page 27 – Table 11. Path RDI bit values
  • Page 28 – Row Column
  • Page 29 – The first; Figure 14. Pointer Byte Fields; s of detection and re-
  • Page 32 – Any variation from the current
  • Page 33 – Figure 15. Pointer Processing
  • Page 34 – Table 13. Pointer Processing; Normal NDF AND match of ss bits AND offset value in range.; Table 14. Pointer Tracking; The MSBs of all path
  • Page 35 – the all zeros Unequipped label,
  • Page 36 – Figure 17. Functional block of SONET framer scrambler
  • Page 38 – Application Information; Chip setup and configuration
  • Page 40 – HDMP-3001 Pin Name Microprocessor Pin Name; Microprocessor Pin Name
  • Page 42 – Register Definitions
  • Page 48 – of; DEFAULT; is the value of the reg-
  • Page 52 – Value; Reserved; Bit name
  • Page 54 – GPIOCTL5
  • Page 57 – These bits are automatic protection switching (APS) signaling.
  • Page 66 – (Synchronization Message) The received four LSBs of the S1 byte.
  • Page 67 – A 16-bit B1 error counter that counts B1 bit errors.
  • Page 68 – A 24-bit B2 error counter that counts every B2 bit error.
  • Page 71 – Receive Loss of Pointer Indication
  • Page 76 – • all zeros unequipped label
  • Page 77 – It contributes to the insertion of Path RDI.
  • Page 78 – The lower byte of the G1 error counter.; The upper byte of the G1 error counter.
  • Page 80 – specifies the Rate Adaptation Byte for LAPS mode and the MSB of the
  • Page 81 – specifies the LSB of the TX FIFO Threshold which is used by the; MSBs of the register above.
  • Page 83 – is the LSB of the SAPI field in LAPS mode and the spare field byte in; is the MSB of the SAPI field in the LAPS header. It is inhibited by the
  • Page 84 – is the Transmit MII Frames Received OK counter. It is non-resetable
  • Page 87 – MASK; is set to suppress the new TX FIFO Underrun Error from setting the
  • Page 89 – are the three MSBs of the previous register.; is the LSB of the High Inter-Frame-Gap Water Mark which is
  • Page 90 – is the LSB of the Low Inter-Frame-Gap Water Mark which is
  • Page 92 – specifies the expected address when in LAPS mode or the expected
  • Page 93 – specifies the expected Control when in LAPS mode or the expected
  • Page 94 – INH; is set to inhibit the checking of the received Address field.
  • Page 96 – specifies the expected LSB of the SAPI field when in GFP mode. If; is the MSB of the field above.
  • Page 104 – Package Specification; Figure 25. Top View of Package; LLLLLLLLL - WAFER LOT NUMBER; Figure 24. Package Marking
  • Page 107 – Electrical and Thermal Specifications; is measured in a still air environment at 25; x P
  • Page 110 – Microprocessor Bus Timing - Write Cycle; Figure 29. Microprocessor Write Cycle Timing.
  • Page 111 – Figure 30. Microprocessor Read Cycle Timing.
  • Page 112 – Figure 31. Line Interface Transmit Timing; between one and two microprocessor clock cycles.
  • Page 113 – Figure 32. Line Interface Receive Timing.
  • Page 114 – Figure 35. DCC Interface Transmit Timing
  • Page 115 – Figure 36. DCC Interface Receive Timing
  • Page 116 – Reset specification; Figure 38. MII timing as defined by IEEE 802.3
  • Page 118 – Figure 39. In Frame Declaration
  • Page 119 – Figure 40. Out of Frame Declaration; Figure 41. Loss of Frame Declaration/Removal; Figure 42. Line AIS and Line RDI Declaration/Removal
  • Page 120 – Figure 43. Transmit Overhead Clock and Data Alignment
  • Page 121 – Figure 44. Receive Overhead Clock and Data Alignment
  • Page 122 – Figure 45. Transmit Data Link Clock and Data Alignment
  • Page 123 – Figure 46. Receive Data Link Clock and Data Alignment
  • Page 124 – Applicable Documents; Bellcore Specification “SONET
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Agilent HDMP-3001
Ethernet over SONET Mapper IC
Device Specification

Data Sheet

Table of Contents

1. Introduction ............................................................................................... 5

1.1 Internal Functional Blocks .............................................................. 5
1.2 HDMP-3001 Features List ................................................................ 5
1.3 Applications ....................................................................................... 6
1.4 Benefits ............................................................................................... 6
1.5 Interfaces ............................................................................................ 6
1.6 Data Processing ................................................................................. 6

2. Pinout ......................................................................................................... 7

2.1 Pin Assignments ................................................................................ 7
2.2 Pin Descriptions ................................................................................ 8
2.3 I/O Buffer Types .............................................................................. 16

3. Functional Description .......................................................................... 17

3.1 Introduction ..................................................................................... 17
3.2 Interface Descriptions .................................................................... 17

3.2.1 Microprocessor Interface ....................................................... 17
3.2.2 MII Management Interface .................................................... 17
3.2.3 EEPROM Interface .................................................................. 17
3.2.4 MII Interface ............................................................................. 17
3.2.5 SONET/SDH Interface ............................................................. 18

3.3 Initialization ..................................................................................... 18

3.3.1 Hardware reset ......................................................................... 18
3.3.2 Software Reset ......................................................................... 18
3.3.3 Software State Machine Reset ............................................... 18

3.4 Bit Order ........................................................................................... 18

3.4.1 GFP Mode ................................................................................. 18
3.4.2 LAPS Mode ............................................................................... 19

3.5 Performance Monitoring ................................................................ 19
3.6 Test .................................................................................................... 20

3.6.1 Loopbacks ................................................................................. 20
3.6.2 JTAG .......................................................................................... 21

3.7 Interrupts .......................................................................................... 21

3.7.1 Interrupt Driven Mode ........................................................... 21
3.7.2 Polled Mode .............................................................................. 21
3.7.3 Interrupt Sources ..................................................................... 21
3.7.4 APS_INTB ................................................................................. 22

3.8 Data Processing ............................................................................... 22

3.8.1 LAPS Processing ...................................................................... 22
3.8.2 GFP Processing ........................................................................ 23

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Summary

Page 3 - List of Figures

3 List of Figures Figure 1. Functional Block Diagram ......................................................... 5Figure 2. HDMP-3001 applications ............................................................ 6Figure 3. HDMP-3001 pin assignments ..................................................... 7Fi...

Page 4 - List of Tables

4 List of Tables Table 1. Line Side Interface Pins Description ........................................... 8Table 2. MII Interface Pins Description ..................................................... 9Table 3. Transport Overhead Pins Description ...................................... 10Table 4. Mi...

Page 5 - provides GFP (Generic Framing; Internal Functional Blocks; See the Figure 1 block diagram.; Figure 1. Functional Block Diagram; Packaged in a 160 pin PQFP.

5 1. Introduction The Agilent HDMP-3001 is ahighly integrated VLSI device thatprovides mapping of Ethernet en-capsulated packets into STS-3cpayloads. The HDMP-3001 sup-ports full-duplex processing ofSONET/SDH data streams withfull section, line, and path over-head processing. The devicesupports fram...

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