Page 2 - ii; Copyright; Disclaimer
ii Copyright Copyright 1997 by Acer Incorporated. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any languageor computer language, in any form or by any means, electronic, mechanical, magnetic, optical,...
Page 3 - iii; About this Manual; Purpose; This appendix illustrates the system board and CPU silk screens.
iii About this Manual Purpose This service guide aims to furnish technical information to the service engineers and advancedusers when upgrading, configuring, or repairing the TM7100 series notebook computer. Manual Structure This service guide contains technical information about the TM7100 series ...
Page 4 - iv; Appendix D; This appendix lists and describes the BIOS POST checkpoints.; Conventions; The following are the conventions used in this manual:; Text entered by user; Represents text input by the user.; Screen messages; Denotes actual messages that appear onscreen.
iv Appendix D Schematics This appendix contains the schematic diagrams for the system board. Appendix E BIOS POST Checkpoints This appendix lists and describes the BIOS POST checkpoints. Conventions The following are the conventions used in this manual: Text entered by user Represents text input by ...
Page 7 - vii; Chapter 3
vii 2.4.3 Pin Diagram .........................................................................................2-40 2.4.4 Pin Descriptions ...................................................................................2-41 2.5 Philips 87C552 System Management Controller ............................
Page 8 - viii; Chapter 4
viii 3.3 Advanced System Configuration ...........................................................................3-5 3.3.1 Internal Cache........................................................................................3-5 3.3.2 External Cache ....................................................
Page 9 - ix
ix 4.8.1 Detaching the Lower Housing from the Inside Assembly ......................4-14 4.8.2 Detaching the Upper Housing from the Inside Assembly ......................4-15 4.8.3 Removing the Touchpad ......................................................................4-16 4.8.4 Removing the Mai...
Page 10 - List of Figures
x List of Figures 1-1 Lid Switch .............................................................................................................1-2 1-2 Rear Port Location ................................................................................................1-3 1-3 Left Port Location ...........
Page 11 - xi
xi 4-8 Installing and Removing Memory ......................................................................... 4-8 4-9 Removing the Display Hinge Covers ...................................................................4-10 4-10 Removing the Center Hinge Cover ........................................
Page 12 - xii; List of Tables
xii List of Tables 1-1 Rear Port Descriptions ..........................................................................................1-3 1-2 Left Port Descriptions............................................................................................1-5 1-3 Indicator Light Descriptions ........
Page 13 - xiii
xiii 1-35 Battery Specifications .........................................................................................1-40 1-36 DC-DC Converter Specifications .........................................................................1-40 1-37 DC-AC Inverter Specifications ...........................
Page 14 - System Introduction
C h a p t e r 1 C h a p t e r 1 System Introduction System Introduction 1-1 The computer is packed with features that make it as easy to work with as it is to look at. Here aresome of the computer’s features: 1.1 Features PERFORMANCE • Intel Pentium ® processor with MMX™ technology • 64-bit main mem...
Page 15 - USB port onboard; Lid Switch
1-2 Service Guide • Ergonomically-positioned touchpad pointing device EXPANDABILITY • CardBus PC Card (PCMCIA) slots (two type II/I or one type III) with Zoomed Video portfunction • Mini-dock option with two CardBus PC Card slots (two type II/I or one type III) • USB port onboard • Upgradeable memor...
Page 16 - Port
System Introduction 1-3 1.2 Ports The computer’s ports allow you to connect peripheral devices to your computer just as you would toa desktop PC. The main ports are found on the computer’s rear panel. The computer’s left panelcontains the computer’s multimedia ports and PC card slots. 1.2.1 Rear Pan...
Page 17 - Service Guide; Left Port Location
1-4 Service Guide UNIVERSAL SERIAL BUS (USB) PORT The computer’s USB (Universal Serial Bus) port located on the rear panel allows you to connectperipherals without occupying too many resources. Common USB devices include the mouse andkeyboard. FAST INFRARED (FIR) PORT The computer’s FIR (fast infrar...
Page 18 - Indicator Lights; Indicator Light; Power Indicator
System Introduction 1-5 Table 1-2 Left Port Descriptions Port Icon Connects to... PC Card slots Two type I/II PC Cards or one type III Card Microphone-in/ Line-in External microphone or line input device Speaker-out/ Line-out Amplified speakers or headphones PC CARD SLOTS The computer contains two P...
Page 19 - Hot Key
1-6 Service Guide 1.2.4 Hot Keys The computer’s special Fn key, used in combination with other keys, provides “hot-key”combinations that access system control functions, such as screen contrast, brightness, volumeoutput, and the BIOS setup utility. Table 1-4 Hot Key Descriptions Hot Key Icon Functio...
Page 20 - Eject Menu Item Descriptions
System Introduction 1-7 Table 1-4 Hot Key Descriptions Hot Key Icon Function Description Fn+ ÿ + ↑ Brightness Up Increases screen brightness Fn+ ÿ + ↓ Brightness Down Decreases screen brightness Fn+ ÿ + → Contrast Up Increases screen contrast (not available for TFT displays) Fn+ ÿ + ← Contrast Down ...
Page 22 - System Specification Overview; System Specifications; Item
System Introduction 1-9 1.3 System Specification Overview Table 1-6 System Specifications Item Standard Optional Microprocessor Intel Pentium ® processor with MMX™ technology Memory System / Main External cache 32MBDual 64-bit memory banks 512KB L2 cache (synchronous SRAM) Expandable to 128MB using8...
Page 29 - Jumpers and Connectors; Mainboard Jumpers and Connectors (Top Side)
1-16 Service Guide 1.5 Jumpers and Connectors 1.5.1 Mainboard CN1 CN2 CN3 CN4 CN5 CN6 CN13 CN14, CN15 CN7 U1 CN10 CN11 CN12 CN8 CN9 CN1 USB CN2 VGA port CN3 Mini dock port CN4 Parallel port CN5 Serial Port CN6 PS2 mouse/keyboard port CN7 AC adapter plug-in port CN8, CN9 Multimedia board connector CN...
Page 30 - Jumper Pad; Keyboard type selection
System Introduction 1-17 CN16 CN22 CN17 CN19, CN18 SW1 CN20 SI2 SI1 SW2 ONOFF 1 4 CN20, CN19 DC-DC converter connector CN17 Left speaker connector CN20 Debug port CN22 Battery connector CN16 Right speaker connector SW1 Reset Switch SW2 Jumper Setting Figure 1-10 Mainboard Jumpers and Connectors (Bot...
Page 32 - System Configurations and Specifications; System Memory Map
System Introduction 1-19 1.6 System Configurations and Specifications 1.6.1 System Memory Map Table 1-8 System Memory Map Address Range Definition Function 000000 -09FFFF 640 KB memory Base memory 0A0000 -0BFFFF 128 KB video RAM Reserved for graphics display buffer 0C0000 -0CBFFF Video BIOS Video BI...
Page 33 - Cascade
1-20 Service Guide Table 1-10 I/O Address Map Address Range Device 060 -06E070 -071080 -08F0A0 -0A10C0 -0DF1F0 -1F73F6 -3F7170 -177376 -377220 -22F240 -24F260 -26F280 -28F278 -27F2E8 -2EF2F8 -2FF300 -301310 -311320 -321330 -321378 -37F388 -38B3BC -3BE3B4, 3B5, 3BA3C0 -3C53C6 -3C93C0 -3CF3D0 -3DF3E8 ...
Page 34 - Description
System Introduction 1-21 1.6.5 GPIO Port Definition Map Table 1-12 GPIO Port Definition Map I GPIO/Signal Pin # I/O Description GPIO Pin Assignment: PIIX4 SUSA# (PX3_SUSA#) W20 O 0: Power down clock generator GPO0 (PX3_DOCKRST#) G4 O 0 : Enable docking reset GPO1 (PX3_HDPON) Y15 O 1: Turn on HDD pow...
Page 35 - GPIO Port Definition Map II; GPIO
1-22 Service Guide Table 1-12 GPIO Port Definition Map I GPIO/Signal Pin # I/O Description GPI1 (DK3_DOCKIRQ#) P19 O 0: Detect Docking IRQ GPI2/REQA# (PX3_OEM0) M1 O OEM detection GPI3/REQB# (SM5_BAYSW) N2 O Detect FDD/CD bay 1: installed, 0: not installed GPI4/REQC# (CF5_FDD/CD#) P3 O Detect FDD or...
Page 37 - PCI Devices Assignment
1-24 Service Guide Table 1-13 GPIO Port Definition Map II GPIO I/O Description P2.0 I NC P2.1 O NC P2.2 (SM5_BAYSW) I Detect FDD/CD bay installed or not P2.3 O NC P2.4 O NC P2.5 O NC P2.6 O NC P2.7 O NC P3.0 (SM5_RXD) I Receiving data from KBC to SMC P3.1 (SM5_TXD) O Transmitting data from SMC to KB...
Page 38 - Device
System Introduction 1-25 Device Device ID Assignment MTXC North Bridge 0 AD11 PIIX4 ISA Bridge 1 AD18 (Function 0) PIIX4 IDE controller 1 AD18 (Function 1) PIIX4 USB controller 1 AD18 (Function 2) PIIX4 PM/SMBUS controller 1 AD18 (Function 3) PCI VGA(NM2160) 2 AD13 PCI Cardbus controller A AD21 PCI ...
Page 40 - System activities; Hard disk
System Introduction 1-27 Table 1-15 PMU Timers List Item Descriptions System activitiesand timerretriggers System activities − Power off either or both FDD and CD-ROM. Tri-state FDD and CD-ROMinterfaces and stop IDE controller clock. Timer retriggers − The I/O access to 3F2, 3F4, 3F5(FDD), 3F7, 376(...
Page 41 - Floppy; Disable the UART1 decode in the 87338 chip.
1-28 Service Guide 3. CD-ROM Reset [pin-U13 of U21(PX3_CDRST#) of PIIX4]. The reset pin is used to assert the hard reset needed for the CD-ROM during power up. The reset pin is asserted beforeCD-ROM power up and is deasserted after CD-ROM power up and before the buffer isenabled. • Floppy The floppy...
Page 42 - Parallel port
System Introduction 1-29 Recovery from power down is the opposite procedure. • SIR (UART) The FIR port is basically UART2. The UART operates off of a 14MHz clock. The IR port has aDA converter. The UART2 disable control circuit is within the 87338 chip. 1. Tri-state the UART2 output pins. 2. Disable...
Page 43 - CPU; C, shut down the system while higher; System; C while trickle charge higher than
1-30 Service Guide • • CPU The CPU clock. The clock to the CPU can be physically stopped. The chip is static, so thecurrent state is retained. During a clock stop state, the CPU is stopped and the internal cacheand external bus signals are inoperative. Therefore, any bus master or DMA activity is ha...
Page 45 - System Memory Specifications
1-32 Service Guide 1.6.9 BIOS Table 1-17 BIOS Specifications Item Specification BIOS programming vendor Acer BIOS version V3.0 BIOS ROM type Intel 28F002, Flash ROM with boot block protection BIOS ROM size 256KB BIOS ROM package type 40-pin TSOP Same BIOS for TFT LCD type Yes Boot from CD-ROM featur...
Page 46 - RAM Size; Video Memory Specification; Memory size
System Introduction 1-33 1.6.10.1 SIMM Memory Combination List Table 1-19 SIMM Memory Combination List RAM Size Bank A Bank B 8MB 8MB 0MB 8MB 0MB 8MB 16MB 8MB 8MB 16MB 16MB 0MB 16MB 0MB 16MB 24MB 8MB 16MB 24MB 16MB 8MB 32MB 16MB 16MB 32MB 32MB 0MB 32MB 0MB 32MB 40MB 8MB 32MB 40MB 32MB 8MB 48MB 16MB ...
Page 48 - PCMCIA Specifications
System Introduction 1-35 1.6.13 Audio Table 1-24 Audio Specifications Item Specification Chipset Neomagic-3097 Audio onboard or optional Built-in Mono or stereo stereo Resolution 16-bit Compatibility Sound Blaster Game, Windows Sound System, Plug&PlayISA 1.0a Music synthesizer 20-voice, 72 opera...
Page 55 - System Block Diagrams; “7100” System Block Diagram; MAIN BOARD; AC Adapter; Touchpad; ” HDD module; System Functional Block Diagram
1-42 Service Guide 1.7 System Block Diagrams 1.7.1 System Functional Block Diagram “7100” System Block Diagram “7100” System Block Diagram MAIN BOARD . Intel Tillamook/Deschutes MMO . PCI IDE . Intel 430TX Core Logic chipset . NS87338 Super I/O controller . 512KB L2 cache memory . 256KB PMU/System/V...
Page 56 - 70T SYSTEM BLOCK DIAGRAM; System Bus Block Diagram
System Introduction 1-43 1.7.2 System Bus Block Diagram 970T SYSTEM BLOCK DIAGRAM 430TX SYSTEM CONTROLLER HOST BUS L2 CACHE 32KX32 MD[0..63] MA[0..13] EDO/SDRAM 2, 4, 8MX64 2 BANKS DIMCLK(60/66MHz) PCI BUS 14.318MHz INTEL CPU CLOCK GEN. IMICS651 HCLK(60/66MHz) PCICLK(30/33MHz) USB(48MHz) IDE CD PIIX...
Page 57 - Environmental Requirements
1-44 Service Guide 1.8 Environmental Requirements Table 1-39 Environmental Requirements Item Specification Temperature Operating (ºC) +5 ~ +35 Non-operating(ºC)(unpacked) -10 ~ +60 Non-operating(ºC)(storage package) -20 ~ +60 Humidity Operating (non-condensing) 20% ~ 80% Non-operating (non-condensin...
Page 58 - Mechanical Specifications
System Introduction 1-45 1.9 Mechanical Specifications Table 1-40 Mechanical Specifications Item Specification Weight (includes battery and FDD) 12.1 TFT SVGA LCD and 12.5mm HDD Adapter 3.3 kgs (7.2 lbs)230 g (0.52 lb) Dimensions round contour main footprint 297~313mm x 233~240mm x 50~53mm11.7” x 9....
Page 59 - Major Chips Description; Major Component List; Major Chips List; Component
C h a p t e r 2 C h a p t e r 2 Major Chips Description Major Chips Description 2-1 This chapter discusses the major components. 2.1 Major Component List Table 2-1 Major Chips List Component Vendor Description PIIX4 Intel MMO NM2160 NeoMagic Flat Panel Video Accelerator NMA1 NeoMagic Audio chip 87C5...
Page 60 - PCI to ISA/EIO Bridge
2-2 Service Guide 2.2 Intel PIIX4 PIIX4 is a multi-function PCI device that integrates many system-level functions. PCI to ISA/EIO Bridge PIIX4 is compatible with the PCI Rev 2.1 specification, as well as the IEEE 996 specification for theISA (AT) bus. On PCI, PIIX4 operates as a master for various ...
Page 61 - Enhanced Universal Serial Bus (USB) Controller
Major Chips Description 2-3 The timer/counter block contains three counters that are equivalent in function to those found inone 82C54 programmable interval timer. These three counters are combined to provide the systemtimer function, refresh request, and speaker tone. The 14.31818-MHz oscillator in...
Page 62 - Enhanced Power Management
2-4 Service Guide Enhanced Power Management PIIX4’s power management functions include enhanced clock control, local and global monitoringsupport for 14 individual devices, and various low-power (suspend) states, such as Power-OnSuspend, Suspend-to-DRAM, and Suspend-to-Disk. A hardware-based thermal...
Page 67 - Name; IDSEL
Major Chips Description 2-9 Table 2-2 82371AB Pin Descriptions Name Type Description PCI BUS INTERFACE AD[31:0] I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. Duringthe first clock of a transaction, AD[31:0] contain a physical byte address (32bits). During subsequent clocks, A...
Page 68 - PAR
2-10 Service Guide Table 2-2 82371AB Pin Descriptions Name Type Description IRDY# I/O INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to completethe current data phase of the transaction. It is used in conjunction with TRDY#.A data phase is completed on any clock both IRDY# and TR...
Page 69 - AEN
Major Chips Description 2-11 Table 2-2 82371AB Pin Descriptions Name Type Description TRDY# I/O TARGET READY. TRDY# indicates PIIX4’s ability to complete the current dataphase of the transaction. TRDY# is used in conjunction with IRDY#. A dataphase is completed when both TRDY# and IRDY# are sampled ...
Page 70 - RSTDRV
2-12 Service Guide Table 2-2 82371AB Pin Descriptions Name Type Description IOW# I/O I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave maylatch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4owns the ISA Bus. IOW# is an input when an external ISA master own...
Page 73 - TC
Major Chips Description 2-15 Table 2-2 82371AB Pin Descriptions Name Type Description XOE#/ GPO23 O X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the outputenable of a 74’245 that buffers the X-Bus data, XD[7:0], from the system databus, SD[7:0]. XOE# is asserted anytime a PIIX4 supporte...
Page 74 - INTR
2-16 Service Guide Table 2-2 82371AB Pin Descriptions Name Type Description INTERRUPT CONTROLLER/APIC SIGNALS APICACK#/ GPO12 O APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 afterits internal buffers are flushed in response to the APICREQ# signal. When theI/O APIC samples this...
Page 75 - PCI; OD
Major Chips Description 2-17 Table 2-2 82371AB Pin Descriptions Name Type Description IRQ 12/M I INTERRUPT REQUEST 12. In addition to providing the standard interruptfunction as described in the pin description for IRQ[3:7,9:11,14:15], this pin canalso be programmed to provide the mouse interrupt fu...
Page 77 - PCICLK
Major Chips Description 2-19 Table 2-2 82371AB Pin Descriptions Name Type Description PCICLK I FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLKprovides timing for all transactions on the PCI Bus. All other PCI signals aresampled on the rising edge of PCICLK, and all timing para...
Page 78 - PDDREQ
2-20 Service Guide Table 2-2 82371AB Pin Descriptions Name Type Description PDDACK# O PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE deviceDMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devicesthat a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a DM...
Page 79 - PIORDY
Major Chips Description 2-21 Table 2-2 82371AB Pin Descriptions Name Type Description PIORDY I PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal isdirectly driven by the corresponding IDE device IORDY signal. In an UltraDMA/33 read cycle, this signal is used as STROBE, with the PIIX4 l...
Page 80 - SDDREQ
2-22 Service Guide Table 2-2 82371AB Pin Descriptions Name Type Description SDDREQ I SECONDARY DISK DMA REQUEST. This input signal is directly driven fromthe IDE device DMARQ signal. It is asserted by the IDE device to request a datatransfer, and used in conjunction with the PCI bus master IDE funct...
Page 82 - SMBCLK; SM BUS DATA. Serial data line used to transfer data on SMBus.
2-24 Service Guide Table 2-2 82371AB Pin Descriptions Name Type Description SMBALERT#/ GPI11 I SM BUS ALERT. Input used by System Management Bus logic to generate aninterrupt (IRQ or SMI) or power management resume event when enabled. If thisfunction is not needed, this pin can be used as a general-...
Page 83 - These input signals can be monitored via the
Major Chips Description 2-25 Table 2-2 82371AB Pin Descriptions Name Type Description GENERAL PURPOSE INPUT AND OUTPUT SIGNALS Some of the General Purpose Input and Output signals are multiplexed with other PIIX4 signals. The usageis determined by the system configuration. The default pin usage is s...
Page 85 - CORE GROUND. These pins are the primary ground for PIIX4.
Major Chips Description 2-27 Table 2-2 82371AB Pin Descriptions (continued) Name Type Description CONFIG1 I CONFIGURATION SELECT 1. This input signal is used to select the type of microprocessor being used in the system. If CONFIG1=0, the system containsa Pentium microprocessor. If CONFIG1=1, the sy...
Page 89 - Input and Output to/from NM2160; Pin name
Major Chips Description 2-31 2.3.3 Pin Descriptions Conventions used in the pin description types: I Input into NM2160 O Output from NM2160 I/O Input and Output to/from NM2160 T/S Tri-state during un-driven state S/T/S Before becoming tri-state the pin will be driven inactive O/D Open-drain type out...
Page 90 - Reset This active-low input is used to initialize NM2160
2-32 Service Guide Table 2-3 NM2160 Pin Descriptions Pin name Number I/O Description 72 FRAME# I/O Frame This active-low signal is driven by the bus master toindicate the beginning and duration of an access. NM2160 drivesthis pin in the Bus Master mode 65 PAR I/O Parity Even parity across AD31:0&...
Page 92 - FPVEE; CRT Interface; VSYNC
2-34 Service Guide Table 2-3 NM2160 Pin Descriptions Pin name Number I/O Description 143 FPVEE O Flat Panel VEE This is used to control the bias power to thepanels 108 FPBACK O Flat Panel Backlight This is used to control the backlight powerto the panels or as a General Purpose Output Pin as defined...
Page 93 - REXT
Major Chips Description 2-35 Table 2-3 NM2160 Pin Descriptions Pin name Number I/O Description 98 R O(Analog) RED This DAC analog output drives the CRT interface 97 G O(Analog) GREEN This DAC analog output drives the CRT interface 96 B O(Analog) BLUE This DAC analog output drives the CRT interface 1...
Page 94 - Activity; ZV Interface; HREF; Miscellaneous Pins
2-36 Service Guide Table 2-3 NM2160 Pin Descriptions Pin name Number I/O Description 75 Activity I/O Activity This pin when in input mode and asserted indicates thesystem activity. A high on this pin can be used to reset internaltimers. This pin when in output mode is a General Purpose Outputpin as ...
Page 101 - Philips 87C552 System Management Controller
Major Chips Description 2-43 2.5 Philips 87C552 System Management Controller The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process andis a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the80C51. The 87C552 contains a 8kx...
Page 104 - Mnemonic; Pulse Width Modulation: Output 1
2-46 Service Guide 2.5.4 Pin Descriptions Table 2-5 87C552 Pin Descriptions Mnemonic Pin No. Type Name And Function V DD 2 I Digital Power Supply: +5V power supply pin during normal operation,idle and power-down mode. STADC 3 I Start ADC Operation: Input starting analog to digital conversion (ADCope...
Page 110 - Pin
2-52 Service Guide 2.6.4 Pin Description Table 2-6 NS87338VJG Pin Descriptions Pin No. I/O Description A15-A0 67, 64,62-60,29, 19-28 I Address. These address lines from the microprocessor determinewhich internal register is accessed. A0-A15 are don't cares duringDMA transfer. /ACK 83 I Parallel Port...
Page 113 - IDLE; Index. This input signals the beginning of a FDD track.; IORCHDY
Major Chips Description 2-55 Table 2-6 NS87338VJG Pin Descriptions Pin No. I/O Description /HDSEL(Normal Mode) 32 O FDC Head Select. This output determines which side of the FDD isaccessed. Active selects side 1, inactive selects side 0. /HDSEL(PPM Mode) 77 O FDC Head Select. This pin offers an addi...
Page 114 - IRTX; Read. Active low input to signal a data read by the microprocessor.
2-56 Service Guide Table 2-6 NS87338VJG Pin Descriptions Pin No. I/O Description IRTX 63 O Infrared Transmit. Infrared serial data output. Software configurationselects either IrDA or Sharp-IR protocol. This pin is multiplexed with SOUT2/BOUT/CFG0. MR 100 I Master Reset. Active high output that rese...
Page 115 - SLCT
Major Chips Description 2-57 Table 2-6 NS87338VJG Pin Descriptions Pin No. I/O Description /RI1/RI2 68, 60 I UARTs Ring Indicator. When low, this indicates that a telephone ringsignal has been received by the modem. The /RI signal is a modemstatus input whose condition is tested by the CPU by readin...
Page 120 - Pin Name
2-62 Service Guide The following table lists the pin descriptions Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number I/O Power PCI Bus Interface Pins AD[31:0] PCI Bus Address Input / DataInput/Outputs: These pins connect to PCI bussignals AD[31:0]. 4-5, 7-12, 16-20,22-24, 38-43, 45...
Page 122 - PWR
2-64 Service Guide Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number I/O Power SOUT#/INTC#/ISLD Serial Interrupt Output / PCI Bus Interrupt C/ Serial IRQ Load: In PCI Interrupt Signalingmode, this output can be used as an interruptoutput connected to the PCI bus INTC#interrupt lin...
Page 128 - SCLK
2-70 Service Guide Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number I/O Power Power Control and General Interface Pins SPKR_OUTt Speaker Output: This output can be used as adigital output to a speaker to allow a system tosupport PCMCIA card fax/modem/voice andaudio sound output. ...
Page 132 - CN2 connector signals
2-74 Service Guide 2.9 Ambit DC-AC Inverter This notebook uses two kinds of DC-AC inverters: One (T62.088.C) is designed for the 13.3-inchTFT (LG LP133X1) LCD, the other (T62.055.C) for the 12.1-inch TFT (IBM ITSV50D) LCD. 2.9.1 T62.055C 2.9.1.1 Pin Diagram CN2 CN1 T62.055.C 12 2120 3 2 1 CN3 Figure...
Page 135 - BIOS Setup Information
C h a p t e r 3 C h a p t e r 3 BIOS Setup Information BIOS Setup Information 3-1 The computer BIOS setup utility allows you to configure the computer and its hardware settings.The computer comes correctly configured, and you do not need to run the BIOS setup utility to usethe computer. However, you...
Page 136 - About My Computer; About My Computer Parameters
3-2 Service Guide 3.1 About My Computer Selecting About My Computer presents you with two screens of details about the computer and itsperipherals. These screens are for information only; you cannot change the settings on thesescreens. The following table tells you what each of the items on the Abou...
Page 137 - System Configuration; Press
BIOS Setup Information 3-3 3.2 System Configuration Selecting System Configuration presents a Basic System Configuration screen, where you canchange several items in your computer’s configuration. Press ↑ or ↓ to move from one item to another, and ← or → to change settings. Press F1 to get help on a...
Page 139 - Advanced System Configuration; The default
BIOS Setup Information 3-5 3.3 Advanced System Configuration For advanced users, the System Configuration menu item contains two hidden pages that allowyou to view and configure more technical aspects of the computer. Caution: The computer is already tuned for optimumperformance and you should not n...
Page 142 - Power Saving Options; reopen the display or press any key.; Suspend to Disk on Critical Battery
3-8 Service Guide 3.4 Power Saving Options Selecting Power Saving Options on the BIOS Utility main screen presents a screen that allows youto adjust several power-saving settings. 3.4.1 When Lid is Closed The computer’s lid switch acts as its power switch: opening the display wakes up the computer,c...
Page 145 - Setting; Warning! Contact your dealer to upgrade your BIOS.
BIOS Setup Information 3-11 3.5.2 Diskette Drive Access Control This parameter allows you to control the read and write functions of the floppy drive. The availableoptions. are: Normal, Write Protect, and Disabled. The default is Normal. With this parameter set to Normal, the floppy drive functions ...
Page 146 - Reset To Default Settings
3-12 Service Guide 3.6 Reset To Default Settings When you select the Reset To Default Settings from the BIOS Utility main screen, a dialog boxappears asking you to confirm that you want to reset all settings to their factory defaults.
Page 147 - Disassembly and Unit Replacement; General Information
C h a p t e r 4 C h a p t e r 4 Disassembly and Unit Replacement Disassembly and Unit Replacement 4-1 This chapter contains step-by-step procedures on how to disassemble the notebook computer formaintenance and troubleshooting. To disassemble the computer, you need the following tools: • Wrist groun...
Page 150 - Service Item
4-4 Service Guide Connectors mentioned in the following procedures are assumed tobe no-lock connectors unless specified otherwise. 4.1.3 Disassembly Sequence The disassembly procedure described in this manual is divided into eight major sections: • Section 4.2: Removing the module • Section 4.3: Rep...
Page 152 - Removing the Module; Slide out and hold the module release button.
4-6 Service Guide 4.2 Removing the Module If you are going to disassemble the unit, it is advisable to remove the module first beforeproceeding. Follow these steps to remove the module: 1. Slide out and hold the module release button. 2. Press the module release latch and slide out the module. Figur...
Page 153 - Replacing the Hard Disk Drive; Turn the computer over to access the base.
Disassembly and Unit Replacement 4-7 4.3 Replacing the Hard Disk Drive Follow these steps: 1. Turn the computer over to access the base. 2. Remove the two screws from the hard disk drive bay cover and remove the cover. Figure 4-5 Removing the Hard Disk Drive Bay Cover 3. Lift up (1), then pull out t...
Page 156 - Removing the Keyboard; Follow these steps to remove the keyboard:
4-10 Service Guide 4.5 Removing the Keyboard Follow these steps to remove the keyboard: 1. Slide out the two display hinge covers on both sides of the notebook. Figure 4-9 Removing the Display Hinge Covers 2. Pull out (first from the edges) and remove the center hinge cover. Figure 4-10 Removing the...
Page 158 - Replacing the CPU; Follow these steps to remove the CPU module.
4-12 Service Guide 4.6 Replacing the CPU Follow these steps to remove the CPU module. 1. Remove six screws that secure the CPU heat sink to the chassis. Figure 4-13 Removing the CPU Heat Sink 2. Remove one screw and pull up the CPU module. (CN8, CN12) When inserting a CPU module, take note of the fe...
Page 159 - Removing the Display; Follow these steps to remove the display module.
Disassembly and Unit Replacement 4-13 4.7 Removing the Display Follow these steps to remove the display module. 1. Remove the two screws that secure the display cable to the motherboard. Then unplug thedisplay cable (CN6). Figure 4-15 Unplugging the Display Cable 2. Remove the four display hinge scr...
Page 160 - Disassembling the Housing; Detaching the Lower Housing from the Inside Assembly; Removing the Lower Housing
4-14 Service Guide 4.8 Disassembling the Housing This section discusses how to disassemble the housing, and during its course, includes removingand replacing of certain major components like the hard disk drive, memory and the main board. 4.8.1 Detaching the Lower Housing from the Inside Assembly To...
Page 161 - Detaching the Upper Housing from the Inside Assembly; Remove three screws in the battery bay.
Disassembly and Unit Replacement 4-15 4.8.2 Detaching the Upper Housing from the Inside Assembly Follow these steps: 1. Remove three screws in the battery bay. Figure 4-18 Removing the Battery Bay Screws 2. Turn the unit back over and remove two screws close to the back part of the unit. Then snapou...
Page 165 - Disassembling the Display; Follow these steps to disassemble the display:; or; Removing the Display Bezel Screws
Disassembly and Unit Replacement 4-19 4.9 Disassembling the Display Follow these steps to disassemble the display: 1. Remove the teardrop-shaped LCD bumpers at the top of the display and the long bumper onthe LCD hinge. Figure 4-25 Removing the LCD Bumpers 2. Remove four screws on the display bezel....
Page 168 - Model Number Definition; TravelMate 7100 VU - W X Y Z; Y: Keyboard language version
A p p e n d i x A A p p e n d i x A Model Number Definition Model Number Definition A-1 This appendix shows the model number definition of the notebook. TravelMate 7100 VU - W X Y Z Z: Acer or TI logo T: TI logo Blank: Acer logo or base unit for uniload Y: Keyboard language version 0: Swiss for ANW ...
Page 169 - Exploded View Diagram; System assembly
A p p e n d i x B A p p e n d i x B Exploded View Diagram Exploded View Diagram This appendix includes exploded view diagrams of the notebook. Table B-1 Exploded View Diagram List No. Description B-1 System assembly B-2 12.1-inch LCD Module assembly (Acer) B-3 12.1-inch LCD Module assembly (TI)
Page 173 - Spare Parts List
A p p e n d i x C A p p e n d i x C Spare Parts List Spare Parts List C-1 This appendix lists the spare parts of the notebook computer. Table C-1 Spare Parts List Ref# of exploded diagram Description Acer part no. Comment/location Min. Qty LCD Module for Acer 12 INVERTER T62.055.C 970 19.21030.041 1...
Page 176 - Prices subject to change without notice.
C-4 Service Guide Table C-1 Spare Parts List Ref# of exploded diagram Description Acer part no. Comment/location Min. Qty HDD 4090MB 2.5" IBM DTLA 56.02834.071 1 G ASSY HDD COVER 970T 60.42A01.001 50 H ASSY HDD DOOR 970T 60.42A02.001 5 Docking ADS-231(TM7100) MINI DOCKING 91.42A27.001 1 SYSTEM B...
Page 177 - BIOS POST Checkpoints; Checkpoint; memory area is tested later.
A p p e n d i x E A p p e n d i x E BIOS POST Checkpoints BIOS POST Checkpoints E-1 This appendix lists the POST checkpoints of the notebook BIOS. Table E-1 POST Checkpoint List Checkpoint Description 04h • Determines if the current booting procedure is from cold boot (press reset button orturn the ...
Page 178 - corresponding initialization program.
E-2 Service Guide Table E-1 POST Checkpoint List Checkpoint Description 23h • Detects whether keyboard u is depressed from system powered-on till POST or not. If yes, set BIOS Setup parameter too default settings; or keep the original settings. 24h • Tests programmable interrupt controller (8259) • ...
