Samsung P8249 - Manual

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S3C8245/P8245/C8249/P8249 MICROCONTROLLER iii Preface The S3C8245/P8245/C8249/P8249 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C8245/P8245/C8249/P8249 microcontroller for application development. It isorganized in two main parts: Part I Pr...

S3C8245/P8245/C8249/P8249 MICROCONTROLLER v Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series Microcontrollers ...............................................................................................................1-1S3C8245/P8245/C8249/P8249 Microcontroller...

S3C8245/P8245/C8249/P8249 MICROCONTROLLER vii Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview .............................................................................................................................................7-1 System Clock Cir...

viii S3C8245/P8245/C8249/P8249 MICROCONTROLLER Table of Contents (Continued) Chapter 11 8-bit Timer A/B 8-Bit Timer A.......................................................................................................................................11-1 Overview .....................................

S3C8245/P8245/C8249/P8249 MICROCONTROLLER ix Table of Contents (Continued) Chapter 15 10-bit Analog-to-Digital Converter Overview .............................................................................................................................................15-1Function Description .......

x S3C8245/P8245/C8249/P8249 MICROCONTROLLER Table of Contents (Concluded ) Chapter 19 Electrical Data Overview .............................................................................................................................................19-1 Chapter 20 Mechanic al Data Overview .........

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xi List of Figures Figure Title Page Number Number 1-1 S3C8245/C8249 Block Diagram ............................................................................1-3 1-2 S3C8245/C8249 Pin Assignment (80-QFP-1420C)...................................................

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xv List of Tables Table Title Page Number Number 1-1 S3C8245/C8249 Pin Descriptions .........................................................................1-5 2-1 S3C8249/P8249 Register Type Summary ............................................................

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Using the Page Pointer for RAM clear (Page 0, Page1) .......................................................................2-5Setting the Register Pointers ........................

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xix List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A/D Converter Control Register .............................................................................4-5 BTCON Basic Timer Control Register .......................

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with Carry ....................................................................................................6-14 ADD Add ........................................

S3C8245/P8245/C8249/P8249 PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range ofintegrated peripherals, and various mask-programmable ROM sizes. Among the major CPU feature...

PRODUCT OVERVIEW S3C8245/P8245/C8249/P8249 1-2 FEATURES Memory • ROM: 32K-byte (S3C8249/P8249) • ROM: 16K-byte (S3C8245/P8245) • RAM: 1056-Byte (S3C8249/P8249) • RAM: 544-Byte (S3C8245/P8245) • Data memory mapped I/O Oscillation Sources • Crystal, ceramic, RC (main) • Crystal for subsystem clock • M...

S3C8245/P8245/C8249/P8249 PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM 544/1056 Byte Register File OSC/ nRESET Basic Timer Watch Timer I/O Port and Interrupt Control 16/32-Kbyte ROM SAM88 RC CPU 8-Bit Timer/ Counter B 16-Bit Timer/ Counter 0 16-Bit Timer/ Counter 1 I/O Port 0 I/O Port 1 A/D Converter I/O Port...

PRODUCT OVERVIEW S3C8245/P8245/C8249/P8249 1-4 PIN ASSIGNMENT SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG26/P5.2SEG27/P5.3SEG28/P5.4SEG29/P5.5SEG30/P5.6SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3....

PRODUCT OVERVIEW S3C8245/P8245/C8249/P8249 1-6 PIN DESCRIPTIONS Table 1-1. S3C8245/C8249 Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin Numbers ( n o t e ) Share Pins P0.0–P0.7 I/O I/O port with bit programmable pins;Schmitt trigger input or output modeselected by software; sof...

PRODUCT OVERVIEW S3C8245/P8245/C8249/P8249 1-8 PIN CIRCUITS In V DD Figure 1-4. Pin Circuit Type B (nRESET) P-Channel N-Channel V D D Out Output Disable Data Figure 1-5. Pin Circuit Type C P-Channel I/O Output Disable Data Circuit Type C Pull-up Enable V DD Figure 1-6. Pin Circuit Type D-2 (P3) I/O ...

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2-1 2 ADDRESS SPACES OVERVIEW The S3C8245/C8249 microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses a...

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2-3 REGISTER ARCHITECTURE In the S3C8245/C8249 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2 . The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1),...

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2-11 REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes fulladvantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operan...

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2-18 SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSHand POP instructions are used to control system stack operations. The S3C8245/C8249 architecture supports stackoperations ...

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2-20 NOTES

S3C8245/P8245/C8249/P8249 ADDRESSING MODES 3-1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructionsindicate the operation to be performed and the data to be operated on. Addressing mode is the method used todeter...

ADDRESSING MODES S3C8245/P8245/C8249/P8249 3-4 INDIRECT REGISTER ADDRESSING MODE (C ontinued) dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program M...

ADDRESSING MODES S3C8245/P8245/C8249/P8249 3-6 INDIRECT REGISTER ADDRESSING MODE (C oncluded) dst OPCODE 4-bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access Program Memory Regist...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-1 4 CONTROL REGISTERS OVERVIEW In this chapter, detailed descriptions of the S3C8245/C8249 control registers are presented in an easy-to-readformat. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1illustra...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-4 FLAGS - System Flags Register .7 Carry Flag (C) .6 Zero Flag (Z) .5 Bit Identifier nRESET Value Read/Write Bit Addressing Mode R = Read-onlyW = Write-onlyR/W = Read/write'-' = Not used Type of addressingthat must be used toaddress the bit(1-bit, 4-bit,...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-5 ADCON — A/D Converter Control Register F7H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used for the S3C8245/C8249 .6–.4 A/...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-6 BTCON — Basic Timer Control Register D3H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for ...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-7 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write – – – R/W R/W – – – Addressing Mode Register addressing mode only .7–.5 Not used for the S3C8245/C8249 .4–.3 CPU Clock (Syste...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-8 EMT — External Memory Timing Register FEH Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 – – – – – – – Read/Write – – – – – – – – Addressing Mode Register addressing mode only .7–.0 Not used for the S3C8245/C8249

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-9 FLAGS — System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .7 Carry Flag (C) 0 Operation does not generate a carry or...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-10 IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enable Bit; External Inter...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-11 INTPND — Interrupt Pending Register D2H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value – – – – – 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .7–.3 Not used for the S3C8245/C8249 .2 Timer 1 Overflow In...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-12 IPH — Instruction Pointer (High Byte) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) ...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-13 IPR — Interrupt Priority Register FFH Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for I...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-14 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.4–0.7...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-15 LCON — LCD Control Register D0H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W – R/W R/W R/W Addressing Mode Register addressing mode only .7 LCD Output Segment and Pin Configuration Bits 0 P5.4–P5....

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-17 LMOD — LCD Mode Control Register D1H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Not used for the S3C8245/C8249 .5–.4 LCD Clock (LC...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-18 OSCCON — Oscillator Control Register F3H Set 1 ,Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write – – – R/W R/W R/W – R/W Addressing Mode Register addressing mode only .7–.5 Not used for the S3C8245/C8249 .4 Sub-sys...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-21 P0INT — Port 0 Interrupt Control Register E2H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT7) E...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-22 P0PND — Port 0 Interrupt Pending Register E3H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7/INT7 Interrupt Pending Bit...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-24 P1CONH — Port 1 Control Register (High Byte) E4H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.7/SI 0 0 Input mode (...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-25 P1CONL — Port 1 Control Register (Low Byte) E5H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.3 0 0 Input mode 0 1 Ou...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-26 P1PUP — Port 1 Pull-up Control Register F5H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P1.7 Pull-up Resistor Enable Bit ...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-32 P4CONH — Port 4 Control Register (High Byte) ECH Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P4.7/SEG23 Mode Selectio...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-33 P4CONL — Port 4 Control Register (Low Byte) EDH Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P4. 3/SEG19 Mode Selection...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-34 P5CONH — Port 5 Control Register (High Byte) EEH Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.7/SEG31 Mode Selectio...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-35 P5CONL — Port 5 Control Register (Low Byte) EFH Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5. 3/SEG27 Mode Selection...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-36 PP — Register Page Pointer DFH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Destination Register Page Selection Bits 0 0 0 0 De...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-37 RP0 — Register Pointer 0 D6H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 1 1 0 0 0 – – – Read/Write R/W R/W R/W R/W R/W – – – Addressing Mode Register addressing only .7–.3 Register Pointer 0 Address Value Register pointer 0 can independe...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-38 SIOCON — SIO Control Register FOH Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 1 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 SIO Shift Clock Selection Bit 0 Internal c...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-39 SPH — Stack Pointer (High Byte) D8H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (High Byte) The high-byte...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-40 STPCON — Stop Control Register F4H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enab...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-41 SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 – – x x x 0 0 Read/Write R/W – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used, But you must keep "0" .6–.5 Not used for ...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-42 T0CON — Timer 0 Control Register F1H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 – 0 0 0 0 Read/Write R/W R/W R/W – R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 0 Input Clock Selection Bits 0 0...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-43 T1CON — Timer 1 Control Register FBH Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 1 Input Clock Selection Bits 0 ...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-44 TACON — Timer A Control Register EDH Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Timer A Input Clock Selection Bits 0...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-45 TBCON — Timer B Control Register ECH Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Timer B Input Clock Selection Bits 0 ...

CONTROL REGISTERS S3C8245/P8245/C8249/P8249 4-46 VLDCON — Voltage Level Detector Control Register F6H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write – – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Not used for the S3C8245/C...

S3C8245/P8245/C8249/P8249 CONTROL REGISTER 4-47 WTCON — Watch Timer Control Register FAH Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Watch Timer Clock Selection Bit 0 Ma...

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPUrecognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-1 6 INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of theinst...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to thebit 7 position (MSB). After rotate and shift operations, it contains the last value shifted ...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-14 ADC — Add with carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand andthe sum is stored in the destination. The contents of the source are unaffected. Two's-c...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination.The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in thedestination. The AND operation results in a "1" bit being stored whenever the corresponding...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of thedestination (or source). The resultant...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both op...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bitsin the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared ...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-20 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bits inthe destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc ...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bits inthe destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst ...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of thedestination (or the source). The resulting bit va...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added tothe program counter and con...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added tothe program counter and cont...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) ofthe destination (or source). The resu...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-26 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The current contents of the program counter are pushed onto the top of the stack. The programcounter value used is the address of the first instruction followi...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero;if C = "0", the value of the carry flag is changed to logic one. Flags: C: Compleme...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-28 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R 4 B1 IR Examples: Given: Register 00H = 4FH, register 01H...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement); all "1s" arechanged to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; clear...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-30 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriateflags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a &#...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0",the relative address...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-32 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not"0", the relative...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtractionoperation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates theoperat...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-35 DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if ari...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand followingthat location are treated as a single 16-bit value that is decremented by one. Flags: C: Unaffected...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling allinterrupt processing. Interrupt requests will continue to set their respective interrupt pending bits...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) isstored in the lower half of the destination. The...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are notlogic zero after decrementing, the relative address is adde...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts tobe serviced as they occur (assuming they have highest priority). If an interrupt's pending bit w...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of theinstruction pointer are pushed to the stack. The program counter (PC) value is then...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is poppedand loaded into the instruction pointer. The program memory word that is pointed to by t...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-43 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idlemode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Form...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that locationare treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected. Z: Set if ...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-46 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register a...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to the destination address if thecondition specified by the condition code (cc) is true; otherwise, th...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-48 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to theprogram counter and control passes to the statement whose address is now in the progr...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-49 LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src dst | opc src 2 4 rC r IM 4 r8 ...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of thesource is loaded into the specified bit of the destination. No o...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-52 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. Thesource values are unaffected. LDC refers to program memory and LDE to data memory. Theassemble...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-55 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memoryto the register file. The address of the memory location is specif...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-56 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memoryto the register file. The address of the memory location is specif...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-57 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory from theregister file. The address of the memory location is specified ...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-58 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory from theregister file. The address of the memory location is specified ...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-59 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source areunaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-60 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand(8 bits) and the product (16 bits) is stored in the register pair specified by the d...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-61 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memoryword that is pointed to by the instruction pointer is loaded into the program counter. The instructionpointer i...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-62 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs areexecuted in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycl...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-63 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in thedestination. The contents of the source are unaffected. The OR operation results in a "1" bei...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-64 POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. Thestack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Cycles Opcode...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-65 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register filelocation addressed by the user stack pointer are loaded into the...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-66 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of theregister file location addressed by the user stack pointer are loaded int...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-67 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)into the location addressed by the decremented stack pointer. The operation then adds the newv...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-68 PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements theuser stack pointer and loads the contents of the source into the r...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-69 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the userstack pointer and then loads the contents of the source into the reg...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-70 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 CF Example: Given: C = &#...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-71 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of aprocedure entered by a CALL instruction. The contents of the location addressed by the stackpointer are ...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-72 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 ismoved to the bit zero (LSB) position and also replace...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-73 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initialvalue of bit 7 replaces the carry flag (C...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-74 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n ) ← dst (n + 1), n = 0–6 The contents of the destinat ion operand are rotated right one bit position. The initial value of bit zero(LSB) is moved to bit 7 (MSB) and also replaces t...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-75 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. Theinitial value of bit zero (LSB) replaces the car...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-76 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format:...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-77 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is notimplemented in some S3C8-s...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-78 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destinationoperand and the result is stored in the destination. The contents of the source ar...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-79 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets t...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-80 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (theLSB) replaces the carry flag. The value of b...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-81 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7), R...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-82 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes themicrocontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,peripheral registers, and I/O port control...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-83 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in thedestination. The contents of the source are unaffected. Subtraction is performed by adding the two'scomple...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-84 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 7 0 4 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-85 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to betested are specified by setting a "1" bit in the corresponding positio...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-86 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to betested are specified by setting a "1" bit in the corresponding position of the source op...

S3C8245/P8245/C8249/P8249 INSTRUCTION SET 6-87 WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt oc curs, except that DMA transfers can still takeplace during this wait state. The WFI status can be released by an internal interrupt, including a fastinterrupt . ...

INSTRUCTION SET S3C8245/P8245/C8249/P8249 6-88 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is storedin the destination. The exclusive-OR operation results in a "1" bit being sto...

S3C8245/P8245/C8249/P8249 CLOCK CIRCUIT 7-1 7 CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C8245/C8249 by an external crystal can range from 1 MHz to 10 MHz. Themaximum CPU clock frequency is 10 MHz. The X IN and X OUT pins connect the external oscillator or clock source to the on-...

S3C8245/P8245/C8249/P8249 n RESET and POWER-DOWN 8-1 8 nRESET and POWER-DOWN SYSTEM nRESET OVERVIEW During a power-on reset, the voltage at V DD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a schmitt trigger circuit where it is then synchronized wi...

S3C8245/P8245/C8249/P8249 BASIC TIMER 10-1 10 BASIC TIMER OVERVIEW S3C8245/C8249 has an 8-bit basic timer . BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or — To signal the ...

S3C8245/P8245/C8249/P8249 WATCH TIMER 13-1 13 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock.To start watch timer operation, set bit1 and bit 6 of the watch timer mode register, WTCON.1and 6, to “1”. After thewatch tim...

S3C8245/P8245/C8249/P8249 LCD CONTROLLER/DRIVER 14-1 14 LCD CONTROLLER/DRIVER OVERVIEW The S3C8245/C8249 micro-controller can directly drive an up-to-16-digit (32-segment) LCD panel. The LCD modulehas the following components: — LCD controller/driver — Display RAM (00H–0FH) for storing display data ...

S3C8245/P8245/C8249/P8249 VOLTAGE BOOSTER 17-1 17 VOLTAGE BOOSTER OVERVIEW This voltage booster works for the power control of LCD : generates 3 × V R (V LC2 ), 2 × V R (V LC1 ), 1 × V R (V LC0 ). This voltage booster allows low voltage operation of LCD display with high quality. This voltage booste...

S3C8245/P8245/C8249/P8249 VOLTAGE LEVEL DETECTOR 18-1 18 VOLTAGE LEVEL DETECTOR OVERVIEW The S3C8245/C8249 micro-controller has a built-in VLD (Voltage Level Detector) circuit which allows detection ofpower voltage drop or external input level through software. Turning the VLD operation on and off c...

S3C8245/P8245/C8249/P8249 ELECTRICAL DATA 19-1 19 ELECTRICAL DATA OVERVIEW In this chapter, S3C8245/C8249 electrical characteristics are presented in tables and graphs.The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characte...

S3C8245/P8245/C8249/P8249 MECHANICAL DATA 20-1 20 MECHANICAL DATA OVERVIEW The S3C8245/C8249 microcontroller is currently available in 80-pin-QFP/TQFP package. 80-QFP-1420C #80 20.00 ± 0.20 23.90 ± 0.30 14.00 ± 0.20 17.90 ± 0.30 #1 0.80 0.35 + 0.10 NOTE : Dimensions are in millimeters. 0.15 MAX (0.8...

S3C8245/P8245/C8249/P8249 DEVELOPMENT TOOLS 22-1 22 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turnkey form. The developmentsupport system is configured with a host system, debugging tools, and support software. For the host system, anystanda...