Page 2 - SECTION 1: INTRODUCTION
USER’S GUIDE 050396 1/173 2 SECTION 1: INTRODUCTION The Secure Microcontroller family is a line of8051–compatible devices that utilize nonvolatile RAM(NV RAM) rather than ROM for program storage. Theuse of NV RAM allows the design of a “soft” microcon-troller which provides a number of unique featur...
Page 3 - LARGE NONVOLATILE MEMORY
USER’S GUIDE 050396 2/173 3 LARGE NONVOLATILE MEMORY Soft Microprocessor chips provide nonvolatile memorycontrol for standard CMOS SRAM. Modules combinethe microprocessor chip with memory and lithium back-up. This includes conditionally write protected chip en-ables and a power supply output that sw...
Page 4 - PRODUCT DESCRIPTION
USER’S GUIDE 050396 3/173 4 PRODUCT DESCRIPTION All devices listed below have the standard 8051 familyfeature set listed once here for convenience, but not re-peated for each device. • 8051–compatible instruction set • Addresses 64K program and 64K data memory • Four 8–bit pseudo–bidirectional I/O p...
Page 5 - DS5002FP Secure Microprocessor Chip; Security is active at all times; DS2252T Secure Microcontroller Module
USER’S GUIDE 050396 4/173 5 DS2251T 128K Soft Microcontroller Module The DS2251T is a SIMM based on the DS5001. It pro-vides up to 128K bytes of on–board NV RAM and hasthe Byte–wide bus available at the connector. This isused with the decoded peripheral enables for memorymapped peripherals such as a...
Page 6 - SECTION 2: SELECTION GUIDE
USER’S GUIDE 050396 5/173 6 SECTION 2: SELECTION GUIDE The following configurations are available. Speeds arerated maximums, but all members of the Secure Micro- controller family are fully static and can be run as slowas desired. CHIP DESCRIPTION MAXIMUM SPEED PART NUMBER DS5000FP–16 Soft Microproc...
Page 7 - Introduction
USER’S GUIDE 050396 6/173 7 SECTION 3: SECURE MICROCONTROLLERARCHITECTURE Introduction The Secure Microcontroller family is based on an 8051compatible core with a memory interface and I/O logicbuild around it. Many functions are identical to standard8051s and are documented here for completeness. In...
Page 8 - SECURE MICROCONTROLLER ARCHITECTURAL BLOCK DIAGRAM Figure 3–1
USER’S GUIDE 050396 7/173 8 SECURE MICROCONTROLLER ARCHITECTURAL BLOCK DIAGRAM Figure 3–1 15 8 CE1 CE2 R/W ADDRESS ENCRYPT OR DA T A ENCRYPT OR TIMING AND CONTROL TA MCON SECURITY LOCK LOGIC PCON TIMED ACCESS LOGIC MEMOR Y ALLOCA TIONS CTL. LOGIC NONVOLA TILE CONTROL INTERRUPT CONTROL IP IE INTERNAL...
Page 9 - using a self–contained lithium energy; is
USER’S GUIDE 050396 8/173 9 Parallel I/O Four SFR’s provide access for the four parallel I/O portlatches. These I/O ports are denoted as P0, P1, P2, andP3. A total of 32 bits of parallel I/O is available throughthese I/O ports. However, up to 16 bits are sacrificedwhen the Expanded Bus mode is used ...
Page 10 - Watchdog Timer
USER’S GUIDE 050396 9/173 10 Watchdog Timer When the user’s software is being executed, the Watch-dog Timer can be used to automatically restart the pro-cessor in the event that software control is lost. It is alsoused to generate an oscillator start–up delay to allow theclock frequency to stabilize...
Page 12 - Programmer’s note : with the use of ‘C’ com-; SCRATCHPAD REGISTER MAP Figure 4–2
7FH 2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH 18H 17H 10H 0FH 08H 07H 00H BANK 3 BANK 2 BANK 1 BANK 0 MSB LSB 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49...
Page 13 - Used to select an 8–byte bank of registers to be assigned as R0–R7.; Program and Data Memory
USER’S GUIDE 050396 12/173 13 The 8051 instruction set allows efficient (single cycle)access to variables when using the Working Registers.These are a group of four 8–byte banks of ScratchpadRAM. The active Working Registers are referred to asR0–R7. They reside between location 00h and 1Fh, de-pendi...
Page 14 - DS5000 Series Memory Organization; IMPORTANT APPLICATION NOTE
USER’S GUIDE 050396 13/173 14 DS5000 Series Memory Organization As mentioned above, the DS5000 series consists of theDS5000FP chip and the DS5000(T) and DS2250T mod-ules. The programming model discussed in this sectionapplies to all of these parts. The DS5000 series Byte–wide bus has 15 address line...
Page 16 - “Partition Address”:; Partition Address; Set to all 1’s on a No V; Power On Reset or when the Security Lock bit is
USER’S GUIDE 050396 15/173 16 case is to select a Range of 8K, and to choose a Parti-tion of greater than 8K. This will result in the Range asthe limiting factor. Addresses above the Range will auto-matically be deflected to the Expanded bus. No datamemory will be allocated in NV RAM for this config...
Page 17 - PAA
USER’S GUIDE 050396 16/173 17 MCON.3: RA32/8 “Range Address”: Sets the maximum usable address on the Byte–wide bus.RA32/8 = 0 sets Range Address = 1FFFH (8K); RA32/8 = 1 sets Range Ad-dress = 7FFFH (32K) Initialization: Set to a 1 on a No V LI Power On Reset and when the Security Lock bit (SL) is cl...
Page 18 - RANGE; NA; PARTITION; FFFFh
USER’S GUIDE 050396 17/173 18 a Partitionable mode (PM=0), the DS5001 can use upto 64K x 8 SRAM for program and data on its Byte–widebus. It can partition this area into program and datasegments on 4K boundaries. The 64K memory spacewould consist of two 32K x 8 SRAMs. Each is accessedby a separate c...
Page 19 - MSEL
USER’S GUIDE 050396 18/173 19 PARTITIONABLE MEMORY MAP FOR DS5001/DS5002 SERIES Figure 4–5 FFFFh 0000 PROGRAM DATA LEGEND: BYTE–WIDE BUS ACCESS BYTE–WIDE BUS ACCESS PARTITION ADDR. ÏÏ ÏÏ = EXPANDED BUS ACCESS ON PORTS 0 AND 2 BYTE–WIDE ACCESS(NONVOLATILE RAM) = PES=0 64K RANGE ADDRESS MEMORY MEMORY ...
Page 20 - is removed, the device will maintain these chip en-
USER’S GUIDE 050396 19/173 20 Any address that does not fall into the Byte–wide busarea is routed to the Expanded bus of Ports 0 and 2. Thiscould only occur for the first two settings. Note that asingle 128K device is the least expensive in terms ofcomponent cost and size. In this case, all memory a...
Page 21 - PERIPHERAL ENABLES IN THE DATA MEMORY MAP Figure 4–7; ÏÏÏÏÏ
USER’S GUIDE 050396 20/173 21 On occasion, a memory mapped peripheral is neededthat interfaces directly to an 8051 multiplexed bus.When this occurs, MOVX instructions can be forced touse the Expanded bus in any mode with the EXBS bit(RPCTL.5). Setting this bit to a logic one forces all MOVX instruct...
Page 23 - Loading and Reloading Program Memory
USER’S GUIDE 050396 22/173 23 DS5001/DS5002 SERIES RPCTL REGISTER BITS AFFECTING MEMORY Figure 4–9 RNR ––– EXBS AE IBI DMA RPCON RG0 Bit Description: RPCTL.5: EXBSThe Expanded Bus Select routes data memory access (MOVX) to theExpanded bus formed by ports 0 and 2 when set. Initialization: Cleared aft...
Page 25 - RELOADING PORTIONS OF A DS5000 SERIES DEVICE Figure 4–10
USER’S GUIDE 050396 24/173 25 MOV TA, #0AAh ; TIMED ACCESS MOV TA, #55h ; TIMED ACCESS 2 MOV MCON, #10001010b ; SET PAA BIT . ; USER’S CODE TO LOAD . ; RAM USING MOVX . . MOV TA, #0AAh ; TIMED ACCESS MOV TA, #55h ; TIMED ACCESS 2 MOV MCON, #11001000b ; LOAD NEW PARTITION AND CLEAR PAA BIT RELOADING ...
Page 26 - gives access to the target area of memory.
USER’S GUIDE 050396 25/173 26 SOFT RELOAD OF A DS5001/DS5002When application software decides that it should repro-gram a portion of memory, the software must convertthe target area into data memory. However, a Soft Re-load of a DS5001 series device has minor variationsfrom the DS5000 version. First...
Page 28 - Special Function Registers
USER’S GUIDE 050396 27/173 28 Special Function Registers The Secure Microcontroller uses Special Function Reg-isters (SFRs) to control most functions. In many cases,an SFR will contain 8 bits, each of which control a func-tion or report status on a function. The SFRs reside inregister locations 80–F...
Page 29 - DS5000 SERIES SPECIAL FUNCTION REGISTER MAP Figure 4–12
F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 C AC F0 RS1 RS0 OV P D7 D6 D5 D4 D3 D2 D1 D0 PA3 PA2 PA1 PA0 RA32/8 ECE2 PAA SL RWT PS PT1 PX1 PT0 PX0 BF – – BC BB BA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 EA ES ET1 EX1 ET0 EX0 AF – – AC AB AA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SM0 SM1 SM2 REN TB8 RB8 TI RI 9F 9E...
Page 31 - POWER CONTROL REGISTER; SMOD; WTR
USER’S GUIDE 050396 30/173 31 POWER CONTROL REGISTER Label: PCON Register Address: 087H D7 D6 D5 D4 D3 D2 D1 D0 SMOD POR PFW WTR EPFW EWT STOP IDL Bit Description: PCON.7 SMOD “Double Baud Rate”: When set to a 1, the baud rate is doubled when the serial port is being usedin modes 1, 2, or 3. Initial...
Page 32 - EPFW; STOP
USER’S GUIDE 050396 31/173 32 PCON.3: EPFW “Enable Power Fail Interrupt”: Used to enable or disable the Power Fail Interrupt. When EPFW is set to a 1, it will be enabled; it will be disabled when EPFW is cleared to a 0. Initialization: Cleared to a 0 on any type of reset. Read Access: Can be read no...
Page 33 - TIMER CONTROL REGISTER
USER’S GUIDE 050396 32/173 33 TIMER CONTROL REGISTER Label: TCON Register Address 088H D7 D6 D5 D4 D3 D2 D1 D0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Description: TCON.7: TF1 “Timer 1 Overflow Flag”: Status bit set to 1 when Timer 1 overflows from a previous count value of all1’s. Cleared to 0 when CPU...
Page 34 - TIMER MODE REGISTER; GATE
USER’S GUIDE 050396 33/173 34 TCON.0: IT0 “Interrupt 0 Type Select”: When set to 1, 1–to–0 transitions on INT0 will be used to generate interruptrequests from this pin. When cleared to 0, INT0 is level–activated. Initialization: Cleared to a 0 on any type of reset. TIMER MODE REGISTER Label: TMOD Re...
Page 35 - SERIAL CONTROL REGISTER
USER’S GUIDE 050396 34/173 35 SERIAL CONTROL REGISTER Label:SCON Register Address: 098H D7 D6 D5 D4 D3 D2 D1 D0 SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Description: SCON.7, SCON.6: SM0, SM1 “Mode Select”: Used to select the operational mode of the serial I/O port as follows: SM0 SM1 MODE WORD FUNCTION BAU...
Page 36 - RI; INTERRUPT ENABLE REGISTER; EA
USER’S GUIDE 050396 35/173 36 Initialization: Cleared to a 0 on any type of reset. SCON.0: RI “Receive Interrupt”: Status bit used to signal that a serial data word has been received andloaded into the receive buffer register. In mode 0, it is set at the end of the 8thbit time. It is set at the mid–...
Page 37 - INTERRUPT PRIORITY REGISTER; RWT
USER’S GUIDE 050396 36/173 37 INTERRUPT PRIORITY REGISTER Label:IP Register Address: 0B8H D7 D6 D5 D4 D3 D2 D1 D0 RWT – – PS PT1 PX1 PT0 PX0 Bit Description: IP.7: RWT “Reset Watchdog Timer”: When set to a 1, the Watchdog Timer count will be reset and counting willbegin again. The RWT bit will then ...
Page 38 - Register Address: 0C1H
USER’S GUIDE 050396 37/173 38 DS5001 CRC REGISTER Label: CRC Register Address: 0C1H RNGE3 RNGE2 RNGE1 RNGE0 ––– ––– MDM CRC Bit Description: CRC.7–4 RNGE3–0Determines the range over which a power–up CRC will be performed.Addresses are specified on 4K boundaries. Initialization: Reset to 0 on a No V ...
Page 39 - DS5000 MEMORY CONTROL REGISTER
USER’S GUIDE 050396 38/173 39 DS5000 MEMORY CONTROL REGISTER Label:MCON Register Address: 0C6H D7 D6 D5 D4 D3 D2 D1 D0 PA3 PA2 PA1 PA0 RA32/8 ECE2 PAA SL Bit Description: MCON.7–4: PA3–0 “Partition Address”: Used to select the starting address of Data Memory on the Byte–wide bus.Program space lies b...
Page 40 - Register Address: 0C6H
USER’S GUIDE 050396 39/173 40 Read Access: May be read normally anytime. Write Access: Cannot be modified by the application software; can only be written via theBootstrap Loader. MCON.2: ECE2 “Enable Chip Enable 2”: Used to enable or disable the CE2 signal for the Byte–wide bus datamemory. This bit...
Page 42 - PROGRAM STATUS WORD REGISTER; AC; General–purpose flag bit which can be set or cleared as needed.
USER’S GUIDE 050396 41/173 42 PROGRAM STATUS WORD REGISTER Label:PSW Register Address: 0D0H D7 D6 D5 D4 D3 D2 D1 D0 C AC F0 RS1 RS0 OV P All of the bits in PSW except parity are read/write and are cleared to 0 on any type of reset. The Parity bit is read onlyand is cleared to 0 on any type of reset....
Page 43 - Register Address: 0D8H
USER’S GUIDE 050396 42/173 43 DS5001/DS5002 RPC CONTROL REGISTER Label: RPCTL Register Address: 0D8H RNR ––– EXBS AE IBI DMA RPCON RG0 Bit Description: RPCTL.7 RNRWhen internal hardware sets this read–only bit to a 1, a new value may beread from the random number generator register of the DS5001/DS5...
Page 44 - Register Address: 0DAH
USER’S GUIDE 050396 43/173 44 Read Access: Can be read anytime. Write Access: Can be written when the RPC mode is enabled (RPCON=1). RPCTL.1 RPCONEnable the RPC 8042 I/O protocol. When set, port 0 becomes the data bus,and port 2 becomes the control signals. Initialization: Cleared on all resets. Rea...
Page 45 - Can be read by DS5001/DS5002 and host CPU when in RPC mode.
USER’S GUIDE 050396 44/173 45 Read Access: Can be read by DS5001/DS5002 and host CPU when in RPC mode. Write Access: Can be written by the DS5001/DS5002 when in RPC mode. RPS.1: IBFInput Buffer Full Flag is set following a write by the external host, and iscleared following a read of the DBBIN by th...
Page 46 - INSTRUCTION SET; ADD
USER’S GUIDE 050396 45/173 46 INSTRUCTION SET Introduction The Secure Microcontroller executes an instruction setwhich is object code compatible with the industry stan-dard 8051 microcontroller. As a result, software toolswritten for the 8051 are compatible with the SecureMicrocontroller, including ...
Page 47 - ORL
USER’S GUIDE 050396 46/173 47 The 16–bit DPTR register may be used to access anyData Memory location within the 64K byte space. MOVX @DPTR,A ; Load the Data Memory location ; pointed to by the contents of the ; DPTR register with the contents ; of the Accumulator. Immediate AddressingImmediate Addre...
Page 48 - Program Status Flags
USER’S GUIDE 050396 47/173 48 Program Status Flags All of the Program Status flags are contained in the PSWregister. Instructions which affect the states of the flagsare summarized below. INSTRUCTIONS THAT AFFECT FLAG SETTINGS INSTRUCTION FLAGS C OV AC INSTRUCTION FLAGS C OV AC ADD CLR C 0 ADDC CPL ...
Page 49 - SECTION 5: MEMORY INTERCONNECT
USER’S GUIDE 050396 48/173 49 SECTION 5: MEMORY INTERCONNECT The Secure Microcontroller family is divided betweenchips and modules. This sections illustrates thememory interconnect for the various chips and showsblock diagrams of selected modules. The Soft Micropro-cessor chips are 80–pin QFP packag...
Page 53 - MEMORY INTERCONNECT USING THE 128K SRAM Figure 5–5
USER’S GUIDE 050396 52/173 53 MEMORY INTERCONNECT USING THE 128K SRAM Figure 5–5 ÓÓ ÓÓ ÓÓÓÓÓÓÓÓÓ ÔÔ ÔÔ ÔÔÔÔÔÔÔÔÔ Ô Ô Ç Ç Ç ÇÇÇ Ç Ç Ç Ç Ç Ç ÇÇÇ Ç Ç Ç Ç Ç ÇÇÇ Ç Ç Ç Ç ÇÇÇ ÇÇÇ Ç Ç 13 54 +3v +5v 12 10 74 28 27 20 22 16 14 52 DS5001FP/DS5002FP V CC WE CS1 A16 A15 A14–A0 D7–D0 GND CS2 OE 128K x 8 SRAM V C...
Page 56 - DATA RETENTION; to the lithium cell. V; BATTERY BACKED CIRCUITS; is falling below the reset volt-
USER’S GUIDE 050396 55/173 56 SECTION 6: LITHIUM/BATTERY BACKUP Soft Microcontroller devices are lithium backed for dataretention in the absence of V CC . In the Soft Microcon- troller the state of the microcontroller is also maintained,unlike a conventional processor system using an exter-nal NV RA...
Page 57 - POWER SUPPLY SLEW RATE Figure 6–1; BATTERY ATTACH PROCEDURE
USER’S GUIDE 050396 56/173 57 POWER SUPPLY SLEW RATE Figure 6–1 40 µ s, 130 µ s V CC V CCMIN V LI LITHIUM CURRENT Each time V CC is restored, the lithium backed functions will remain as they were left. A result is that many ofthese values are not altered on a reset condition exceptfor the ‘no batter...
Page 59 - LITHIUM BATTERY USAGE; To clear the Freshness Seal, simply apply V
USER’S GUIDE 050396 58/173 59 LITHIUM BATTERY USAGE In the vast majority of applications, lithium batteries pro-vide a reliable means of backing up data and configura-tion. The voltage varies only slightly over its useful life,so it is difficult to measure capacity. A CR chemistry willbegin life at ...
Page 60 - SECTION 7: POWER MANAGEMENT; Idle Mode; CONTROL/STATUS BITS FOR POWER CONTROL Figure 7–1; POR
USER’S GUIDE 050396 59/173 60 SECTION 7: POWER MANAGEMENT Introduction All Dallas Semiconductor microcontrollers are imple-mented using fully static CMOS circuitry for low powerconsumption. Power consumption is a linear function ofcrystal frequency. Two software initiated modes areavailable for furt...
Page 61 - PIN STATES IN IDLE/STOP MODES Table 7–1
USER’S GUIDE 050396 60/173 61 Write Access: Cannot be written. PCON.3: EPFW “Enable Power Fail Interrupt”: Used to enable or disable the Power Fail Interrupt. When EPFW is set to a 1,it will be enabled; it will be disabled when EPFW is cleared to a 0. Initialization: Cleared to a 0 on any type of re...
Page 62 - Voltage Monitoring Circuitry; . It insures that the proper internal; SECURE MICROCONTROLLER POWER CYCLING TIMING Figure 7–2
USER’S GUIDE 050396 61/173 62 The original contents of those Special Function regis-ters that are initialized by a reset are lost. Voltage Monitoring Circuitry The on–chip voltage monitoring circuitry automaticallyplaces the microprocessor in its Data Retention state inthe absence of V CC . It insur...
Page 63 - Power Fail Interrupt
USER’S GUIDE 050396 62/173 63 Power Fail Interrupt When V CC is stable, program execution proceeds as normal. If V CC should decay from its nominal operating voltage and drop to a level below the V PFW threshold, then the internal PFW status flag (PCON.5) will be set.In addition, a Power Fail Warnin...
Page 64 - SECURE MICROCONTROLLER POWER MANAGEMENT Figure 7–3
USER’S GUIDE 050396 63/173 64 threshold, the Power On Reset cycle will be executed asbefore. As a result, no special processing is required insoftware to accommodate this case. In the case that V CC dips without going below V LI , the PFW flag will be set and a Power Fail Warning interruptwill still...
Page 66 - TIMED ACCESS PROTECTED CONTROL BITS Table 8–1; BIT NAME
USER’S GUIDE 050396 65/173 66 This code allows the reset of the Watchdog Timer: MOV 0C7H,#0AAH ; 1st TA Value MOV 0C7H,#055H ; 2nd TA Value 2 Cycles SETB IP.7 ; Reset Watchdog Timer 1 Cycle The Watchdog Timer bit may have been set using ORL IP, #80H whichtakes two cycles. This code allows the reset ...
Page 67 - level and returned to nor-
USER’S GUIDE 050396 66/173 67 Timed Access provides a statistical protection. It isunlikely that randomly generated states will correctlymatch the sequence and timing required to bypass theTimed Access logic. Presented below is a brief justifica-tion for each bit that is protected by Timed Access. T...
Page 68 - WATCHDOG TIMER Figure 8–2
USER’S GUIDE 050396 67/173 68 During subsequent program execution, the WatchdogTimer can be reset by a Timed Access write operationwhich sets the RWT bit to a 1. This will cause the Watch-dog Timer to begin counting machine cycles again froman initial count of 0. The RWT bit itself is automaticallyc...
Page 69 - WATCHDOG TIMER CONTROL BITS; EWT; CRC MEMORY VERIFICATION
USER’S GUIDE 050396 68/173 69 WATCHDOG TIMER CONTROL BITS Bit Description: PCON.4: WTR “Watchdog Timer Reset” Set to a 1 when a Watchdog Timer timeout occurs. If Watchdog Timer Resetis enabled, this will indicate the cause of the reset. Cleared to 0 immediatelyfollowing a read of the PCON register. ...
Page 71 - CRC CODE EXAMPLE Figure 8–3; This routine tests the CRC–16 circuit in the DS5001FP
USER’S GUIDE 050396 70/173 71 CRC CODE EXAMPLE Figure 8–3 This routine tests the CRC–16 circuit in the DS5001FP crcmsb equ 0C3h crclsb equ 0C2h org 00h ;after reset, CRC regs = 0000 begin: mov p2,crcmsb ;p2=00 read crcmsb register mov p3,crclsb ;p3=00 read crclsb register mov crclsb, #075h ;check cr...
Page 72 - SECTION 9: FIRMWARE SECURITY; FEATURE; SECURITY OVERVIEW
USER’S GUIDE 050396 71/173 72 SECTION 9: FIRMWARE SECURITY One of the most unique features of the Secure Micro-controller is its firmware security. The family far sur-passes the standard offering of ROM based microcon-trollers in keeping system attackers or competitors fromviewing the contents of me...
Page 73 - SECURITY LOCK; or; RAM Memory; and V; ) from a microprocessor chip to eliminate the; Encrypted Memory
USER’S GUIDE 050396 72/173 73 SECURITY LOCK Ordinarily, the easiest way to dump (view) the memorycontents of a Secure Microcontroller is using the Boot-strap Loader. On request, the Loader will transfer thecontents of memory to a host PC. This is prevented bythe Security Lock. The lock is the minima...
Page 74 - DS5000 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 9–1; DS5002 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 9–2
USER’S GUIDE 050396 73/173 74 DS5000 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 9–1 PROGRAM COUNTER DATA POINTER ADDRESS ENCRYPTOR EXTERNAL BYTEWIDE RAM 40–BIT ENCRYPTION KEY DATA ENCRYPTOR SECURITY LOCK BOOTSTRAP LOADER SECURE INTERNAL DATA BUS SECURE INTERNAL ADDRESS BUS ENCRYPTED BYTEWIDE DATA BUS ...
Page 76 - Encryption Algorithm; ) combinations. There is no method to discover the
USER’S GUIDE 050396 75/173 76 Encryption Algorithm The Secure Microcontroller family uses a proprietaryalgorithm to encrypt memory. The DS5000FP andDS5002FP use different encryption algorithms. Theyare the result of improvements made over time in theproprietary encryptor circuits. The original DS500...
Page 77 - Dummy Bus Access
CE1 ALE BA14–0 BD7–0 XXXXh YYYYh QQQQh RRRRh SINGLE CYCLE INSTRUCTION SINGLE CYCLE INSTRUCTION ENCRYPTED MEMORY ACCESS WITH DUMMY FETCHES Either XXXX or YYYY is real but encrpted, the other is pseudo–random.Either QQQQ or RRRR is real but encrypted, the other is pseudo–random.Either Byte1 or Byte2 i...
Page 78 - On–chip Vector RAM; ing power applied to the V; pin. Activation of the SDI; s pulse is required to activate it.; Microprobe/Die Top Coating; s to develop. Reading a byte from register 0CFh
USER’S GUIDE 050396 77/173 78 On–chip Vector RAM A 48–byte RAM area is incorporated inside theDS5000FP and DS5002FP. This area maps to the first48 locations of program memory to store reset andinterrupt vectors. Any other data stored in the first 48locations will be contained in this Vector RAM. The...
Page 79 - Security Summary by Part
USER’S GUIDE 050396 78/173 79 Security Summary by Part The preceding information outlined each of the securityfeatures. Their inclusion in various parts is shown in thetable at the beginning of this chapter. For completeness,the following is a summary description of security fea-tures for each part ...
Page 81 - Change Code
USER’S GUIDE 050396 80/173 81 Change Code Perhaps most importantly, the user should reprogramportions of the Secure Microcontroller that deal with se-curity. For example, if the microprocessor is performingDES, the user can change DES keys. Any security sys-tem can be broken with enough time and res...
Page 82 - SECTION 10: RESET CONDITIONS; RESET STATUS BITS Figure 10–1
USER’S GUIDE 050396 81/173 82 SECTION 10: RESET CONDITIONS Reset Sources The Secure Microcontroller family is designed to pro-vide proper reset operation with a minimum of externalcircuitry. In fact, for may applications, external reset cir-cuitry is not required. The possible sources of reset areas...
Page 83 - SPECIAL FUNCTION REGISTER RESET STATES Table 10–1; REGISTER
USER’S GUIDE 050396 82/173 83 SPECIAL FUNCTION REGISTER RESET STATES Table 10–1 REGISTER LOCATION RESET CONDITION RESET TYPE PC N/A 0000h All ACC E0h 00h All B F0h 00h All PSW D0h 00h All SP 81h 07h All DPTR 83h, 82h 0000h All P0–P3 80h, 90h, A0h, B0h FFh All IP B8h 0XX00000b All IE A8h 0XX00000b Al...
Page 84 - Power On Reset
USER’S GUIDE 050396 83/173 84 Power On Reset The Secure Microcontroller family provides an internalPower On Reset capability which requires no externalcomponents. When voltage is applied to the V CC pin from a power off condition, the device automatically per- forms an internal reset sequence to pre...
Page 85 - No–V; mum level required (V; ) to insure that the nonvolatile; Finally, the Security Lock bit is cleared to 0.; External Reset; cillator to start and for the clock frequency to stabilize.; Watchdog Timer Reset
USER’S GUIDE 050396 84/173 85 No–V LI Power On Reset During a Power On Reset cycle, a test is automaticallyperformed by the internal control circuitry to measurethe voltage of the lithium power source. This test deter-mines whether or not the voltage (V LI ) is above the mini- mum level required (V ...
Page 86 - APPLICATION: RESET ROUTINE EXAMPLE; MEMORY; Memory Map
USER’S GUIDE 050396 85/173 86 APPLICATION: RESET ROUTINE EXAMPLE Like the 8051, Dallas Semiconductor Microcontrollerswill begin execution at address 0000h. This is the ResetVector, followed by other vector locations used for inter-rupts. These are discussed in the section covering inter-rupt operati...
Page 87 - Interrupts
USER’S GUIDE 050396 86/173 87 A code example that initializes the memory map is asfollows. It assumes that the DS5000FP user requires a Partition of 5800h. A DS5001FP using the same codewould use a Partition of B000h. MCON EQU 0C6h Org 00h SJMP Start Org 30hStart : MOV TA, #0AAh ;Timed MOV TA, #55h ...
Page 88 - Timers
USER’S GUIDE 050396 87/173 88 Timers The microprocessor disables timer activity (excludingthe Watchdog) and serial port communication on a re-set. Therefore, each timer must be setup and enabledas part of the reset routine. The serial port mode mustalso be initialized if used. This is covered in det...
Page 89 - SECTION 11: INTERRUPTS
USER’S GUIDE 050396 88/173 89 SECTION 11: INTERRUPTS The Secure Microcontroller family follows the standard8051 convention for interrupts (with one extra) and isfully compatible. An interrupt stops the normal flow ofprocessing and allows software to react to an event withspecial processing. This eve...
Page 90 - External Interrupts; is falling, the Secure; drops below the; voltage threshold, the PFW flag will be set to a; , the flag will again; voltage is
USER’S GUIDE 050396 89/173 90 External Interrupts The two external interrupts are INT0 and INT1. Theycorrespond to P3.2 and P3.3 respectively. These pinsbecome interrupts when the respective interrupt isenabled. Otherwise, they are simply port pins. No otherspecial action is required. Each pin is sa...
Page 92 - INTERRUPT ENABLE CONTROL BITS Figure 11–2; “Enable All Interrupts”:; “Enable Timer 1 Interrupt”:
USER’S GUIDE 050396 91/173 92 INTERRUPT ENABLE CONTROL BITS Figure 11–2 Bit Description: All bits are read/write at any time and are cleared to 0 following any hardware reset. IE.7: EA “Enable All Interrupts”: When set to 1, each interrupt except for PFW may be individually enabled ordisabled by set...
Page 93 - INTERRUPT PRIORITIES; PRIORITY; INTERRUPT PRIORITY CONTROL BITS Figure 11–3; PS
USER’S GUIDE 050396 92/173 93 INTERRUPT PRIORITIES The Secure Microcontroller provides a three priorityinterrupt scheme. Multiple priority levels allow higherpriority sources to interrupt lower priority ISRs. ThePower–fail Warning Interrupt automatically has thehighest priority if enabled. The remai...
Page 94 - INTERRUPT ACKNOWLEDGE; FLAG; INTERRUPT ACKNOWLEDGE SEQUENCE Figure 11–4
USER’S GUIDE 050396 93/173 94 INTERRUPT ACKNOWLEDGE The various interrupt flags are sampled an latched onceevery machine cycle, specifically during clock phaseS5P2 (see CPU timing section) regardless of other in-terrupt related activity. Likewise, the latched states ofthe flags are polled once every...
Page 96 - OVERVIEW; PIN; PORT 0 FUNCTIONAL CIRCUITRY Figure 12–1
EXTERNALADDRESSCONTROL VCC ADDRESS/DATA POWERDOWN PORT 0.n INTERNALDATA BUS WRITEENABLE READENABLE READLATCH/PIN D Q Q USER’S GUIDE 050396 95/173 96 SECTION 12: PARALLEL I/O OVERVIEW The Secure Microcontroller provides four 8–bit bidirec-tional ports for general purpose I/O functions. Each portpin i...
Page 99 - INPUT FUNCTION
USER’S GUIDE 050396 98/173 99 least significant eight bits of address and data. When 1’sare output on Port 2 for address bits during these cycles,strong current drivers are employed. The information inthe Port 2 SFR latch is unchanged during these cycles. Port 0 also employs strong output drivers fo...
Page 100 - READ–MODIFY–WRITE INSTRUCTIONS; MNEMONIC
USER’S GUIDE 050396 99/173 100 READ–MODIFY–WRITE INSTRUCTIONS MNEMONIC DESCRIPTION ANL – Logical AND ORL – Logical OR XRL – Logical Exclusive OR JBC – Branch if Bit Set and Clear (bit) CPL – Complement Bit INC – Increment DEC – Decrement DJNZ – Decrement and Branch if not Zero MOV PX.n,C – Move Carr...
Page 101 - USE OF THE RPC MODE Figure 12–3; USE OF THE RPC MODE Figure 12–4; RD; DATA OUT; RPC INTERRUPTS
USER’S GUIDE 050396 100/173 101 USE OF THE RPC MODE Figure 12–3 P2.3/WR P2.2/RD P2.1/CE PORT 2 P2.0/A0 P2.7/DACK P2.6/DRQ P2.5/IBF P2.4/OBF CONTROL BUS PORT 0 P0.0/D0 DATA BUS P0.1/D1 P0.2/D2 P0.3/D3 P0.4/D4 P0.5/D5 P0.6/D6 P0.7/D7 USE OF THE RPC MODE Figure 12–4 CS RD WR A0 REGISTER 0 0 1 0 DATA OU...
Page 102 - RPC STATUS REGISTER – STATUS (ADDRESS 0DAH) Figure 12–5
USER’S GUIDE 050396 101/173 102 RPC STATUS REGISTER – STATUS (ADDRESS 0DAH) Figure 12–5 ST7 ST6 ST5 ST4 IAO FO IBF OBF Bit Description: RPS.7–4: General purpose status bits that can be written by the DS5001/2 and can beread by the external host. Initialization: Cleared when RPCON=0. Read Access: Can...
Page 103 - RPC PROTOCOL; RPC detects IBF flag via interrupt or polling. Input; DMA OPERATION
USER’S GUIDE 050396 102/173 103 RPC PROTOCOL Data is written to the microprocessor by the host CPUand is placed in the DBBIN. At this time, the IBF flag isset in the RPC Status Register. If enabled by the IBI bitin the RPCTL register, an IBI interrupt will occur. No fur-ther updates of the DBBIN wil...
Page 104 - RPC CONTROL REGISTER – RPCTL (ADDRESS 0D8H) Figure 12–6
USER’S GUIDE 050396 103/173 104 RPC CONTROL REGISTER – RPCTL (ADDRESS 0D8H) Figure 12–6 RNR – EXBS AE IBI DMA RPCON RG0 Bit Description: RPCTL.3: IBIWhen using the RPC mode, an interrupt may be required for the Input BufferFlag. This interrupt is enabled by setting the Input Buffer Interrupt (IBI) b...
Page 105 - SECTION 13: PROGRAMMABLE TIMERS; Cleared to 0 on any reset.
USER’S GUIDE 050396 104/173 105 SECTION 13: PROGRAMMABLE TIMERS FUNCTIONAL DESCRIPTION The Secure Microcontroller incorporates two 16–bit tim-ers called Timer 0 and Timer 1. Both can be used to gen-erate precise time intervals, measure external pulsewidths, or count externally applied pulses. Each p...
Page 106 - Timer 1 Mode Control; TCON REGISTER CONTROL/STATUS BITS Figure 13–2
USER’S GUIDE 050396 105/173 106 TMOD.5, TMOD.4: Timer 1 Mode Control “Mode Select” These bit select the operating mode of the associated timer/counter as fol-lows: M1 M0 0 0 Mode 0: Eight bits with 5–bit prescale 0 1 Mode 1: 16 bits with no prescale 1 0 Mode 2: Eight bits with auto–reload 1 1 Mode 3...
Page 107 - TIMER/COUNTER MODE 0 AND 1 OPERATION Figure 13–3
USER’S GUIDE 050396 106/173 107 Mode 0 Figure 13–3 is a block diagram of a timer/counter oper-ating in Mode 0. Mode 0 configures either program-mable timer for operation as a 13–bit timer/counter. ForTimer 0, selection of Mode 0 configures bit 4 – 0 of TL0as bits 4 – 0 respectively of the 13–bit tim...
Page 108 - TIMER/COUNTER MODE 2 OPERATION Figure 13–4
USER’S GUIDE 050396 107/173 108 Mode 1 Mode 1 for both programmable timers operates in anidentical fashion described for Mode 0, except Mode 1configures a 16–bit timer/counter register. In this case,for Timer 0, TH0 contains the most significant eight bitsof the count value while TL0 holds the least...
Page 109 - signal; and it cannot generate an interrupt on; TIMER 0 MODE 3 OPERATION Figure 13–5
USER’S GUIDE 050396 108/173 109 Mode 3 When Timer 0 is selected for operation in Mode 3, bothTH0 and TL0 are configured independently as an 8–bittimer/counter and as an 8–bit timer. Figure 13–5 illus-trates the function of Timer 0 for Mode 3 operation. For Timer 0 in Mode 3, TL0 becomes an 8–bit tim...
Page 110 - FUNCTION DESCRIPTION; MODE
USER’S GUIDE 050396 109/173 110 SECTION 14: SERIAL I/O FUNCTION DESCRIPTION The Secure Microcontroller, like the 8051, includes apowerful Serial I/O (UART) port capable of both syn-chronous and asynchronous communication. The baudrate and time–base source is fully programmable. Theserial port uses P...
Page 111 - SERIAL PORT CONTROL REGISTER Figure 14–1; REN
USER’S GUIDE 050396 110/173 111 value that generates the required time interval at itsoverflow. This is the most common mode of communi-cating with a PC COM port or similar device. When talk-ing to a PC in Mode 1, the PC would be set to 8–N–1( 8 bits, no parity, 1 stop). Common baud rates are 2400,9...
Page 112 - BAUD RATE GENERATION
USER’S GUIDE 050396 111/173 112 SCON.2: RB8 “Rcv. Bit 8”: Indicates the state of the 9th data bit received while in Mode 2 or 3 operation.If Mode 1 is selected with SM2=0, RB8 is the state of the stop bit which wasreceived. RB8 is not used in Mode 0. Initialization: Cleared to a 0 on any type of res...
Page 113 - TIMER 1 BAUD RATE GENERATION Table 14–2
USER’S GUIDE 050396 112/173 113 In most applications, Timer 1 will be configured as a tim-er which uses the internal clock oscillator frequency asits clock source. The baud rate will then be divided downfrom the time base applied to the XTAL1 and XTAL2pins. In order to provide the most flexibility, ...
Page 115 - MODE 0 BLOCK DIAGRAM AND TIMING Figure 14–2
USER’S GUIDE 050396 114/173 115 MODE 0 BLOCK DIAGRAM AND TIMING Figure 14–2 T1 FLAG OUTPUT SHIFT REGISTER SI S0 LOAD CLK D7 D6 D5 D4 D3 D2 D1 D0 DATA BUS P3.0 LATCH RXD PIN LDSBUF RDSBUF R1 FLAG SERIALINTERRUPT LDSBUF SI0 CONTROL SHIFT RDSBUF RBUFLD RD RCV BUFFER WR SI S0 INPUT SHIFT REGISTER CLK Q7...
Page 116 - ASYNCHRONOUS OPERATION
USER’S GUIDE 050396 115/173 116 ASYNCHRONOUS OPERATION Mode 1, 2, and 3 provide asynchronous, full-duplexcommunication via the Serial I/O Port. The serial dataword is either 10 or 11 bits long, depending on the modeselected. All three modes include one start bit, eightdata bits, and one stop bit. Mo...
Page 118 - SERIAL PORT MODE 1 BLOCK DIAGRAM Figure 14–3
USER’S GUIDE 050396 117/173 118 SERIAL PORT MODE 1 BLOCK DIAGRAM Figure 14–3 MUX TIMER 1 OVERFLOW 1 0 T1 FLAG BIT DETECTOR RXD PIN DIV. BY 16 f CLK /2 TRANSMIT TIMING: WRSBUF SHIFT TXD TI RXD BIT DETECTORSAMPLING SHIFT RI RECEIVE TIMING: D0 D1 D2 D3 D4 D5 D6 D7 STOP D0 D1 D2 D3 D4 D5 D6 D7 STOP XMIT...
Page 119 - MODE2 AND 3 BLOCK DIAGRAM Figure 14–4
USER’S GUIDE 050396 118/173 119 MODE2 AND 3 BLOCK DIAGRAM Figure 14–4 T1 FLAG BIT DETECTOR RXD PIN DIV. BY 16 XMIT SHIFT REGISTER SI S0 LOAD CLK DATA BUS P3.1 LATCH TXD PIN WRSBUF RDSBUF DIVIDE BY 16 R1 FLAG SERIALINTERRUPT WRSBUF SCLK RESET SI0 CONTROL SHIFT RDSBUF LOAD RD RCV DATA BUFFER WR SI S0 ...
Page 120 - SERIAL I/O OPERATING MODES
USER’S GUIDE 050396 119/173 120 APPLICATION: SERIAL PORTINITIALIZATION The serial port can provide either synchronous orasynchronous serial communication. This note demon-strates how to initialize the serial port and includes anexample showing how to perform asynchronous com-munication with a PC COM...
Page 121 - s. Note that the timers count up, so the value; Timer runs at 12 t; Baud Rate
USER’S GUIDE 050396 120/173 121 SM0 = 0 and SM1 = 1 corresponds to the value SCON.7= 0 and SCON.6 = 1. In addition the since the applica-tion requires receiving data, the serial receiver must be enabled. This is done by setting the REN bit at SCON.4to a logic 1. The remaining bits in SCON can be wri...
Page 124 - SECTION 15: CPU TIMING; CLOCK SOURCE INPUT Figure 15–2
XTAL2 XTAL1 GND NC EXT. OSC.SIGNAL USER’S GUIDE 050396 123/173 124 SECTION 15: CPU TIMING OSCILLATOR The Secure Microcontroller provides an on–chip oscilla-tor circuit which may be driven either by using an exter-nal crystal as a time base or from a TTL–compatibleclock signal. The oscillator circuit...
Page 125 - INSTRUCTION TIMING
USER’S GUIDE 050396 124/173 125 INSTRUCTION TIMING The internal clocking signals are divided to produce thenecessary clock phases, state times, and machinecycles which define the sequential execution of instruc-tions. Two clock oscillator periods define one state time.The first clock oscillator puls...
Page 127 - EXPANDED PROGRAM MEMORY FETCH Figure 15–4
USER’S GUIDE 050396 126/173 127 Multiplexed address and data information appear on thePort 0 pins as Program Memory fetches are performedon the Expanded Bus. The falling edge of ALE can beused to signal when the lowest eight bits of valid ad-dress information are being output on Port 0 when sucha fe...
Page 129 - EXPANDED DATA MEMORY TIMING
USER’S GUIDE 050396 128/173 129 EXPANDED DATA MEMORY TIMING The timing for the Expanded Data Memory access cycleis illustrated in Figures 15–5 and 6. Accesses to DataMemory on the Expanded Bus will occur any time that aMOVX instruction is executed that references a DataMemory location that is mapped...
Page 130 - SECTION 16: PROGRAM LOADING; Guaranteed Preserved
USER’S GUIDE 050396 129/173 130 SECTION 16: PROGRAM LOADING INTRODUCTION Program loading is performed to initialize the contentsof NV RAM and to configure the microcontroller. Load-ing is done using a Bootstrap ROM Loader built into allmembers of the Secure Microcontroller family. Whenthis Bootstrap...
Page 131 - EXITING THE LOADER
USER’S GUIDE 050396 130/173 131 The indeterminate area contains various stacks andbuffers used by the loader, and a given byte in this areamay or may not be modified by the loader. As such theuser should not rely on the bootstrap loader preservingany data in this area. In a like manner, because not ...
Page 134 - AUTO–BAUD RATE DETECTION; BAUD RATE
USER’S GUIDE 050396 133/173 134 AUTO–BAUD RATE DETECTION The Serial Bootstrap Loader has the capability of deter-mining which of the six supported baud rate frequenciesis being used for communication and initializing its inter-nal hardware for communication at that frequency.When the Program Load mo...
Page 135 - BOOTSTRAP LOADER INITIALIZATION; COMMAND; COMMAND LINE SYNTAX
USER’S GUIDE 050396 134/173 135 BOOTSTRAP LOADER INITIALIZATION When loader mode is invoked, the device will await anincoming <CR> character at a valid baud rate througheither the serial port (in Serial Program Load mode) orvia the parallel interface (in Parallel Program Loadmode). At this poi...
Page 136 - COMMAND SUMMARIES
USER’S GUIDE 050396 135/173 136 An address will always be the right–most four digits of ahexadecimal number. For example, the following hexa-decimal numbers will result in the following addresses: A → 000AH AB → 00ABH ABC → 0ABCH ABCD → 0ABCDH ABCDE → 0BCDEH The D and F commands allow optional addre...
Page 137 - K byte–1 byte–2 byte–3 byte–4 byte–5; is removed following execution; W byte; byte to the MCON register to configure the Parti-
USER’S GUIDE 050396 136/173 137 F byte [begin–address [end–address]] Fill memory with the value of the specified byte. An op-tional address range may be specified. G Data is read from ports 0, 1, 2 and 3 and is printed as fourpairs of hexadecimal digits. I A CRC–16 is computed from 0 to CRC_RANGE mi...
Page 139 - ERROR MESSAGES; An invalid command letter was entered.
USER’S GUIDE 050396 138/173 139 compared to the computed value for the record, and ifdifferent, the error message E:BADCKS is printed out.Unfortunately, the data bytes for this record will havebeen put to memory already. End of Data records (01)do not check for valid checksums. After a byte is put t...
Page 140 - INTEL HEX FILE FORMAT
USER’S GUIDE 050396 139/173 140 INTEL HEX FILE FORMAT 8051–compatible assemblers produce an absolute out-put file in Intel Hex format. These files are composed of aseries of records. Records in an Intel Hex file have thefollowing format: <Header><Hex Information><Record Terminator>...
Page 141 - PARALLEL PROGRAM LOAD CYCLES Figure 16–4
USER’S GUIDE 050396 140/173 141 PARALLEL PROGRAM LOAD OPERATION The DS5000 Parallel Program Load mode is compatiblewith the Program mode of the 87C51. The hardwareconfiguration used for this mode of operation is shown in Figure 16–3. Dallas Semiconductor recommends theuse of the serial Program Load ...
Page 142 - PARALLEL PROGRAM LOAD MODE
USER’S GUIDE 050396 141/173 142 PARALLEL PROGRAM LOAD MODE Table 16–3 summarizes the selection of the availableParallel Program Load cycles. Figure 16–4 illustratesthe timing associated with these cycles. 8751–COMPATIBLE PROGRAM LOAD CYCLES Table 16–3 MODE RST PSEN PROG EA P2.7 P2.6 P2.5 Program 1 0...
Page 143 - PARALLEL PROGRAMMING CONCERNS
USER’S GUIDE 050396 142/173 143 PARALLEL PROGRAMMING CONCERNS Dallas Semiconductor highly recommends using theserial load mode for programming the DS5000. It hasproven highly reliable and easy to use. In the event thatparallel programming is still desirable to some users,several incompatibilities ha...
Page 144 - SECTION 17: REAL–TIME CLOCK
USER’S GUIDE 050396 143/173 144 SECTION 17: REAL–TIME CLOCK Many user applications require a time–of–day clock.For this reason, all Secure Microcontroller moduleshave real–time clock (RTC) options. These include theDS5000T DIP and the DS2250T, DS2251T, andDS2252T SIMMs. In addition, users of the mon...
Page 146 - PATTERN COMPARISON REGISTER DESCRIPTION Figure 17–2
USER’S GUIDE 050396 145/173 146 PATTERN COMPARISON REGISTER DESCRIPTION Figure 17–2 7 6 5 4 3 2 1 0 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 HEX CODE C5 3A A...
Page 149 - TIME REGISTER EXAMPLES Figure 17–5
USER’S GUIDE 050396 148/173 149 TIME REGISTER EXAMPLES Figure 17–5 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 RANGE (BCD) 00–99 00–59 00–59 01–12 01–07 01–31 01–12 00–99 CLOCK 0 1 2 3 4 5 6 7 REGISTER # 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 ...
Page 150 - DS1283 WATCHDOG TIMEKEEPER CHIP
USER’S GUIDE 050396 149/173 150 DS1283 WATCHDOG TIMEKEEPER CHIP The DS2251T and DS2252T use the DS1283 Byte–wide RTC. This is also the clock of choice for usersdesigning with the microprocessor chips (DS5000FP,DS5001FP, and DS5002FP). This clock gives perma-nently powered time–of–day monitoring. The...
Page 151 - MEMORY MAP
USER’S GUIDE 050396 150/173 151 DS2251T/DS2252T RTC BLOCK DIAGRAM Figure 17–6 ÇÇÇÇÇÇ ÇÇÇÇÇÇ DS5001 CPU DS1283 RTC DS2251T V CCO V CC PE1 CE R/W WE ÑÑÑÑÑÑ ÑÑÑÑÑÑ BA5–0 A5–0 BD7–0 INTB INTA INTP ÇÇÇÇÇÇ ÇÇÇÇÇÇ DS5002 CPU DS1283 RTC DS2252T V CCO V CC PE1 CE R/W WE ÑÑÑÑÑÑ ÑÑÑÑÑÑ BA5–0 A5–0 BD7–0 INTP P3...
Page 153 - DS1283 REAL–TIME CLOCK COMMAND REGISTER Figure 17–8
USER’S GUIDE 050396 152/173 153 The time, calendar, and alarms are controlled by theinformation in these 14 registers. In particular, the Com-mand register controls most functions. This is describedin Figure 17–8. There are two additional bits thatdeserve mention. These reside in the register ataddr...
Page 154 - ALARM MASKBIT OPERATION Figure 17–9; MASK; Alarm once per minute.
USER’S GUIDE 050396 153/173 154 DS1283 RTC INTERRUPTS The DS1283 provides two interrupt functions. They aretime–of–day alarm and a watchdog alarm. The watch-dog alarm is a user programmed periodic interval time–out. It is programmed using registers 0Ch and 0Dh. Thetime–of–day alarm is controlled by ...
Page 164 - SECTION 18: TROUBLESHOOTING; SOURCE; RAM LOSES DATA WHEN POWERED DOWN
USER’S GUIDE 050396 163/173 164 SECTION 18: TROUBLESHOOTING Dallas Semiconductor’s Secure Microcontroller familyhas proven itself to be a reliable and easy–to–use prod-uct. As with any highly–integrated device, however,questions and or problems can arise during its use anddevelopment. Many of these ...
Page 165 - SFR latch set to 1?
USER’S GUIDE 050396 164/173 165 lithium batteries have a very long time constant. Puttingthe device on the shelf for one to two weeks may restoreenough voltage to battery back the memory again. Thelifetime of such a battery will be reduced, however. UNABLE TO INVOKE STOP MODE Unlike the 8051, the ST...
Page 168 - SECTION 19: INSTRUCTION SET DETAILS; TION
USER’S GUIDE 050396 167/173 168 SECTION 19: INSTRUCTION SET DETAILS MNEMONIC INSTRUCTION CODE HEX BYTE CYCLE EXPLANATION MNEMONIC D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 HEX BYTE CYCLE EXPLANATION ADD A, Rn 0 0 1 0 1 n 2 n 1 n 0 28–2F 1 1 (A) = (A) + (Rn) ADD A, direct 0 a 7 0 a 6 1 a 5 0 a 4 0 a 3 1 a 2 0 ...
Page 169 - DA A
USER’S GUIDE 050396 168/173 169 EXPLANATION CYCLE BYTE HEX INSTRUCTION CODE MNEMONIC EXPLANATION CYCLE BYTE HEX D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 MNEMONIC ARITHMETIC OPER. DA A 1 1 0 1 0 1 0 0 D4 1 1 Contents of Accu-mulator are BCD, IF [[(A 3–0 ) > 9] OR [(AC) = 1]] THEN(A 3–0 ) = (A 3–0 ) + 6 AND...
Page 170 - RL A
USER’S GUIDE 050396 169/173 170 EXPLANATION CYCLE BYTE HEX INSTRUCTION CODE MNEMONIC EXPLANATION CYCLE BYTE HEX D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 MNEMONIC RL A 0 0 1 0 0 0 1 1 23 1 1 A 1 A 7 A 6 A 5 A 4 A 3 A 2 A 0 The contents of theaccumulator are ro-tated left by one bit. R A TION RLC A 0 0 1 1 0 0...
Page 171 - NSFER
USER’S GUIDE 050396 170/173 171 EXPLANATION CYCLE BYTE HEX INSTRUCTION CODE MNEMONIC EXPLANATION CYCLE BYTE HEX D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 MNEMONIC MOV direct,#data 0 a 7 d 7 1 a 6 d 6 1 a 5 d 5 1 a 4 d 4 0 a 3 d 3 1 a 2 d 2 0 a 1 d 1 1 a 0 d 0 75 Byte 2Byte 3 3 2 (direct) = #data MOV @Ri, A 1 ...
Page 172 - ULA
USER’S GUIDE 050396 171/173 172 EXPLANATION CYCLE BYTE HEX INSTRUCTION CODE MNEMONIC EXPLANATION CYCLE BYTE HEX D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 MNEMONIC CLR C 1 1 0 0 0 0 1 1 C3 1 1 (C) = 0 CLR bit 1 b 7 1 b 6 0 b 5 0 b 4 0 b 3 0 b 2 1 b 1 0 b 0 C2 Byte 2 2 1 (bit) = 0 SETB C 1 1 0 1 0 0 1 1 D3 1 1 ...
Page 173 - NCHING
USER’S GUIDE 050396 172/173 173 EXPLANATION CYCLE BYTE HEX INSTRUCTION CODE MNEMONIC EXPLANATION CYCLE BYTE HEX D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 MNEMONIC ACALL addr 11 a 10 a 7 a 9 a 6 a 8 a 5 1 a 4 0 a 3 0 a 2 0 a 1 1 a 0 Byte 1Byte 2 2 2 (PC) = (PC) + 2(SP) = (SP) + 1((SP)) = (PC 7–0 ) (SP) = (SP) ...
Page 174 - OGRAM BRANCHING
USER’S GUIDE 050396 173/173 174 EXPLANATION CYCLE BYTE HEX INSTRUCTION CODE MNEMONIC EXPLANATION CYCLE BYTE HEX D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 MNEMONIC JNB bit, rel 0 b 7 r 7 0 b 6 r 6 1 b 5 r 5 1 b 4 r 4 0 b 3 r 3 0 b 2 r 2 0 b 1 r 1 0 b 0 r 0 30 Byte 2Byte 3 3 2 (PC) = (PC) + 3IF (bit) = 0 THEN(P...
