IBM PD78083 - Manual

IBM PD78083

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Table of Contents:

  • Page 2 – NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; unused pin should be connected to V; or GND with a resistor, if it is considered to have a; STATUS BEFORE INITIALIZATION OF MOS DEVICES; devices having reset function.
  • Page 3 – The customer must judge the need for license:
  • Page 5 – Regional Information; • Device availability
  • Page 6 – Major Revision in This Edition; Differences between the; The mark
  • Page 7 – PREFACE
  • Page 8 – Legend
  • Page 9 – Related Documents; versions. However, preliminary versions are not marked as such.; Related documents for
  • Page 12 – PROM programming mode pins (; CHAPTER 3
  • Page 13 – – ii –; CHAPTER 4
  • Page 14 – – iii –; CHAPTER 7
  • Page 15 – – iv –
  • Page 17 – – vi –; Title
  • Page 18 – – vii –
  • Page 19 – – viii –
  • Page 20 – – ix –
  • Page 22 – – xi –
  • Page 23 – – xii –
  • Page 24 – CHAPTER 1 OUTLINE; Note; Program Memory
  • Page 25 – Ordering Information; Under development; Remark; indicates ROM code suffix.
  • Page 26 – Under planning
  • Page 27 – AV; Cautions 1. Be sure to connect IC (Internally Connected) pin to V; pin to V; Pin connection in parentheses is intended for the
  • Page 28 – NC
  • Page 29 – Pin Identifications
  • Page 30 – : Individually connect to V; OE
  • Page 31 – PGM
  • Page 33 – 0 bits timer: 1 channel
  • Page 34 – Pin connection in parentheses is intended for the
  • Page 35 – Outline of Function; Part Number
  • Page 36 – Differences between the; Table 1-1 Differences between the
  • Page 38 – CHAPTER 2 PIN FUNCTION
  • Page 40 – Description of Pin Functions; The following operating modes can be specified bit-wise.
  • Page 42 – to the function the user requires.
  • Page 44 – Connect it directly to the V; with the shortest possible wire in the normal operating mode.; pin because the wiring between those two pins; Connect IC pins to V; IC
  • Page 48 – CHAPTER 3 CPU ARCHITECTURE
  • Page 51 – The internal program memory is mask ROM with a 8192
  • Page 52 – The internal high speed RAM configuration is 256; Caution Do not access addresses where the SFR is not assigned.; registers. This area is between FE00H and FFFFH for the; Operand Address Addressing.
  • Page 56 – PC; Processor Registers; The; Figure 3-7. Program Counter Configuration; RESET input sets the PSW to 02H.; Figure 3-8. Program Status Word Configuration
  • Page 57 – is acknowledged, and set to 1 when the EI instruction is executed.
  • Page 58 – instruction execution.
  • Page 59 – FEFFH; processing and a register for interruption request for each bank.; Figure 3-12. General Register Configuration
  • Page 62 – The value after reset depends on products.
  • Page 63 – Instruction Address Addressing; of the next instruction.
  • Page 64 – instruction branches to an area of addresses 0800H through 0FFFH.; In the case of CALLF !addr11 instruction
  • Page 66 – rp
  • Page 67 – Operand Address Addressing; manipulation during instruction execution.
  • Page 68 – Identifier
  • Page 69 – Operation code; Memory
  • Page 71 – Short Direct Memory
  • Page 72 – SFR
  • Page 74 – can be carried out for all the memory spaces.
  • Page 76 – CHAPTER 4 PORT FUNCTIONS
  • Page 78 – Port Configuration; A port consists of the following hardware:; Item; Dual-functions include external interrupt request input.; the output mode is used, set the interrupt mask flag to 1.
  • Page 79 – Internal bus; Internal bus
  • Page 80 – WR; RD; Selector
  • Page 86 – Port Function Control Registers; The following two types of registers control the ports.
  • Page 89 – RESET input sets this register to 00H.; Caution
  • Page 90 – Port Function Operations; latch contents are output from the pins.; than the manipulated bit.
  • Page 92 – CHAPTER 5 CLOCK GENERATOR; of system clock oscillator is available.; Main system clock oscillator; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 5-1. Clock Generator Configuration
  • Page 93 – Figure 5-1. Block Diagram of Clock Generator
  • Page 94 – Clock Generator Control Register; Figure 5-2. Processor Clock Control Register Format
  • Page 95 – OSMS is set with 8-bit memory manipulation instruction.; Figure 5-3. Oscillation Mode Selection Register Format; must be 2.7 V or higher before the write execution.; : Main system clock oscillation frequency
  • Page 96 – System Clock Oscillator; connected to the X1 and X2 pins.
  • Page 97 – is too long
  • Page 98 – The scaler divides the main system clock oscillator output (f
  • Page 99 – Clock Generator Operations
  • Page 100 – Changing CPU Clock Settings; Time required for CPU clock switchover
  • Page 101 – RESET
  • Page 102 – CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6; The timers incorporated into the; Table 6-1 Timer/Event Counter Types and Functions
  • Page 103 – Values in parentheses when operated at f
  • Page 108 – Figure 6-3. Timer Clock Select Register 5 Format; or f; Values in parentheses when operated at f
  • Page 109 – This register sets count clocks of 8-bit timer register 6.; Figure 6-4. Timer Clock Select Register 6 Format
  • Page 110 – TMC5 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting TMC5.
  • Page 111 – TMC6 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting TMC6.
  • Page 112 – PM10 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 6-7. Port Mode Register 10 Format; Symbol
  • Page 113 – TCEn
  • Page 114 – Figure 6-9. Interval Timer Operation Timings
  • Page 116 – and TCL6) is input. Either the rising or falling edge can be selected.
  • Page 117 – as a square wave output at the desired frequency.
  • Page 118 – Minimum Pulse Width
  • Page 123 – with the count pulse.; Count Pulse; Figure 6-19. External Event Counter Operation Timing
  • Page 126 – CHAPTER 7 WATCHDOG TIMER
  • Page 127 – Interrupt requests are generated at the preset time intervals.; Values in parentheses when operated at f
  • Page 128 – Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Figure 7-1. Watchdog Timer Block Diagram; Control register
  • Page 129 – Watchdog Timer Control Registers; This register sets the watchdog timer count clock.
  • Page 130 – Figure 7-2. Timer Clock Select Register 2 Format
  • Page 131 – WDTM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 7-3. Watchdog Timer Mode Register Format; Thus, once counting starts, it can only be stopped by RESET input.; up to 0.5 % shorter than the time set by timer clock select register 2.
  • Page 132 – Watchdog Timer Operations; to detect any inadvertent program loop.; Runaway Detection Time
  • Page 133 – requests, the INTWDT default has the highest priority.; timer mode is not set unless RESET input is applied.; Interval Time
  • Page 134 – CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT; Follow the procedure below to output clock pulses.
  • Page 135 – Clock Output Control Circuit Configuration; Table 8-1. Clock Output Control Circuit Configuration; Figure 8-2. Clock Output Control Circuit Block Diagram
  • Page 136 – Clock Output Function Control Registers; This register sets PCL output clock.; Figure 8-3. Timer Clock Select Register 0 Format
  • Page 137 – PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 138 – CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT; Follow the procedure below to output the buzzer frequency.; Buzzer Output Control Circuit Configuration; Table 9-1. Buzzer Output Control Circuit Configuration; Figure 9-1. Buzzer Output Control Circuit Block Diagram
  • Page 139 – Buzzer Output Function Control Registers; This register sets the buzzer output frequency.
  • Page 140 – Figure 9-2. Timer Clock Select Register 2 Format
  • Page 142 – CHAPTER 10 A/D CONVERTER
  • Page 143 – Tap Selector
  • Page 145 – • External interrupt mode register 1 (INTM1)
  • Page 146 – Setting prohibited because A/D conversion time is less than 19.1
  • Page 147 – ADIS is set with an 8-bit memory manipulation instruction.; Cautions 1. Set the analog input channel in the following order.
  • Page 148 – This register sets the valid edge for INTP3.; Figure 10-4. External Interrupt Mode Register 1 Format
  • Page 149 – by the tap selector.; , the MSB of the SAR remains set. If it is; • Analog input voltage
  • Page 150 – After RESET input, the value of ADCR is undefined.
  • Page 151 – Input voltage and conversion results
  • Page 152 – The following two ways are available to start A/D conversion.
  • Page 153 – tinues repeatedly until new data is written to ADM.
  • Page 154 – current still flows in the AV; voltage, and therefore; or below AV; Series Resistor String; Output Port
  • Page 155 – Figure 10-10. Analog Input Pin Disposition; pin input impedance
  • Page 156 – for the post-change analog input has not ended.; pin; The AV; Therefore, be sure to apply the same voltage as V; to this pin shown in the following figure even when the; Pin
  • Page 158 – CHAPTER 11 SERIAL INTERFACE CHANNEL 2; Serial interface channel 2 has the following three modes.
  • Page 159 – Serial Interface Channel 2 Configuration; Table 11-1. Serial Interface Channel 2 Configuration
  • Page 160 – Figure 11-1. Serial Interface Channel 2 Block Diagram; See Figure 11-2 for the baud rate generator configuration.
  • Page 161 – Figure 11-2. Baud Rate Generator Block Diagram
  • Page 162 – Writing data to TXS starts the transmit operation.; RXS cannot be directly manipulated by a program.
  • Page 163 – Serial Interface Channel 2 Control Registers; Figure 11-3. Serial Operating Mode Register 2 Format
  • Page 164 – N o t e; Figure 11-4. Asynchronous Serial Interface Mode Register Format
  • Page 165 – Table 11-2. Serial Interface Channel 2 Operating Mode Settings
  • Page 166 – will continue to be generated until RXB is read.
  • Page 167 – Baud Rate Generator Input Clock Selection; BRGC is set with an 8-bit memory manipulation instruction.
  • Page 169 – scaled from the clock input from the ASCK pin.; Table 11-3. Relation between Main System Clock and Baud Rate
  • Page 170 – Frequency of clock input to ASCK pin
  • Page 171 – Serial Interface Channel 2 Operation
  • Page 172 – ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 173 – CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 175 – ASIS is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 176 – -bit counter source clock
  • Page 178 – a signal scaled from the clock input from the ASCK pin.; Table 11-5. Relation between Main System Clock and Baud Rate
  • Page 180 – Data frame is configured from the following bits.; Stop Bit
  • Page 181 – Even parity; The value of the parity bit is as follows:; Number of bits with a value of “1” in transmit data is odd: 0; • Reception
  • Page 183 – is enabled and sampling of the RxD pin input is performed.
  • Page 184 – the error contents, ASIS must be read before reading RXB.
  • Page 185 – Non Generation of an Interrupt Request (INTSR)
  • Page 191 – SRIF; received bit by bit in synchronization with the serial clock.
  • Page 192 – Figure 11-13. Circuit of Switching in Transfer Bit Order; following two conditions are satisfied.
  • Page 194 – CHAPTER 12 INTERRUPT FUNCTION; The following three types of interrupt functions are used.
  • Page 195 – Interrupt Sources and Configuration; highest priority and 9 is the lowest priority.
  • Page 198 – Interrupt Function Control Registers; to interrupt request sources.
  • Page 199 – a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0.; or upon application of RESET input.; Figure 12-2. Interrupt Request Flag Register Format
  • Page 200 – RESET input sets these registers to FFH.; Figure 12-3. Interrupt Mask Flag Register Format
  • Page 201 – Figure 12-4. Priority Specify Flag Register Format
  • Page 202 – These registers set the valid edge for INTP1 to INTP3.
  • Page 203 – processing are mapped.; Figure 12-7. Program Status Word Configuration
  • Page 204 – Interrupt Servicing Operations; table are loaded in the PC and branched.
  • Page 205 – WDTM; Figure 12-9. Non-Maskable Interrupt Request Acknowledge Timing; : Watchdog timer interrupt request flag
  • Page 206 – If a new non-maskable interrupt request is generated during
  • Page 207 – Maskable interrupt request acknowledge operation
  • Page 208 – Start
  • Page 210 – Software interrupt request acknowledge operation; as a multiple interrupt.
  • Page 212 – Example of when a multiple interrupt is generated twice.
  • Page 213 – : Interrupt request acknowledge disabled.
  • Page 215 – The interrupt request reserve timing is shown in Figure 12-15.; Instruction M: Instructions other than instruction N; IF (interrupt request) is not affected by; CPU processing
  • Page 216 – CHAPTER 13 STANDBY FUNCTION; intermittent operations.; request, it enables intermittent operations to be carried out.; execute the STOP instruction.
  • Page 217 – Standby function control register
  • Page 218 – Standby Function Operations; The HALT mode is set by executing the HALT instruction.
  • Page 219 – (a) Clear upon unmasked interrupt request; status is acknowledged.
  • Page 220 – Figure 13-3. HALT Mode Release by RESET Input; : main system clock oscillation frequency; Values in parentheses when operated at f; Clock
  • Page 221 – The STOP mode is set by executing the STOP instruction.; via a pull-up resistor; The operating status in the STOP mode is described below.
  • Page 222 – (a) Release by unmasked interrupt request
  • Page 223 – Figure 13-5. Release by STOP Mode RESET Input
  • Page 224 – CHAPTER 14 RESET FUNCTION; (2) Internal reset by watchdog timer overrun time detection; Cautions 1. For an external reset, input a low level for 10
  • Page 225 – Figure 14-2. Timing of Reset Input by RESET Input
  • Page 227 – Hardware; The values after reset depend on the product.
  • Page 229 – Memory Size Switching Register; Figure 15-1. Memory Size Switching Register Format
  • Page 230 – PROM Programming; address specification function.; Table 15-3. PROM Programming Operating Modes
  • Page 232 – Figure 15-2. Page Program Mode Flowchart; N = Last address of program
  • Page 234 – Figure 15-4. Byte Program Mode Flowchart
  • Page 235 – Cautions 1. Be sure to apply V; before applying V; , and remove it after removing V; to the V; pin may have an adverse affect on device reliability.
  • Page 236 – pin. Unused pins are handled as shown in paragraph,; and V; (3) Input the address of data to be read to pins A0 through A14.; Address Input
  • Page 237 – Screening of One-Time PROM Versions
  • Page 238 – CHAPTER 16 INSTRUCTION SET; This chapter describes each instruction set of the
  • Page 239 – Legends Used in Operation List; Operand identifiers and description methods
  • Page 240 – Description of “operation” column
  • Page 241 – When an area except the internal high-speed RAM area is accessed.; One instruction clock cycle is one cycle of the CPU clock (f; MOV
  • Page 242 – When an area except the internal high-speed RAM area is accessed; ADD
  • Page 243 – SUB
  • Page 244 – OR
  • Page 249 – Instructions Listed by Addressing Type
  • Page 254 – APPENDIX A DEVELOPMENT TOOLS; Figure A-1 shows the configuration of the development tools.
  • Page 255 – Figure A-1. Development Tool Configuration
  • Page 256 – A.1 Language Processing Software
  • Page 257 – A.2 PROM Programming Tools
  • Page 262 – As the OS for IBM PC, the following is supported.; OS; IBM DOSTM; Only English mode is supported.
  • Page 263 – Maintenance product; Notes 1. Maintenance product; trace board with a supervisor board must be done by NEC.
  • Page 264 – I T E M
  • Page 266 – APPENDIX B EMBEDDED SOFTWARE; PD78083 subseries to allow users to
  • Page 267 – and
  • Page 268 – B.2 Fuzzy Inference Development Support System
  • Page 270 – APPENDIX C REGISTER INDEX
  • Page 272 – APPENDIX D REVISION HISTORY; Major revisions by edition and revised chapters are shown below.
  • Page 273 – APPENDIX D REVISION HISTORY; Edition; Figure A-1. Development Tool Configuration has been changed .; The following Development Tools have been added:; APPENDIX B EMBEDDED SOFTWARE
  • Page 274 – Thank you for your kind support.; Document Rating; Name; Facsimile
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PD78081

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PD78081(A)

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PD78082

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PD78082(A)

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PD78P083

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PD78P083(A)

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PD78P081(A2)

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PD78083 SUBSERIES

8-BIT SINGLE-CHIP

MICROCONTROLLER

Document No. U12176EJ2V0UM00 (2nd edition)
(O. D. No. IEU-886)
Date Published May 1997 N
Printed in Japan

©

1992

1994

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Summary

Page 2 - NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; unused pin should be connected to V; or GND with a resistor, if it is considered to have a; STATUS BEFORE INITIALIZATION OF MOS DEVICES; devices having reset function.

NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and qui...

Page 3 - The customer must judge the need for license:

FIP, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, ...

Page 5 - Regional Information; • Device availability

NEC Electronics Inc. (U.S.) Santa Clara, CaliforniaTel: 800-366-9782Fax: 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, GermanyTel: 0211-65 03 02Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UKTel: 01908-691-133Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy...

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