IBM EM78P259N/260N - Manual

IBM EM78P259N/260N

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Table of Contents:

  • Page 2 – Trademark Acknowledgments:; ELAN and ELAN logo; Copyright; All Rights Reserved; Fax
  • Page 3 – Contents; General; Clock; Purpose
  • Page 4 – Sampling
  • Page 5 – APPENDIX; A Package; Trap
  • Page 6 – Specification Revision History; Revision Description; official
  • Page 7 – -Bit Microprocessor with OTP ROM; Product Specification; 3-bit Electrical One Time Programmable; Features
  • Page 8 – Assignment; Block
  • Page 9 – Description; Symbol
  • Page 11 – Function; Registers; Memory; Stack Level 1; Data Memory Configuration
  • Page 14 – RST; The T
  • Page 15 – The upper 2 bits of R5 are fixed to “0” (if EM78P259N is selected).; Bit; are IRC calibration bits in IRC oscillator
  • Page 17 – VREFS CKR1 CKR0 ADRUN ADPD; NOTE; functions; as VREF analog input pin, then CONT Bit 5 “TS”; Operation Mode; Internal RC; High
  • Page 18 – CALI; RB
  • Page 19 – ADIF
  • Page 20 – LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF EXIF
  • Page 21 – Special Purpose Registers; INTE INT TS
  • Page 22 – TCC Rate; Function Description
  • Page 23 – TCCBHE TCCBEN TCCBTS TCCBTE
  • Page 24 – TCCCSE TCCCS2 TCCCS1 TCCCS0
  • Page 25 – TCCCS2; Function
  • Page 27 – WDTE EIS ADIE; EIS is both readable and writable.
  • Page 28 – WDT Rate; The IOCF0 register is both readable and writable
  • Page 29 – TCCBX
  • Page 30 – When TCCBH is Disabled:; In TCCC Up Counter mode:; TCCC Scale
  • Page 31 – FT; HTSE HTS2 HTS1 HTS0 LTSE LTS2 LTS1 LTS0; High time scale enable bit.
  • Page 32 – High time scale bits; High time Rate; Low time scale enable bit.; Low time Rate; The TCC prescaler counter can be read and written to.; TCC; 1 0 - V V V V V V V; a value is written to TCC register
  • Page 33 – and Prescaler; for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT; time-out period is approximately 18ms
  • Page 34 – Ports
  • Page 37 – Next instruction; A reset is initiated by one of the following events; period
  • Page 39 – pin
  • Page 40 – Wake-Up and Interrupt Modes Operation Summary; Signal
  • Page 41 – TCCA Over Flow
  • Page 42 – Register Initial Values after Reset; The following summarizes the initialized values for registers.; Address Name
  • Page 43 – Address
  • Page 46 – Controller Reset Block Diagram; Fig. 6-7 Controller Reset Block Diagram
  • Page 47 – A reset condition is initiated by one of the following events; Reset Type; The following shows the events that may affect the status of T and P.; Event; Port 5 Input Status Change Interrupt
  • Page 48 – for digital noise rejection definition
  • Page 49 – Interrupt sources; Interrupt; STACKACC; RETI; ACC
  • Page 50 – ADC; alog; AISR
  • Page 51 – ADCON
  • Page 53 – s for each K; Operation; The AD Conversion is considered completed as determined by
  • Page 54 – Process/Considerations; Process
  • Page 55 – The contents are the results of ADC
  • Page 56 – are dependent on applications
  • Page 57 – Infrared Remote Control Application/PWM Waveform; HF; Fcarrier
  • Page 58 – start
  • Page 59 – IR disable
  • Page 60 – The following figure shows; Programming the Related Registers; IR/PWM Related Control Registers; low time width
  • Page 64 – Programming the Related Registers; TCCX Related Control Registers; Related TCCX Status/Data Registers; CMP
  • Page 65 – The reference signal must be between Vss and Vdd.; The compared result is stored in the CMPOUT of IOC80.; Fig. 6-15 Comparator Output Configuration
  • Page 66 – Using a Comparator as an Operation Amplifier; IOC80 (Comparator and TCCA; Under Operation Amplifier:; The Comparator is considered completed as determined by
  • Page 67 – Oscillator Modes
  • Page 68 – OSCI; RS; Ceramic Resonators
  • Page 69 – O SC I; O S C I; Vcc; . If the frequency cannot be
  • Page 70 – The RC Oscillator frequencies
  • Page 71 – s before power can be switched ON again.
  • Page 72 – Vdd; Fig. 6-22 Residual Voltage Protection Circuit 1; Vdd; Vdd; Fig. 6-23 Residual Voltage Protection Circuit 2
  • Page 73 – Code Option; Word 0; Instruction period option bit
  • Page 74 – Protect; Others Enable; Word 1; NRHL
  • Page 75 – WDT Time; ms; Word 2; X X X X X X X X X X X X X; Instruction Set
  • Page 76 – The following are the EM78P259N/260N instruction set; Instruction Binary
  • Page 77 – Absolute
  • Page 78 – Electrical
  • Page 79 – Operating supply current; Internal RC Electrical Characteristics (Ta=25
  • Page 80 – AD Converter Characteristics
  • Page 81 – Characteristics
  • Page 82 – eque
  • Page 83 – 0 Timing Diagrams; Instruction 1; AC Test Input/Output Waveform
  • Page 84 – OTP MCU; B Package
  • Page 89 – C Quality Assurance and Reliability; Test Category; C.1 Address Trap Detect
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EM78P259N/260N

8-Bit Microprocessor

with OTP ROM

Product

Specification

D

OC

.

V

ERSION

1.2

ELAN

MICROELECTRONICS

CORP.

May 2007

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Summary

Page 2 - Trademark Acknowledgments:; ELAN and ELAN logo; Copyright; All Rights Reserved; Fax

Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2005~2007 by ELAN Microelectronics Corporation All Rights Reserved Printed in ...

Page 3 - Contents; General; Clock; Purpose

Contents Product Specification (V1.2) 05.18.2007 • iii Contents 1 General Description .................................................................................................. 1 2 Features .........................................................................................................

Page 4 - Sampling

Contents iv • Product Specification (V1.2) 05.18.2007 6.2.13 IOC61 (TCCB Counter) ................................................................................... 23 6.2.14 IOC71 (TCCBH/MSB Counter) ........................................................................24 6.2.15 IOC81 (TCCC Coun...

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