Hitachi HD/3691 - Manual

Rev. 1.0, 07/01, Page v of xxiv Preface The H8/3694 Series is a single-chip microcomputer made up of the high-speed H8/300H CPU asits core, and the peripheral functions required to configure a system. The H8/300H CPU has aninstruction set that is compatible with the H8/300 CPU. Target Users: This ma...

Rev. 1.0, 07/01, page vi of xxiv 5. When the E10T is used, address breaks can be set as available to the user, or for use by the E10T. If address breaks are set as being used by the E10T, the address breakcontrol registers must not be accessed. 6. When the E10T is used, NMI is an input/output pin (o...

Rev. 1.0, 07/01, Page vii of xxiv Contents Section 1 Overview........................................................................................................... ......... 11.1 Overview ..............................................................................................................

Rev. 1.0, 07/01, page viii of xxiv 3.4.1 External Interrupts ............................................................................................... 50 3.4.2 Internal Interrupts ................................................................................................ 51 3.4.3 Interrup...

Rev. 1.0, 07/01, Page ix of xxiv 6.4 Direct Transition ............................................................................................................... 786.4.1 Direct transition from the active mode to the subactive mode ............................. 78 6.4.2 Direct transition from th...

Rev. 1.0, 07/01, Page xi of xxiv 11.3.5 Timer Control Register V1(TCRV1) ................................................................... 143 11.4 Operation........................................................................................................................... 14411.4.1 Timer V...

Rev. 1.0, 07/01, page xii of xxiv Section 14 Serial Communication Interface3 (SCI3) ........................................ 181 14.1 Features ............................................................................................................................. 181 14.2 Input/Output Pins .......

Rev. 1.0, 07/01, Page xiii of xxiv 15.3.6 Slave Address Register (SAR) ............................................................................. 23215.3.7 I 2 C Bus Transmit Data Register (ICDRT)............................................................ 233 15.3.8 I 2 C Bus Receive Data Regist...

Rev. 1.0, 07/01, page xiv of xxiv Section 18 Power Supply Circuit ...................................................................... 273 18.1 When Using the Internal Power Supply Step-Down Circuit ............................................. 273 18.2 When Not Using the Internal Power Supply Ste...

Rev. 1.0, 07/01, Page xv of xxiv Figures of Contents Section 1 OverviewFigure 1-1 Internal Block Diagram of H8/3694 Series of the F-ZTAT TM and Mask-ROM Versions ............................................................................................. 2 Figure 1-2 Pin Arrangement of H8/3694 Seri...

Rev. 1.0, 07/01, page xvi of xxiv Figure 5-5 Typical Connection to Ceramic Oscillator .................................................................. 65Figure 5-6 Example of External Clock Input ................................................................................ 65Figure 5-7 Block Di...

Rev. 1.0, 07/01, Page xvii of xxiv Figure 11-8 Clear Timing by TMRIV Input ............................................................................... 146Figure 11-9 Pulse Output Example ............................................................................................. 147Figure 11-10...

Rev. 1.0, 07/01, page xviii of xxiv Figure 14-3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits).............. 195 Figure 14-4 Sample SCI Initialization Flowchart ...............................................................

Rev. 1.0, 07/01, Page xix of xxiv Figure 15-17 Sample Flowchart for Master Transmit Mode ...................................................... 246Figure 15-18 Sample Flowchart for Master Receive Mode ........................................................ 247Figure 15-19 Sample Flowchart for Slave...

Rev. 1.0, 07/01, page xx of xxiv Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 359Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 360Figure B.13 Por...

Rev. 1.0, 07/01, Page xxi of xxiv Tables of Contents Section 1 OverviewTable 1-1 Pin Functions ......................................................................................................... ....... 4 Section 2 CPUTable 2-1 Operation Notation...................................................

Rev. 1.0, 07/01, page xxii of xxiv Table 7-7 Command Sequence in Programmer Mode ................................................................ 96 Table 7-8 AC Characteristics in Transition to Memory Read Mode (Conditions: V CC = 5.0 V ±0.5 V, V SS = 0 V, T a = 25°C ±5°C).............................

Rev. 1.0, 07/01, Page xxiii of xxiv Section 16 A/D ConverterTable 16-1 Pin Configuration .................................................................................................. 25 5 Table 16-2 Analog Input Channels and Corresponding ADDR Registers .............................. 256 Table ...

Rev. 1.0, 07/01, page 1 of 372 Section 1 Overview 1.1 Overview • High-speed H8/300H central processing unit with an internal 16-bit architecture  Upward-compatible with H8/300 and H8/300H CPUs on an object level  Sixteen 16-bit general registers  62 basic instructions • Various peripheral functio...

Rev. 1.0, 07/01, page 2 of 372 1.2 Internal Block Diagram P10/TMOW P11 P12 P14/ P15/ P16/ P17/ /TRGV P50/ P51/ P52/ P53/ P54/ P55/ / P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 V CC V SS V CL TEST AV CC P20/SCK3 P21/RXD P22/TXD P80/FTCI P81/FTIOA P82/FTIOB P83/FTI...

Rev. 1.0, 07/01, page 3 of 372 1.3 Pin Arrangement NC NC AV CC X2 X1 V CL TEST V SS OSC2 OSC1 V CC P50/ P51/ NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC NC P22/TXD P21/RXD P20/SCK3 P87 P86 P85 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI NC NC ...

Rev. 1.0, 07/01, page 5 of 372 1.4 Pin Functions Table 1-1 Pin Functions Pin No. Type Symbol FP-64EFP-64A FP-48F I/O Functions Powersource V CC 12 10 Input Power supply pin. Connect this pin to thesystem power supply. pins V SS 9 7 Input Ground pin. Connect this pin to the systempower supply(0V). AV...

Rev. 1.0, 07/01, page 6 of 372 Pin No. Type Symbol FP-64EFP-64A FP-48F I/O Functions Timer W FTCI 36 26 Input External event input pin. FTIOA toFTIOD 37 to 40 27 to 30 I/O Output compare output/ input capture input/ PWM output pin I 2 C bus inerface SDA 26 20 I/O IIC data I/O pin. Can directly drive...

Rev. 1.0, 07/01, page 7 of 372 Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upword-compatible withthe H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs  Can execute H8/300 CPUs object programs...

Rev. 1.0, 07/01, page 8 of 372 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area.Figures 2-1 show the memory map. Interrupt vector On-chip ROM (32 kbytes) Not used Not used (1-kbyte work area for flash memory programming) I...

Rev. 1.0, 07/01, page 10 of 372 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2-2. There are two types of registers;general registers and control registers. The control registers are a 24-bit program counter (PC), andan 8-bit condition code register (CCR). PC ...

Rev. 1.0, 07/01, page 11 of 372 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionallyidentical and can be used as both address registers and data registers. When a general register isused as a data register, it can be accessed as a 3...

Rev. 1.0, 07/01, page 12 of 372 SP (ER7) Free area Stack area Figure 2-4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The lengthof all CPU instructions is 2 bytes (one word), so th...

Rev. 1.0, 07/01, page 14 of 372 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,…, 7) of byte operand data. The DAA and DAS decimal-adjust inst...

Rev. 1.0, 07/01, page 16 of 372 2.3.2 Memory Data Formats Figure 2-6 shows the data formats in memory. The H8/300H CPU can access word data andlongword data in memory, however word or longword data must begin at an even address. If anattempt is made to access word or longword data at an odd address,...

Rev. 1.0, 07/01, page 17 of 372 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2-2 to 2-9 summarize the instructions in eachfunctional category. The notation used in tables 2-2 to 2-9 is defined below. Table 2-1 Operation Notation S...

Rev. 1.0, 07/01, page 18 of 372 Table 2-2 Data Transfer Instructions Instruction Size * Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general registerand memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd, Cannot be used in th...

Rev. 1.0, 07/01, page 24 of 372 Table 2-7 Branch Instructions Instruction Size Function Bcc * — Branches to a specified address if a specified condition is true. Thebranching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High...

Rev. 1.0, 07/01, page 25 of 372 Table 2-8 System Control Instructions Instruction Size * Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand cont...

Rev. 1.0, 07/01, page 26 of 372 Table 2-9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0else next; Transfers a data block. Starting ...

Rev. 1.0, 07/01, page 27 of 372 • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carriedout on the operand. The operation field always includes the first four bits of the instruction.Some instructions have two operation fields. • Register Fiel...

Rev. 1.0, 07/01, page 28 of 372 2.5 Addressing Modesand Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in thegenerated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight ...

Rev. 1.0, 07/01, page 29 of 372 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)specified by the register field of the instruction, and the lower 24 bits of the sum the address of amemo...

Rev. 1.0, 07/01, page 30 of 372 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as anoperand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bitmanipulation instructions contain 3-bit immediate data in the instruction code...

Rev. 1.0, 07/01, page 33 of 372 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (ø) or a subclock (ø SUB ). The period from a rising edge of ø or ø SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on ...

Rev. 1.0, 07/01, page 34 of 372 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bitsor 16 bits depending on the register. For description on the data bus width and number ofaccessing states of each register, refer to sec...

Rev. 1.0, 07/01, page 35 of 372 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, andexception-handling state. The program execution state includes active mode and subactive mode.For the program halt state there are a sleep mode, standby mode, an...

Rev. 1.0, 07/01, page 36 of 372 Reset state Program halt state Exception-handling state Program execution state Reset cleared SLEEP instruction executed Reset occurs Interrupt source Reset occurs Interruptsource Exception-handling complete Reset occurs Figure 2-12 State Transitions 2.8 Usage Notes 2...

Rev. 1.0, 07/01, page 39 of 372 • Prior to executing BSET instruction MOV.B #80, R0LMOV.B R0L, @RAM0MOV.B R0L, @PDR5 The PDR5 value (H'80) is written to a work area inmemory (RAM0) as well as to PDR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output ...

Rev. 1.0, 07/01, page 43 of 372 Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is clearedby the RES pin. The chip is also reset whe...

Rev. 1.0, 07/01, page 44 of 372 Table 3-1 Exception Sources and Vector Address Vector Exception Sources Number Vector Address Priority Reset 0 H'0000 to H'0001 High Reserved for system use 1 to 6 H'0002 to H'000D NMI 7 H'000E to H'000F Trap instruction (#0) 8 H'0010 to H'0011 (#1) 9 H'0012 to H'0013...

Rev. 1.0, 07/01, page 45 of 372 Vector Exception Sources Number Vector Address Priority IIC2 Transmit data empty Transmit end Receive data full NACK detection Arbitration lost/Overrun error Stop conditions detected 24 H'0030 to H'0031 High A/D conversion end 25 H'0032 to H'0033 Low Note : * A low-vo...

Rev. 1.0, 07/01, page 50 of 372 3.3 Reset When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensurethat this LSI is reset at power-up, hold the RES pin low u...

Rev. 1.0, 07/01, page 51 of 372 WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP 5 to WKP 0. These six interrupts have the same vector addresses, and are detected individually by either rising edgesensing or falling edge sensing, depending on the settings of...

Rev. 1.0, 07/01, page 52 of 372 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt contr...

Rev. 1.0, 07/01, page 53 of 372 PC and CCR saved to stack SP (R7) SP – 1 SP – 2 SP – 3 SP – 4 Stack area SP + 4 SP + 3 SP + 2 SP + 1 SP (R7) Even address Prior to start of interrupt exception handling After completion of interrupt exception handling Legend:PCH :PCL :CCR:SP: Upper 8 bits of program c...

Rev. 1.0, 07/01, page 54 of 372 Vector fetch ø Internal address bus Internal read signal Internal write signal (2) Internal data bus (16 bits) Interrupt request signal (9) (1) Internal processing Prefetch instruction of interrupt-handling routine (1) Instruction prefetch address (Instruction is not ...

Rev. 1.0, 07/01, page 55 of 372 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC andCCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,including NMI, are d...

Rev. 1.0, 07/01, page 57 of 372 Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interruptwhen the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.Break conditions that can be set include instruc...

Rev. 1.0, 07/01, page 59 of 372 Table 4-1 Access and Data Bus Used Word Access Byte Access Even Address Odd Address Even Address Odd Address ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits I/O register with 8-bit data buswid...

Rev. 1.0, 07/01, page 60 of 372 4.1.4 Break Data Registers (BDRH, BDRL) BDR (BDRH, BDRL) is a 16-bit read/write register that sets the data for generating an addressbreak interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with thelower 8-bit data bus. When memory or register...

Rev. 1.0, 07/01, page 63 of 372 Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both asystem clock pulse generator and a subclock pulse generator. The system clock pulse generatorconsists of a system clock oscillator, a duty cor...

Rev. 1.0, 07/01, page 64 of 372 LPM Note : LPM: Low-power mode (standby mode, subactive mode, or subsleep mode) 2 1 OSC OSC Figure 5-2 Block Diagram of the System Clock Generator 5.1.1 Connecting a Crystal Oscillator Figure 5-3 shows a typical method of connecting a crystal oscillator. An AT-cut par...

Rev. 1.0, 07/01, page 65 of 372 5.1.2 Connecting a Ceramic Oscillator Figure 5-5 shows a typical method of connecting a ceramic oscillator. OSC 1 OSC 2 C 1 C 2 C 1 = 30 pF ±10% C 2 = 30 pF ±10% Figure 5-5 Typical Connection to Ceramic Oscillator 5.1.3 External Clock Input Method Connect an external ...

Rev. 1.0, 07/01, page 66 of 372 5.2.1 Connecting a 32.768-kHz Crystal Oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystaloscillator, as shown in figure 5-8. Figure 5-9 shows the equivalent circuit of the 32.768-kHzcrystal oscillator. X X C 1 C 2 1 2 C =...

Rev. 1.0, 07/01, page 67 of 372 5.3 Prescalers 5.3.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. The divided output isused for the internal clock of on-chip peripheral modules. Prescaler S is initialized to H'0000 by areset, and starts counting on exit ...

Rev. 1.0, 07/01, page 68 of 372 5.4.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors asclose as possible to the OSC 1 and OSC 2 pins. Other signal lines should be routed away from the oscillator circuit to prevent induction from ...

Rev. 1.0, 07/01, page 69 of 372 Section 6 Power-down Modes This LSI has six modes of operation after a reset. These include a normal active mode and fourpower-down modes, in which power dissipation is significantly reduced. The module standbymode reduces power dissipation by selectively halting on-c...

Rev. 1.0, 07/01, page 71 of 372 Table 6-1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 0 0 8,192 states 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 1.0 1.6 2.0 4.1 8.2 16.4 32.8 1 0 32,768 states 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65...

Rev. 1.0, 07/01, page 72 of 372 6.1.2 System Control Register 2(SYSCR2) The SYSCR2 register controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 6 5 SMSEL LSON DTON 0 0 0 R/W R/W R/W Sleep Mode Selection Low Speed on Flag Direct Transfer on Flag These bits s...

Rev. 1.0, 07/01, page 73 of 372 Bit Bit Name Initial Value R/W Description 7 − 0 − Reserved This bit is always read as 0 and cannot be modified 6 MSTIIC 0 R/W IIC2 Module Standby IIC2 enters the standby mode when this bit is set to 1 5 MSTS3 0 R/W SCI3 Module Standby SCI3 enters the standby mode whe...

Rev. 1.0, 07/01, page 74 of 372 Reset state Standby mode Active mode Sleep mode Subsleep mode Subactive mode Program halt state Program execution state Program halt state SLEEP instruction SLEEP instruction Interrupt Direct transition interrupt Direct transition interrupt Notes: 1. To make a transit...

Rev. 1.0, 07/01, page 76 of 372 Table 6-3 Internal State in Each Operating Mode Function Active Mode Sleep Mode SubactiveMode SubsleepMode Standby Mode System clock oscillator Functioning Functioning Halted Halted Halted Subclock oscillator Functioning Functioning Functioning Functioning Functioning...

Rev. 1.0, 07/01, page 77 of 372 When the RES pin goes low, the CPU goes into the reset state and the sleep mode is cleared. 6.2.2 Standby Mode In the standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modulesstop functioning. However, as long as the rated voltage is sup...

Rev. 1.0, 07/01, page 78 of 372 6.2.4 Subactive Mode The operating frequency of the subactive mode is selected from ø W /2, ø W /4, and ø W /8 by the SA1 and SA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEPinstruction execution. When the SLEEP instruction is execu...

Rev. 1.0, 07/01, page 79 of 372 Legendtosc: OSC clock cycle timetw: Watch clock cycle timetcyc: System clock (ø) cycle timetsubcyc: Subclock (ø SUB ) cycle time 6.4.2 Direct Transition from the Subactive Mode to the Active Mode The time from the start of SLEEP instruction execution to the end of int...

Rev. 71, 07/01, page 81 of 372 Section 7 ROM The features of the 32-bit flash memory built into the flash memory (F-ZTAT) version aresummarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-blockunits. The flash memory is config...

Rev. 1.0, 07/01, page 82 of 372 H'007F H'0000 H'0001 H'0002 H'00FF H'0080 H'0081 H'0082 H'03FF H'0380 H'0381 H'0382 H'047F H'0400 H'0401 H'0402 H'04FF H'0480 H'0481 H'0481 H'07FF H'0780 H'0781 H'0782 H'087F H'0800 H'0801 H'0802 H'08FF H'0880 H'0881 H'0882 H'0BFF H'0B80 H'0B81 H'0B82 H'0C7F H'0C00 H'...

Rev. 71, 07/01, page 85 of 372 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSIswitches to subactive mode. The power supply circuit can be read in the subactive mode, althoughit is partly halted in the power-d...

Rev. 1.0, 07/01, page 86 of 372 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on-board programming/erasing, and programmer mode, in which programming/erasing is performedwith a PROM programmer. On-board programming/erasing ca...

Rev. 1.0, 07/01, page 88 of 372 Table 7-2 Boot Mode Operation Item Host Operation LSI Operation Branches to boot program at reset-start. Processing Contents Processing Contents Bit rateadjustment Continuously transmits data H'00 atspecified bit rate. · Measures low-level period of receive data H'00....

Rev. 71, 07/01, page 89 of 372 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in userprogram mode by branching to a user program/erase control program. The user must set branchingconditions and provide on-board me...

Rev. 1.0, 07/01, page 90 of 372 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on-board programming modes. Depending on the FLMCR1 setting, the flash memory operates in oneof the following four modes: Program mode, program-ve...

Rev. 1.0, 07/01, page 92 of 372 Table 7-4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 7-5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-...

Rev. 71, 07/01, page 93 of 372 6. If the read data is not erased erased successfully, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memor...

Rev. 71, 07/01, page 95 of 372 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, softwareprotection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is f...

Rev. 1.0, 07/01, page 96 of 372 7.6 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via asocket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCUdevice type with the on-chip Hitachi 64-kbyte flash memory (F-ZTAT64V5...

Rev. 71, 07/01, page 97 of 372 H8/3694F FP-64A/FP-64E Socket Adapter (Conversion to 32-pin arrangement) Pin No. Pin Name P54 P76 P20 P80 P81 P82 P83 P84 P85 P86 P87 P10 P14 P15 P16 P17 P50 P51 P52 P53 P21 P55 P56 P57 P74 P75 P22 TEST PB3 AV CC V CC X1 V SS V CL PB2 PB1 PB0 OSC1, OSC2 (OPEN) HN28F101...

Rev. 1.0, 07/01, page 98 of 372 7.6.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode mustfirst be made with a command write, after which the memory ...

Rev. 71, 07/01, page 99 of 372 Table 7-9 AC Characteristics in Transition from Memory Read Mode to Another Mode(Conditions: V CC = 5.0 V ±0.5 V, V SS = 0 V, T a = 25°C ±5°C) Item Symbol Min Max Unit Notes Command write cycle t nxtc 20 — µs Figure 7-7 CE hold time t ceh 0 — ns CE setup time t ces 0 —...

Rev. 1.0, 07/01, page 100 of 372 A15–A0 I/O7–I/O0 t acc t acc t oh t oh Address stable Address stable Figure 7-8 CE and OE Enable State Read Timing Waveforms A15–A0 I/O7–I/O0 t acc t ce t oe t oe t ce t acc t oh t df t df t oh Address stable Address stable Figure 7-9 CE and OE Clock System Read Timi...

Rev. 1.0, 07/01, page 102 of 372 A15–A0 I/O7 I/O6 I/O5–I/O0 t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc Address stable H'40 H'00 Data transfer 1 to 128 bytes Write operation end decision signal Write normal end decision signal Figure 7-10 Auto-Program Mode Timing...

Rev. 71, 07/01, page 103 of 372 Table 7-12 AC Characteristics in Auto-Erase Mode (Conditions: V CC = 5.0 V ±0.5 V, V SS = 0 V, T a = 25°C ±5°C) Item Symbol Min Max Unit Notes Command write cycle t nxtc 20 — µs Figure 7-11 CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ...

Rev. 1.0, 07/01, page 104 of 372 7.6.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode commandw...

Rev. 71, 07/01, page 105 of 372 Table 7-14 Status Read Mode Return Codes Pin Name Initial Value Indications I/O7 0 1: Abnormal end 0: Normal end I/O6 0 1: Command error 0: Otherwise I/O5 0 1: Programming error 0: Otherwise I/O4 0 1: Erasing error 0: Otherwise I/O3 0 Undefined I/O2 0 Undefined I/O1 0...

Rev. 1.0, 07/01, page 106 of 372 7.6.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer modesetup period. After the programmer mode setup time, a transition is made to memory read mode. Table 7-16 Stipulated Transition Times to...

Rev. 71, 07/01, page 107 of 372 7.7 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to at high speed. • Power-down operating mode The power supply circuit of the flash m...

Rev. 1.0, 07/01, page 109 of 372 Section 8 RAM This LSI has 2 kbyte, 1 kbyte or 512 kbytes of on-chip high-speed static RAM. The RAM isconnected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte dataand word data. RAM0300A0000_000020010700

Rev. 1.0, 07/01, page 111 of 372 Section 9 I/O Ports The series of this LSI has twenty-nine general I/O ports and eight input-only ports. Port 8 is alarge current port, which can drive 20 mA (@V OL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately af...

Rev. 1.0, 07/01, page 113 of 372 9.1.2 Port Control Register 1(PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 PCR17 PCR16 PCR15 PCR14 − PCR12 PCR11 PCR10 0 0 0 0 − 0 0 0 W W W W − W W W Whe...

Rev. 1.0, 07/01, page 116 of 372 P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function Setting value 0 0 P10 input pin 0 1 P10 output pin 1 X TMOW output pin Legend X: Don't care. 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown i...

Rev. 1.0, 07/01, page 117 of 372 Bit Bit Name Initial Value R/W Description 7 6 5 4 3 −−−−− −−−−− −−−−− Reserved 2 1 0 PCR22 PCR21 PCR20 0 0 0 W W W When each of the port 2 pins P22 to P20 functions as angeneral I/O port, setting a PCR2 bit to 1 makes thecorresponding pin an output port, while clear...

Rev. 1.0, 07/01, page 118 of 372 P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 0 1 P21 output pin 1 X RXD input pin Legend X:Don't care. P20/SCK3 pin Register SCR3 SMR PCR2 Bit Name CKE1 CKE0 COM PCR20 Pin Function Setting Value 0 0 0 0 P20 input pin 0...

Rev. 1.0, 07/01, page 120 of 372 Bit Bit Name Initial Value R/W Description 0 WKP0 0 R/W P50/ WKP0 Pin Function Switch Selects whether pin P50/ WKP0 is used as P50 or as WKP0 . 0: P50 I/O port 1: WKP0 input pin 9.3.2 Port Control Register 5(PCR5) PCR5 selects inputs/outputs in bit units for pins to ...

Rev. 1.0, 07/01, page 122 of 372 P55/ WKP5 / ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 0 1 P55 output pin 1 X WKP5 / ADTRG input pin Legend X: Don't care. P54/ WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Pin Function Setting Value 0 0 P54 input...

Rev. 1.0, 07/01, page 124 of 372 9.4.1 Port Control Register 7(PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W Description 7 − − − Reserved 6 5 4 PCR76 PCR75 PCR74 0 0 0 W W W Setting a PCR7 bit to 1 makes the correspo...

Rev. 1.0, 07/01, page 126 of 372 9.5 Port 8 Port 8 is a general I/O port also functioning as a Timer W I/O pin. Each pin of the port 8 is shownin figure 9-5. The register setting of the timer W has priority for functions of the pins P84/FTIOD,P83/FTIOC, P82/FTIOB, and P81/FTIOA. P80/FTCI also functi...

Rev. 1.0, 07/01, page 127 of 372 9.5.2 Port Data Register 8(PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDR8 stores output data for port 8 pins. PD...

Rev. 1.0, 07/01, page 129 of 372 P81/FTIOA pin Register TIOR0 PCR8 Bit Name IOA2 IOA1 IOA0 PCR81 Pin Function Setting Value 0 0 0 0 P81 input/FTIOA input pin 0 0 0 1 P81 output/FTIOA input pin 0 0 1 X FTIOA output pin 0 1 X X FTIOA output pin 1 X X 0 P81 input/FTIOA input pin 1 X X 1 P81 output/FTIO...

Rev. 1.0, 07/01, page 130 of 372 9.6.1 Port Data Register B(PDRB) PDRB is a general input-only port data register of port B. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 −−−−−−−− R R R R R R R R The input value of each pin is read by reading this registe...

Rev. 1.0, 07/01, page 131 of 372 Section 10 Timer A Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clocktime-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10-1shows a block diagram of timer A. 10.1 Features • Timer A ...

Rev. 1.0, 07/01, page 132 of 372 ø W TMOW ø ø W /32 ø W /16 ø W /8 ø W /4 ø W /32 ø W /16 ø W /8 ø W /4 ø/8192, ø/4096,ø/2048, ø/512, ø/256, ø/128, ø/32, ø/8 ø W /128 ø W /4 1/4 PSW PSS TMA TCA IRRTA ÷ 8 * ÷ 64 * ÷ 128 * ÷ 256 * LegendTMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A ov...

Rev. 1.0, 07/01, page 134 of 372 10.3.2 Timer Counter A (TCA) TCA is an 8-bit readable up-counter, which is incremented by internal clock input. The clocksource for input to this counter is selected by bits TMA3 to TMA0 in TMA. TCA values can beread by the CPU in active mode, but cannot be read in s...

Rev. 1.0, 07/01, page 135 of 372 10.5 Usage Note When the clock time base function is selected as the internal clock of TCA in active mode or sleepmode, the internal clock is not synchronous with the system clock, so it is synchronized by asynchronizing circuit. This may result in a maximum error of...

Rev. 1.0, 07/01, page 137 of 372 Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare-match signals with two registers can also be used to reset the counter, request an interrupt, oroutput a pulse signal with an arbitrary duty cycle. Countin...

Rev. 1.0, 07/01, page 138 of 372 TRGV TMCIV TMRIV TMOV ø Trigger control Clock select Clear control Output control PSS TCRV1 TCORB Comparator TCNTV Comparator TCORA TCRV0 Interrupt request control TCSRV CMIACMIBOVI Inter nal data b u s Legend:TCORA: Time constant register A TCORB: Time constant regi...

Rev. 1.0, 07/01, page 139 of 372 11.3 Register Descriptions Time V has the following registers. For details on register addresses and register states duringeach process, refer to section 19, Internal I/O Registers. • Timer counter V(TCNTV) • Timer constant register A(TCORA) • Timer constant register...

Rev. 1.0, 07/01, page 141 of 372 Table 11-2 Clock signals to input to TCNTV and the counting conditions TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 CKS2 CKS1 CKS0 ICKS0 Description 0 0 0 − Clock input disabled 1 0 Internal clock: counts on φ /4, falling edge 1 Internal clock: counts on φ /8, falling edge 1 ...

Rev. 1.0, 07/01, page 144 of 372 11.4 Operation 11.4.1 Timer V operation 1. According to table 11-2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected,TCNTV starts counting-up. Figure 11-2 sho...

Rev. 1.0, 07/01, page 145 of 372 N – 1 N + 1 N ø TMCIV(External clock input pin) TCNTV input clock TCNTV Figure 11-3 Increment Timing with External Clock H'FF H'00 ø TCNTV Overflow signal OVF Figure 11-4 OVF Set Timing N N N+1 ø TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11-5 CMFA...

Rev. 1.0, 07/01, page 146 of 372 ø Compare match A signal Timer V output pin Figure 11-6 TMOV Output Timing N H'00 ø Compare match A signal TCNTV Figure 11-7 Clear Timing by Compare Match N – 1 N H'00 ø Compare match A signal Timer V output pin TCNTV Figure 11-8 Clear Timing by TMRIV Input 11.5 Time...

Rev. 1.0, 07/01, page 147 of 372 4. With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB. Counter cleared TCNTV H'FF TCORA TCORB H'00 TMOV Figure 11-9 Pulse Output Example 11.5.2 Pulse Output with Arb...

Rev. 1.0, 07/01, page 148 of 372 Counter cleared TCNTV H'FF TCORA TCORB H'00 TRGV TMOV Compare match A Compare match B clears TCNTV and halts count-up Compare match B clears TCNTV and halts count-up Compare match A Figure 11-10 Example of Pulse Output Synchronized to TRGV Input 11.6 Usage Notes The ...

Rev. 1.0, 07/01, page 150 of 372 Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11-13 Internal Clock Switching and TCNTV Operation

Rev. 1.0, 07/01, page 151 of 372 Section 12 Timer W Timer W has a 16-bit timer having output compare and input capture functions. Timer W cancount external events and output pulses with an arbitrary duty cycle by compare match betweenthe timer counter and four general registers. Thus, it can be appl...

Rev. 1.0, 07/01, page 152 of 372 Table 12-1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Count clock Internal clocks: φ , φ /2, φ /4, φ /8 External clock: FTCI General registers(output compare/inputcapture registers) Periodspecified inGRA GRA GRB GRC (bufferregister forGR...

Rev. 1.0, 07/01, page 157 of 372 12.3.3 Timer Interrupt Enable Register W(TIERW) TIERW controls the timer W interrupt request. Bit Bit Name Initial Value R/W Description 7 OVIE 0 R/W Timer Overflow Interrupt Enable When this bit is set to 1, FOVI interrupt requested by OVFflag in TSRW is enabled. 6 ...

Rev. 1.0, 07/01, page 162 of 372 12.4 Operation • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free-running counter. When the CST bit in TMRW is set to 1, TCNT starts incrementing the count.When t...

Rev. 1.0, 07/01, page 163 of 372 TCNT value GRA H'0000 CST bit IMFA Time Flag cleared by software Figure 12-3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D cancause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, ...

Rev. 1.0, 07/01, page 165 of 372 TCNT value H'FFFF H'1000 H'0000 FTIOA GRA Time H'AA55 H'55AA H'F000 H'1000 H'F000 H'55AA GRB H'AA55 FTIOB Figure 12-7 Input Capture Operating Example Figure 12-8 shows an example of buffer operation when the GRA is set as an input-captureregister and GRC is set as th...

Rev. 1.0, 07/01, page 166 of 372 12.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB,GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, andFTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a gene...

Rev. 1.0, 07/01, page 168 of 372 TCNT value GRA H'0000 FTIOB Time GRB Duty 0% Write to GRB Write to GRB TCNT value GRA H'0000 FTIOB Time GRB Duty 100% Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occur simultaneously. TCNT value GRA H'0000 FT...

Rev. 1.0, 07/01, page 169 of 372 TCNT value GRA H'0000 FTIOB Time GRB Duty 100% Write to GRB TCNT value GRA H'0000 FTIOB Time GRB Duty 0% Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occursimultaneously. TCNT value GRA H'0000 FTIOB Time GRB D...

Rev. 1.0, 07/01, page 170 of 372 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12-14 shows the TCNT count timing when the internal clock source is selected. Figure 12-15 shows the timing when the external clock source is selected. The pulse width of the externalclock signal must be at least ...

Rev. 1.0, 07/01, page 171 of 372 Figure 12-16 shows the output compare timing. GRA to GRD TCNT TCNT input clock φ N N N+1 Compare match signal FTIOA to FTIOD Figure 12-16 Output Compare Output Timing 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be sel...

Rev. 1.0, 07/01, page 172 of 372 12.5.4 Timing of Counter Clearing by Compare Match Figure 12-18 shows the timing when the counter is cleared by compare match A. When the GRAvalue is N, the counter counts from 0 to N, and its cycle is N + 1. TCNT Compare match signal φ GRA N N H'0000 Figure 12-18 Ti...

Rev. 1.0, 07/01, page 173 of 372 GRA, GRB TCNT Input capturesignal φ GRC, GRD N M M N+1 N N N+1 Figure 12-20 Buffer Operation Timing (Input Capture) 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, thecor...

Rev. 1.0, 07/01, page 174 of 372 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, thecorresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure12-22 shows the timing of the IM...

Rev. 1.0, 07/01, page 175 of 372 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock( φ ) cycles; shorter pulses will not be detected correctly. 2. ...

Rev. 1.0, 07/01, page 176 of 372 TCNT Previous clock N N+1 N+2 N+3 New clock Count clock The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12-25 Internal Clock Switching and TCNT Operation

Rev. 1.0, 07/01, page 177 of 372 Section 13 Watchdog Timer The watchdog timer(WDT) is an 8-bit timer that can generate an internal reset signal for this LSIif a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the WDT is shown in fig...

Rev. 1.0, 07/01, page 180 of 372 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 toB2WI when TCSRWE in TCSRWD is set to 1, TCWD begins counting up. (To operate thewatchdog timer, two write accesses to TCSRWD is required.) When a clock puls...

Rev. 1.0, 07/01, page 181 of 372 Section 14 Serial Communication Interface3 (SCI3) Serial Communication Interface (SCI) can handle both asynchronous and clocked synchronousserial communication. In asynchronous mode, serial data communication can be carried out usingstandard asynchronous communicatio...

Rev. 1.0, 07/01, page 182 of 372 Clock TXD RXD SCK3 BRR SMR SCR3 SSR TDR RDR TSR RSR Transmit/receive control circuit Internal data bus LegendRSR:RDR:TSR: TDR: SMR: SCR3:SSR:BRR:BRC: Receive shift registerReceive data registerTransmit shift registerTransmit data registerSerial mode registerSerial co...

Rev. 1.0, 07/01, page 183 of 372 14.2 Input/Output Pins Table 14-1 shows the SCI pin configuration. Table 14-1 Pin Configuration Pin Name Abbrev. I/O Function SCI clock SCK3 I/O SCI clock input/output SCI receive data input RXD Input SCI receive data input SCI transmit data output TXD Output SCI tra...

Rev. 1.0, 07/01, page 190 of 372 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13-2shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 ofSMR in asynchronous mode. Table 13-3 shows the...

Rev. 1.0, 07/01, page 193 of 372 Table 14-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency ø (MHz) 12.288 14 14.7456 16 Bit Rate(bit/s) n N Error(%) n N Error(%) n N Error(%) n N Error(%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 ...

Rev. 1.0, 07/01, page 194 of 372 Table 14-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency ø (MHz) 2 4 8 10 16 Bit Rate(bit/s) n N n N n N n N n N 110 3 70 — — — — — — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2....

Rev. 1.0, 07/01, page 195 of 372 14.4 Operation in Asynchronous Mode Figure 14-2 shows the general format for asynchronous serial communication. One character (orframe) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high orlow level), and finally stop bits ...

Rev. 1.0, 07/01, page 197 of 372 14.4.3 Data Transmission Figure 14-5 shows an example of operation for transmission in asynchronous mode. Intransmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been...

Rev. 1.0, 07/01, page 200 of 372 Table 14-5 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF * OER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing e...

Rev. 1.0, 07/01, page 203 of 372 14.5 Operation in Clocked Synchronous Mode Figure 14-9 shows the general format for clocked synchronous communication. In clockedsynchronous mode, data is transmitted or received synchronous with clock pulses. A singlecharacter in the transmit data consists of the 8-...

Rev. 1.0, 07/01, page 204 of 372 14.5.3 Serial Data Transmission Figure 14-10 shows an example of SCI operation for transmission in clocked synchronous mode.In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes...

Rev. 1.0, 07/01, page 206 of 372 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14-12 shows an example of SCI operation for reception in clocked synchronous mode. Inserial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a s...

Rev. 1.0, 07/01, page 208 of 372 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14-14 shows a sample flowchart for simultaneous serial transmit and receive operations.The following procedure should be used for simultaneous serial data transmit and receiveoperations. To switch from...

Rev. 1.0, 07/01, page 210 of 372 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number ofprocessors sharing communication lines by asynchronous serial communication using themultiprocessor format, in which a multiprocessor ...

Rev. 1.0, 07/01, page 212 of 372 14.6.1 Multiprocessor Serial Data Transmission Figure 14-16 shows a sample flowchart for multiprocessor serial data transmission. For an IDtransmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmissioncycle, clear the MPBT bit in SSR to...

Rev. 1.0, 07/01, page 213 of 372 14.6.2 Multiprocessor Serial Data Reception Figure 14-17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit inSCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving datawith a 1 multiprocessor bi...

Rev. 1.0, 07/01, page 214 of 372 Yes No Start reception No Yes [4] Clear RE bit in SCR3 to 0 Error processing [5] Yes No FER+OER = 1 RDRF = 1 All data received? Read MPIE bit in SCR3 [1] [2] Read OER and FER flags in SSR Read RDRF flag in SSR [3] Read receive data in RDR No Yes [A] This station’s ID...

Rev. 1.0, 07/01, page 215 of 372 Start receive error processing Yes No Clear OER, and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing OER = 1 FER = 1 Break? [5] [A] End Figure 14-17 Sample Multiprocessor Serial Reception Flowchart (2)

Rev. 1.0, 07/01, page 217 of 372 14.7 Interrupts SCI creates the following six interrupt requests: transmission end, transmit data empty, receivedata full, and receive errors (overrun error, framing error, and parity error). Table 14-6 shows theinterrupt sources. Table 14-6 SCI Interrupt Requests In...

Rev. 1.0, 07/01, page 218 of 372 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin valuedirectly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possiblythe PER flag. Note...

Rev. 1.0, 07/01, page 219 of 372 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transferrate. In reception, the SCI samples the falling edge of the start bit using the basic clock,...

Rev. 1.0, 07/01, page 223 of 372 Vcc Vcc SCL in out SCL SDA in out SDA SCL (Master) (Slave 1) (Slave 2) SDA SCL in out SCL SDA in out SDA SCL in out SCL SDA in out SDA Figure 15-2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15-1 summarizes the input/output pins used by the ...

Rev. 1.0, 07/01, page 225 of 372 Table 15-2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ =5 MHz φ =8 MHz φ =10 MHz φ =16 MHz 0 φ /28 179 kHz 286 kHz 357 kHz 571 kHz 0 1 φ /40 125 kHz 200 kHz 250 kHz 400 kHz 0 φ /48 104 kHz 167 kHz 208 kHz 333 kHz 0 1 1 φ /64 78.1 k...

Rev. 1.0, 07/01, page 232 of 372 Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first framefollowing a start condition matches bits SVA6 to SVA0 inSAR. [Setting conditions] • When the slave address is detected...

Rev. 1.0, 07/01, page 234 of 372 15.4 Operation The I 2 C bus interface can communicate either in I 2 C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 I 2 C Bus Format Figure 15-3 shows the I 2 C bus formats. Figure 15-4 shows the I 2 C bus timing. The first frame following...

Rev. 1.0, 07/01, page 235 of 372 P: Stop condition. The master device drives SDA from low to high while SCL is high. 15.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and theslave device returns an acknowledge signal. For master...

Rev. 1.0, 07/01, page 237 of 372 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slavedevice, and returns an acknowledge signal. For master receive mode operation timing, refer tofigures 15-7 and 15-8. The reception procedur...

Rev. 1.0, 07/01, page 239 of 372 15.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputsthe receive clock and returns an acknowledge signal. For slave transmit mode operation timing,refer to figures 15-9 and 15-10. The trans...

Rev. 1.0, 07/01, page 241 of 372 TDRE Data n TEND ICDRS ICDRR 1 9 2 3 4 5 6 7 8 9 TRS ICDRT A SCL (Master output) SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Slave transmit mode Slave receivemode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [3] Clear TEND [5] Clear TDRE [4] Read ICD...

Rev. 1.0, 07/01, page 242 of 372 4. The last byte data is read by reading ICDRR. ICDRS ICDRR 1 2 1 3 4 5 6 7 8 9 9 A A RDRF Data 1 Data 2 Data 1 SCL (Master output) SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [2] Read ICDRR (dummy r...

Rev. 1.0, 07/01, page 243 of 372 15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit inSAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. WhenMST is 0, the external clock input i...

Rev. 1.0, 07/01, page 244 of 372 1 2 7 8 1 7 8 1 SCL TRS Bit 0 Data 1 Data 1 Data 2 Data 3 Data 2 Data 3 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 SDA (Output) TDRE ICDRT ICDRS User processing [3] Write data to ICDRT [3] Write data to ICDRT [3] Write data to ICDRT [3] Write data to ICDRT [2] Set TRS...

Rev. 1.0, 07/01, page 246 of 372 15.4.8 Example of Use Flowcharts in respective modes that use the I 2 C bus interface are shown in figures 15-17 to 15-20. BBSY=0 ? No TEND=1 ? No Yes Start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] Initialize Set MST and TRS in ICCR1 to 1. Write 1...

Rev. 1.0, 07/01, page 247 of 372 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Mater receive mode Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT in ICIER to 1 Set RCVD in ICCR1 to 1 Read ICDRR Read R...

Rev. 1.0, 07/01, page 248 of 372 TDRE=1 ? Yes Yes No Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR Last byte? Write transmit data in ICDRT Read TEND in ICSR Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End [1] Clear the AAS fla...

Rev. 1.0, 07/01, page 249 of 372 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Slave receive mode Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT in ICIER to 1 Read ICDRR Read RDRF in ICSR Read ICDRR End No Yes [1] [2] [3] [4] [5] [6] [7] [8] [...

Rev. 1.0, 07/01, page 250 of 372 15.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,NACK receive, STOP recognition, and arbitration lost/overrun. Table 15-3 shows the contents ofeach interrupt request. Table 15-3 Interrupt Req...

Rev. 1.0, 07/01, page 251 of 372 15.6 Bit Synchronous Circuit In master mode,this module has a possibility that high level period may be short in the two statesdescribed below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load...

Rev. 1.0, 07/01, page 253 of 372 Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eightanalog input channels to be selected. The block diagram of the A/D converter is shown in figure16-1. 16.1 Features • 10-bit resolution • Eight input...

Rev. 1.0, 07/01, page 254 of 372 Module data bus Control circuit Internal data bus 10-bit D/A Comparator + Sample-and-hold circuit ADIinterrupt Bus interface Successive approximations register Analog multiplexer ADCSR ADCR ADDRD ADDRC ADDRB ADDRA AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 LegendADCR :ADCSR :AD...

Rev. 1.0, 07/01, page 255 of 372 16.2 Input/Output Pins Table 16-1 summarizes the input pins used by the A/D converter. The 18 analog input pins aredivided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog inputpins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin...

Rev. 1.0, 07/01, page 256 of 372 16.3 Register Description The A/D converter has the following registers. For details on register addresses and register statesduring each processing, refer to section 19, Internal I/O Registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data r...

Rev. 1.0, 07/01, page 259 of 372 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has twooperating modes; single mode and scan mode. When changing the operating mode or analog inputchannel, in order to prevent incorrect operation, first clear the bit A...

Rev. 1.0, 07/01, page 260 of 372 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analoginput when the A/D conversion start delay time (t D ) has passed after the ADST bit is set to 1, then starts conversion. Figure...

Rev. 1.0, 07/01, page 261 of 372 Table 16-3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conversion start delay time t D 6 — 9 4 — 5 Input sampling time t SPL — 31 — — 15 — A/D conversion time t CONV 131 — 134 69 — 70 Note: All values represent the number...

Rev. 1.0, 07/01, page 262 of 372 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16-4)...

Rev. 1.0, 07/01, page 263 of 372 FS Digital output Ideal A/D conversioncharacteristic Nonlinearityerror Analoginput voltage Offset error Actual A/D conversioncharacteristic Full-scale error Figure 16-5 A/D Conversion Accuracy Definitions (2) 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedanc...

Rev. 1.0, 07/01, page 264 of 372 20 pF 10 k C in = 15 pF Sensor outputimpedanceup to 5 k This LSI Low-passfilterC to 0.1 F Sensor input A/D converterequivalent circuit Figure 16-6 Analog Input Circuit Example

Rev. 1.0, 07/01, page 265 of 372 Section 17 Power-on Reset and Low-Voltage Detection Circuits (Optional) This LSI includes a power-on reset circuit and low-voltage detection circuit. The low-voltage detection circuit has two functions: one is to generate an interrupt when thepower-supply voltage fal...

Rev. 1.0, 07/01, page 266 of 372 PSS :LVDCR :LVDSR : Prescaler SLow-voltage-detection control registerLow-voltage-detection status register Legend CK R PSS R S Q OVF Vreset Vint LVDCR LVDSR Referencevoltage Analog-noisecancellation circuit Analog-noisecancellation circuit Interruptcontrolcircuit Int...

Rev. 1.0, 07/01, page 268 of 372 17.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR is an 8-bit readable/writable register which indicates whether or not the power-supplyvoltage has become lower or higher than the respective specified values. Bit Bit Name InitialValue R/W Description 7 to 2 ...

Rev. 1.0, 07/01, page 269 of 372 V CC V SS V SS OVF PSS-resetsignal Internal resetsignal PSS counter starts Reset released 131,072 cycles t PWON Figure 17-2 Operational Timing of the Power-on Reset Circuit 17.3.2 Low-Voltage Detection Circuit Reset by Low Voltage Detect (LVDR): Figure 17-3 shows the...

Rev. 1.0, 07/01, page 270 of 372 V CC Vreset V SS OVF PSS-resetsignal Internal resetsignal PSS counter starts Reset released 131,072 cycles Figure 17-3 Operational Timing of LVDR Interrupt by Low Voltage Detect (LVDI) : Figure 17-4 shows the timing of LVDI functions. LVDI enters the module-standby s...

Rev. 1.0, 07/01, page 271 of 372 V CC Vint(D) Vint(U) V SS LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated LVDDE Figure 17-4 Operational Timing of LVDI Procedures for Operating and Releasing the Low-Voltage Detection Circuit : To operate or release the low-voltage detection circu...

Rev. 1.0, 07/01, page 273 of 372 Section 18 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables theinternal power supply to be fixed at a constant level of approximately 3.0 V, regardless of thevoltage of the power supply connected to th...

Rev. 1.0, 07/01, page 274 of 372 18.2 When Not Using the Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supplyto the V CL pin and V CC pin, as shown in figure 18-2. The external power supply is then input directly to t...

Rev. 1.0, 07/01, page 275 of 372 Section 19 Internal I/O Registers 19.1 Register Addresses Register Name Abbre-viation Bit No Address ModuleName DataBusWidth AccessState — — — H'F000 toH'F72F — — — Low-voltage detection control register LVDCR 8 H'F730 LVDC * 1 8 2 Low-voltage detection status regist...

Rev. 1.0, 07/01, page 279 of 372 19.2 Register Bits RegisterName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name — — — — — — — — — — LVDCR LVDE — — — LVDSEL LVDRE LVDDE LVDUE LVDC LVDSR — — — — — — LVDDF LVDUF (optional) * 1 — — — — — — — — — — ICCR1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 ...

Rev. 1.0, 07/01, page 282 of 372 19.3 Registers States in Each Operating Mode RegisterName Reset Active Sleep Subactive Subsleep Standby Module LVDCR Initialized − − − − − LVDC LVDSR Initialized − − − − − (optional) * 1 ICCR1 Initialized − − − − − IIC2 ICCR2 Initialized − − − − − ICMR Initialized − ...

Rev. 1.0, 07/01, page 284 of 372 RegisterName Reset Active Sleep Subactive Subsleep Standby Module PCR5 Initialized − − − − − I/O port PCR7 Initialized − − − − − PCR8 Initialized − − − − − SYSCR1 Initialized − − − − − Power-down SYSCR2 Initialized − − − − − Power-down IEGR1 Initialized − − − − − Int...

Rev. 1.0, 07/01, page 285 of 372 Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20-1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage V CC –0.3 to +7.0 V * Analog power supply voltage AV CC –0.3 to +7.0 V * Input voltage Ports other than portsB and...

Rev. 1.0, 07/01, page 286 of 372 Power Supply Voltage and Operating Frequency Range 10.0 1.0 16.0 3.0 4.0 5.5 V CC (V) ø (MHz) 16.384 3.0 4.0 5.5 V CC (V) ø SUB (kHz) 8.192 4.096 1250 78.125 2000 3.0 4.0 5.5 V CC (V) ø (kHz) • AV CC = 3.3 to 5.5 V • Active mode• Sleep mode (When MA2 in SYSCR2 = 0 ) ...

Rev. 1.0, 07/01, page 287 of 372 20.2.2 DC Characteristics Table 20-2 DC Characteristics (1) V CC = 3.0 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes Input highvoltage V IH RES , NMI , WKP0 to WKP5 , I...

Rev. 1.0, 07/01, page 291 of 372 Note: * Pin states during current consumption measurement are given below (excluding current inthe pull-up MOS transistors and output buffers). Mode RES Pin Internal State Other Pins Oscillator Pins Active mode 1 V CC Operates V CC System clock oscillator:ceramic or ...

Rev. 1.0, 07/01, page 295 of 372 Table 20-4 I 2 C Bus Interface Timing V CC = 3.0 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, unless otherwise indicated. Test Values Reference Item Symbol Condition Min Typ Max Unit Figure SCL input cycle time t SCL 12t cyc + 600 — — ns Figure 20-4 SCL input high wid...

Rev. 1.0, 07/01, page 297 of 372 20.2.4 A/D Converter Characteristics Table 20-6 A/D Converter Characteristics V CC = 3.0 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, unless otherwise indicated. Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Analog power supplyvol...

Rev. 1.0, 07/01, page 298 of 372 Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Conversion time(single mode) AV CC = 4.0 to 5.5 V 134 — — t cyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB...

Rev. 1.0, 07/01, page 302 of 372 20.3 Electrical Characteristics (Mask ROM Version) 20.3.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range 10.0 2.0 16.0 2.7 4.0 5.5 V CC (V) ø OSC (MHz) 32.768 2.7 4.0 5.5 V CC (V) ø W (kHz) • AV CC = 3.0 to 5.5 V • Acti...

Rev. 1.0, 07/01, page 314 of 372 Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Conversion time(single mode) AV CC = 4.0 to 5.5 V 134 — — t cyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB...

Rev. 1.0, 07/01, page 315 of 372 20.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 20-16 Power-Supply-Voltage Detection Circuit Characteristics V CC = 2.7 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, unless otherwise specified. Test Values Item Symbol Condition Min Typ Ma...

Rev. 1.0, 07/01, page 316 of 372 V IH V IL t IL to to TMCIFTIOA to FTIODTMCIV, TMRIVTRGV t IH Figure 20-3 Input Timing SCL V IH V IL t STAH t BUF P * S * t Sf t Of t Sr t SCL t SDAH t SCLH t SCLL SDA Sr * t STAS t SP t STOS t SDAS P * Note: * S, P, and Sr represent the following:S: Start conditionP:...

Rev. 1.0, 07/01, page 317 of 372 t Scyc t TXD t RXS t RXH V OH V or V IH OH V or V IL OL * * * V OL * SCK3 TXD (transmit data) RXD (receive data) Note: * Output timing reference levels Output high: Output low: Load conditions are shown in figure 20-7. V = 2.0 V V = 0.8 V OH OL Figure 20-6 SCI Synchr...

Rev. 1.0, 07/01, page 319 of 372 Appendix A Instruction Set A.1 Instruction List Condition Code Symbol Description Rd General destination register Rs General source register Rn General register ERd General destination register (address register or 32-bit register) ERs General source register (addres...

Rev. 1.0, 07/01, page 320 of 372 Condition Code Notation (cont) Symbol Description ↔ Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes

Rev. 1.0, 07/01, page 321 of 372 Table A.1 Instruction Set 1. Data Transfer Instructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code I H N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd...

Rev. 1.0, 07/01, page 323 of 372 2. Arithmetic Instructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code I H N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32,...

Rev. 1.0, 07/01, page 326 of 372 3. Logic Instructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code I H N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd ...

Rev. 1.0, 07/01, page 327 of 372 4. Shift Instructions Mnemonic Operand Size No. of States * 1 Condition Code I H N Z V C SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W R...

Rev. 1.0, 07/01, page 330 of 372 6. Branching Instructions — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —...

Rev. 1.0, 07/01, page 332 of 372 7. System Control Instructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code I H N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — TRAPA #x:2 RTE SLEEP LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(...

Rev. 1.0, 07/01, page 333 of 372 8. Block Transfer Instructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code I H N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — EEPMOV. B EEPMOV. W Operation if R4L ≠ 0 then repeat @R5 → @R6 R5+1 ...

Rev. 1.0, 07/01, page 334 of 372 A.2 Operation Code Map Table A.2 Operation Code Map (1) AH AL 0123 4567 89 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F NOP BRA MULXU BSET BRN DIVXU BNOT STC BHI MULXU BCLR LDC BLS DIVXU BTST ORC OR.B BCC RTS OR XORC XOR.B BCS BSR XOR BOR BIOR BXOR BIXOR BAND BIAND AN...

Rev. 1.0, 07/01, page 337 of 372 A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculatingthe number of states required for instruction execution are shown below. Table A.4 shows thenumber of cycles of each type occurring in each ins...

Rev. 1.0, 07/01, page 338 of 372 Table A.3 Number of Cycles in Each Instruction Execution Status Access Location (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch S I 2 — Branch address read S J Stack operation S K Byte data access S L 2 or 3 * Word data access S M — Int...

Rev. 1.0, 07/01, page 348 of 372 A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Addressing Mode MOV POP, PUSH MOVFPE, MOVTPE ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS AND, OR, XOR ...

Rev. 1.0, 07/01, page 349 of 372 Appendix B I/O Port Block Diagrams B.1 I/O Port Block RES goes low in a reset, and SBY goes low in a reset and in standby mode. PDR PUCR PMR PCR PUCR: Port pull-up control registerPMR: Port mode register PDR: Port data register PCR: Port control register TRGV Interna...

Rev. 1.0, 07/01, page 365 of 372 DEC V IN CH3 to CH0 A/D converter Internal data bus Figure B.17 Port B Block Diagram (PB7 to PB0) B.2 Port States in Each Operating State Port Reset Sleep Subsleep Standby Subactive Active P17 to P14,P12 to P10 Highimpedance Retained Retained Highimpedance * Function...

Rev. 1.0, 07/01, page 366 of 372 Appendix C Product Code Lineup Package (Hitachi Package Code) Product Type QFP-64(FP-64A) LQFP-64(FP-64E) LQFP-48(FP-48F) Flash memoryversion Product with POR& LVDC HD64F3694GH HD64F3694GFP HD64F3694GFX Standard product HD64F3694H HD64F3694FP HD64F3694FX Mask Rom...

Rev. 1.0, 07/01, page 367 of 372 Appendix D Package Dimensions The package dimensions that are shows in the Hitachi Semiconductor Packages Data Book haspriority. Hitachi CodeJEDECEIAJMass (reference value) FP-64E Conforms 0.4 g Unit: mm *Dimension including the plating thickness Base material dimens...

Rev. 1.0, 07/01, page 369 of 372 Index A/D Converter ........................................ 253 sample-and-hold circuit ...................... 260Scan Mode .......................................... 259Single Mode ........................................ 259 Absolute Maximum Ratings .................

Rev. 1.0, 07/01, page 370 of 372 large current ports ....................................... 1 Memory Map .............................................. 8Module Standby Function......................... 79 On-Board Programming Modes................ 86 Package ...........................................

Rev. 1.0, 07/01, page 371 of 372 TCORA ....................... 139, 276, 279, 281TCORB ....................... 139, 276, 279, 281TCRV0........................ 140, 275, 279, 281TCRV1........................ 143, 276, 279, 281TCRW ......................... 156, 275, 278, 281TCSRV .......................