Page 5 - Preface; How to Use This Manual; This document contains the following chapters:; Related Documentation From Texas Instruments and Others; Reducing EMI With Low Voltage Differential Signaling (SLLA030B).; FCC Warning
v Read This First Preface How to Use This Manual This document contains the following chapters: - Chapter 1—The M-LVDS Evaluation Module - Chapter 2—Test Setup - Chapter 3—Bill of Materials, Board Layout, and PCB Construction - Appendix A—Schematic Related Documentation From Texas Instruments and Ot...
Page 7 - Contents; The M-LVDS Evaluation Module
Running Title—Attribute Reference vii Chapter Title—Attribute Reference Contents 1 The M-LVDS Evaluation Module 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Overview 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 8 - Figures
Running Title—Attribute Reference viii Figures 1−1. M-LVDS Unit Interval Definition 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region 1-4 . . . . 1−3 Point-to-Poin...
Page 9 - controlled impedance cable of varying lengths. This provides the; Topic; Chapter 1
1-1 The M-LVDS Evaluation Module The M-LVDS Evaluation Module This document describes the multipoint low-voltage differential-signaling(M-LVDS) evaluation module (EVM) used to aid designers in development andanalysis of this new signaling technology. The Texas InstrumentsSN65MLVD200A, SN65MLVD201, S...
Page 10 - and t; ) rule results in the signaling rates shown in Table 1−1.; Figure 1−1. M-LVDS Unit Interval Definition; Table 1−1. M-LVDS Devices Supported by the EVM
Overview 1-2 The M-LVDS Evaluation Module 1.1 Overview The EVM comes with all the production devices in Table 1−1. TheSN65MLVD201 and SN65MLVD207 are installed on the circuit board, and caneasily be replaced with the other devices supplied. The M-LVDS devicesevaluated with this EVM are in the SN75AL...
Page 12 - Table 1−2. Receiver Input Voltage Threshold Requirements; Region; M-LVDS EVM Kit Contents; The M-LVDS EVM kit contains the following:
M-LVDS EVM Kit Contents 1-4 The M-LVDS Evaluation Module Table 1−2. Receiver Input Voltage Threshold Requirements Receiver Type Low High Type-1 −2.4 V ≤ V ID ≤ −0.05 V 0.05 V ≤ V ID ≤ 2.4 V Type-2 −2.4 V ≤ V ID ≤ 0.05 V 0.15 V ≤ V ID ≤ 2.4 V Figure 1−2. Expanded Graph of Receiver Differential Input ...
Page 13 - Configurations; Figure 1−4. Parallel Termination Simplex Circuit
Configurations 1-5 The M-LVDS Evaluation Module 1.4 Configurations The M-LVDS EVM board allows the user to construct various busconfigurations. The two devices on the EVM allow for point-to-point simplex,parallel-terminated point-to-point simplex, and two-node multipoint operation.All of these modes...
Page 14 - Multidrop; Figure 1−5. Multidrop or Distributed Simplex Circuit; Multipoint
Configurations 1-6 The M-LVDS Evaluation Module 1.4.2 Multidrop A multidrop configuration (see Figure 1−5) with two receiver nodes can besimulated with the EVM. To get additional receiver nodes on the same busrequires additional EVMs. M-LVDS controlled driver transition times andhigher signal levels...
Page 15 - EVM Operation With Separate Power Supplies; Set PS2 to 0 V; PS2 Output
Configurations 1-7 The M-LVDS Evaluation Module Figure 1−7. Two-Node Multipoint Circuit T U1 U2 T 1.4.4 EVM Operation With Separate Power Supplies The EVM has been designed with independent power planes for the twodevices. The two devices can be powered with independent supplies or witha single supp...
Page 16 - Recommended Equipment; transmission medium from the driver to the receiver, (twisted-pair
Recommended Equipment 1-8 The M-LVDS Evaluation Module Figure 1−8. EVM Configuration for Including a Ground Potential Difference VoltageBetween Nodes PS1 PS2 PS3 Jumpers removed from W7, W8, W9, W10 W9 W7 W8 W10 J13 J14 J17 J18 + − + − + − 1.5 Recommended Equipment - 3.3 Vdc at 0.5-A power supply or...
Page 17 - Test Setup; This chapter describes how to setup and use the M-LVDS EVM.; Chapter 2
2-1 Test Setup Test Setup This chapter describes how to setup and use the M-LVDS EVM. Topic Page 2.1 Typical Cable Test Configurations 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Test Results 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 18 - Table 2−1. EVM Configuration Options; transmission line at one end.
Typical Cable Test Configurations 2-2 Test Setup 2.1 Typical Cable Test Configurations Each of the following test configurations is a transmission line consisting of atwisted-pair cable connected on the 2-pin connectors (P1, P2, or P3).Table 2−1 shows the possible configurations. In addition to the ...
Page 19 - Point-to-Point Parallel Terminated Simplex Transmission; Two-Node Multipoint Transmission
Typical Cable Test Configurations 2-3 Test Setup 2.1.2 Point-to-Point Parallel Terminated Simplex Transmission 1) Connect a twisted-pair cable from P1 to P2. 2) Verify resistor R4 and R7 are installed. 3) Remove resistors R5 and R6. This properly terminates the transmission line at both ends. 4) Ena...
Page 20 - Figure 2−3. Two-Node Multipoint Transmission
Typical Cable Test Configurations 2-4 Test Setup Figure 2−3. Two-Node Multipoint Transmission R16 100 P3 R3 49.9 R5 100 U1 R7 100 R6 100 J2 9 10 5 P2 Twisted Pair Cable Input Signal R14 49.9 R4 100 U2 R15 100 U1 J8 11 12 2 7 6 4 Input Signal R13 453 J7 TP3 R2 453 J1 Output Signal TP1 TP4 3 W1 V CC J...
Page 21 - Test Results
Test Results 2-5 Test Setup 2.2 Test Results The test configurations described in Section 2.1 were used to simulate point-to-point simplex, parallel-terminated point-to-point simplex, and two-nodemultipoint. The test results are shown in the following figures. A TektronixHFS9003 was used to generate...
Page 22 - due to the lower load seen by the; Figure 2−6. Two-Node Multipoint Typical Eye Pattern Data
Test Results 2-6 Test Setup signal on TP1, R2 is shorted. Type-2 behavior is again observed on theSN65MLVD207 receiver output. Trace three shows the differential voltage on the bus. Note that the bus volt-ages are nominal M-LVDS levels of 1.1 V PP due to the lower load seen by the current driver. Fi...
Page 23 - Bill of Materials, Board Layout, and PCB Construction; Construction; Chapter 3
3-1 Bill of Materials, Board Layout, and PCB Construction Bill of Materials, Board Layout, and PCB Construction This chapter contains the bill of materials, board layout of the M-LVDS, anddescribes the printed-circuit board. Topic Page 2.1 Bill of Materials 3-2 . . . . . . . . . . . . . . . . . . . ...
Page 25 - Board Layout; Figure 3−1. Assembly Drawing; Figure 3−2. Top Layer
Board Layout 3-3 Bill of Materials, Board Layout, and PCB Construction 3.2 Board Layout Figure 3−1. Assembly Drawing GND01 VCC01 VCC GND VCC01 GND01 GND VCC VCC GND GND01 VCC01 TEXAS INSTRUMENTS A/W NO. # 6424409BPWA. EVM.SN65MLVDSERIAL NO. MADE IN U.S.A. GND VCC VCC01 GND01 GND01 VCC01 GND VCC U1 J...
Page 26 - Figure 3−3. Second Layer
Board Layout 3-4 Bill of Materials, Board Layout, and PCB Construction The second layer of the EVM has the separate ground planes. These are thereference planes for the controlled impedance traces on the top layer. Figure 3−3. Second Layer ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ...
Page 27 - Figure 3−5. Bottom Layer
Board Layout 3-5 Bill of Materials, Board Layout, and PCB Construction The bottom layer of the EVM contains bulk and decoupling capacitors to beplaced close to the power and ground pins on the device. Figure 3−5. Bottom Layer C9 C8 C7 C5 C4 C3 C10 C6 C2 C1 VCC GND VCC01 GND01
Page 28 - PCB Construction; ln; ln
PCB Construction 3-6 Bill of Materials, Board Layout, and PCB Construction 3.3 PCB Construction Information in this section was obtained from the following source: - Electromagnetic Compatibility Printed Circuit Board and ElectronicModule Design, VEC workshop, Violette Engineering Corporation. Chara...
Page 29 - Figure 3−6. Trace Configurations in Printed-Circuit Boards; MICROSTRIP; Board
PCB Construction 3-7 Bill of Materials, Board Layout, and PCB Construction Figure 3−6. Trace Configurations in Printed-Circuit Boards MICROSTRIP STRIPLINE Board Material W h t W t W S Stripline construction is the preferred configuration for differential signaling.This configuration reduces radiated...
Page 30 - Table 3−2. EVM Layer Stack Up
PCB Construction 3-8 Bill of Materials, Board Layout, and PCB Construction Table 3−2 shows the layer stack up of the EVM with the defined trace widthsfor the controlled impedance etch runs using microstrip construction. Table 3−2. EVM Layer Stack Up Differential Model Single-Ended Model Material Typ...
Page 31 - Schematic; This Appendix contains the EVM schematic.; Appendix A
A-1 Schematic Schematic This Appendix contains the EVM schematic. Appendix A
