Transcend TS4G-32GSDHC6-P2 - Manuals

Page 2 - SDHC Memory Card + Reader P2; Transcend Information Inc.

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 2 Architecture

Page 3 - General

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 3 Bus Operating Conditions • General Parameter Symbol Min. Max. Unit Remark Peak voltage on all lines -0.3 V DD +0.3 V All Inputs Input Leakage Curr...

Page 5 - Bus Signal Levels; Parameter

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 5 • Bus Signal Levels As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. To meet the re...

Page 6 - Bus Timing

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 6 • Bus Timing Parameter Symbol Min Max. Unit Remark Clock CLK (All values are referred to min (V IH ) and max (V IL ) Clock frequency Data Transfer...

Page 7 - Output Delay time during Data Transfer Mode; ns; ns

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 7 Output Delay time during Data Transfer Mode t ODLY 0 14 ns C L ≤ 40 pF, (1 card) Output Delay time during Identification Mode t ODLY 0 50 ns C L ≤...

Page 11 - The OCR register shall be implemented by the cards.

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 11 Register Information Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only by correspo...

Page 12 - OCR Register Definition; MID

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 12 OCR Register Definition 1) This bit is valid only when the card power up status bit is set. 2) This bit is set to LOW if the card has not finishe...

Page 15 - CSD Register Structure; TAAC

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 15 CSD Register Structure • TAAC This field is fixed to 0Eh, which indicates 1 ms. The host should not use TAAC, NSAC, and R2W_FACTOR to calculate t...

Page 20 - SCR Register Structure Version

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 20 is 0x404. 6. SCR Register In addition to the CSD register there is another configuration register that named - SD CARD Configuration Register (SC...

Page 21 - SD Supported Security Algorithm

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 21 Defines the data status after erase, whether it is ‘0’ or ‘1’ (the status is card vendor dependent). • SD_SECURITY Describes the security algorit...

Page 22 - Mechanical Dimension

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information Inc. 22 Mechanical Dimension

Page 26 - Pin Identification; Block Diagram

T T T S S S 4 4 4 G G G - - - 3 3 3 2 2 2 G G G S S S D D D H H H C C C 6 6 6 - - - P P P 2 2 2 SDHC Memory Card + Reader P2 Transcend Information, Inc. 26 Pinouts Pin No. Pin Name 01 V USB 02 USB- 03 USB+ 04 VSS Pin Identification Symbol Function USB- USB+ USB differential signal: The pairs are use...