Page 2 - Table of Contents
Table of Contents TLCS-900/H1 Devices TMP92CZ26A 1. Outline and Features ････････････････････････････････････････ 92CZ26A-1 2. Pin Assignment and Pin Functions ････････････････････････････ 92CZ26A-6 2.1 Pin Assignment Diagram ････････････････････････････････ 92CZ26A-6 2.2 Pin names and Functions ･･･...
Page 4 - CMOS 32-Bit Micro controllers; Outline and Features
TMP92CZ26A 92CZ26A-1 CMOS 32-Bit Micro controllers TMP92CZ26AXBG 1. Outline and Features TMP92CZ26A is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CZ26AXBG is housed in a 228-pin BGA package. (1) CPU : 32-bit CPU(High-speed 900/H1 C...
Page 5 - Separate bus system
TMP92CZ26A 92CZ26A-2 (4) External memory expansion • Expandable up to 3.1G bytes (shared program/data area) • Can simultaneously support 8/16-bit width external data bus …… Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output : 4 channel • One channel in 4 channel...
Page 9 - Pin Assignment and Pin Functions; OPEN check of mounting if mounting this LSI to Target board.
TMP92CZ26A 92CZ26A-6 2. Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CZ26A, their names and functions are as follows; 2.1 Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CZ26A. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A...
Page 11 - Pin names and Functions
TMP92CZ26A 92CZ26A-8 2.2 Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/6) Pin name Number of Pins I/O Functions D0 to D7 8 I/O Data: Data bus D0 to D7. P10 to P17 D8 to D15 8 I/O I/O Port 1: I/O port. Input ...
Page 17 - Outline; Outline is as follows:
TMP92CZ26A 92CZ26A-14 3. Operation This section describes the basic components, functions and operation of the TMP92CZ26A. 3.1 CPU The TMP92CZ26A contains an advanced high-speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CP...
Page 18 - Operation
TMP92CZ26A 92CZ26A-15 3.1.2 Reset Operation When resetting the TMP92CZ26A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 20 system clocks (32µs at ...
Page 21 - Set AM1 and AM0 pins as Table 3.1.2 shows according to system usage.; Mode Setup input pin; DBGE; Operation Mode; 6-bit external bus starting
TMP92CZ26A 92CZ26A-18 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as Table 3.1.2 shows according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup input pin RESET AM1 AM0 DBGE Operation Mode 0 Debug mode 0 1 1 16-bit external bus starting 0 1 0 1 Test mode (Prohibit to set) 0 ...
Page 23 - Clock Function and Standby Function; circuit
TMP92CZ26A 92CZ26A-20 3.3 Clock Function and Standby Function TMP92CZ26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4) noise-reducing circuit. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock ...
Page 24 - Figure 3.3.1 System clock block diagram
TMP92CZ26A 92CZ26A-21 The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.3.1 shows a transition figure. Reset (f OSCH /16) release Reset instruction interrupt STOP mode (Stops all circuits) PLL-OFF mode (f OSCH /gear value) IDLE...
Page 25 - Figure 3.3.2 Block Diagram of System clock
TMP92CZ26A 92CZ26A-22 3.3.1 Block diagram of system clock Clock gear SYSCR0<PRCK> fs f OSCH Low frequency Oscillator circuit XT1 XT2 SYSCR0<XTEN > Warming up timer (High/Low frequency oscillator circuit) SYSCR0<WUEF> SYSCR2<WUPTM1:0> X1 X2 ÷ 2 ÷ 16 ÷ 4 fc/16 fc/8 fc/4 fc/2 fc...
Page 26 - System; USB
TMP92CZ26A 92CZ26A-23 TMP92CZ26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1). Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz. Don’t connect oscillator more than10MHz. When clock is input by using external oscillator, range of inp...
Page 29 - This register is used to set each pin-status at stand-by mode.
TMP92CZ26A 92CZ26A-26 7 6 5 4 3 2 1 0 bit symbol FCSEL LUPFG Read/Write R/W R After reset 0 0 Function Select fc-clock 0 : f OSCH 1 : f PLL Lock-up timer Status flag 0 : not end 1 : end Note: Be carefull that logic of PLLCR0<LUPFG> is different from 900/L1’s DFM. 7 6 5 4 3 2 1 0 bit symbol PLL...
Page 30 - The system clock controller generates the system clock signal (f; ) for the CPU core and; Clock gear controller; reduces power consumption.
TMP92CZ26A 92CZ26A-27 3.3.3 System clock controller The system clock controller generates the system clock signal (f SYS ) for the CPU core and internal I/O. SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator. SYSCR1<GEAR2:0> sets the high frequency cloc...
Page 31 - when using PLL and clock gear at f; at f; Frequency of f
TMP92CZ26A 92CZ26A-28 3.3.4 Clock doubler (PLL) PLL0 outputs the f PLL clock signal, which is 12 or 16 times as fast as f OSCH . That is, the low-speed frequency oscillator can be used as external oscillator, even though the internal clock is high-frequency. Since Reset initializes PLL0 to stop stat...
Page 34 - resonator; X2 pin; to 10MHz condition.
TMP92CZ26A 92CZ26A-31 3.3.5 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator circuit (2) Reduced drivability for low-frequency oscillator circuit (3) Single drive for high-frequenc...
Page 46 - ROM; kinds of downloading methods.; Modes; is
TMP92CZ26A 92CZ26A-43 3.4 Boot ROM The TMP92CZ26A contains boot ROM for downloading a user program, and supports two kinds of downloading methods. 3.4.1 Operation Modes The TMP92CZ26A has two operation modes: MULTI mode and BOOT mode. The operation mode is selected according to the AM1 and AM0 pin l...
Page 47 - Hardware Specifications of Internal Boot ROM; (2) Switching the boot ROM area to an external area
TMP92CZ26A 92CZ26A-44 3.4.2 Hardware Specifications of Internal Boot ROM (1) Memory map Figure 3.4.1 shows a memory map of BOOT mode. The boot ROM incorporated in the TMP92CZ26A is an 8-Kbyte ROM area mapped to addresses 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and the above are...
Page 48 - Outline of Boot Operation; Figure 3.4.2 Flowchart for Internal Boot ROM Operation; Clock setting
TMP92CZ26A 92CZ26A-45 3.4.3 Outline of Boot Operation The method for downloading a user program can be selected from two types: from UART, or via USB. After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2. Regardless of the downloading method used, the boot program...
Page 49 - Figure 3.4.3 How the Boot Program Uses Internal RAM
TMP92CZ26A 92CZ26A-46 Figure 3.4.3 How the Boot Program Uses Internal RAM Work Area for Boot Program (4 Kbytes) Download Area for User Program (282 Kbytes) Stack Area for Boot Program (2 Kbytes) 002000H 049800H 003000H 049FFFH
Page 53 - Downloading a User Program via UART; PC must also be set up with the same conditions.
TMP92CZ26A 92CZ26A-50 3.4.4 Downloading a User Program via UART (1) Connection example Figure 3.4.4 shows an example of connections for downloading a user program via UART (using a 16-bit NOR Flash memory device as program memory). Note: When USB is not used, add a pull-up or pull-down resistor to t...
Page 55 - Table 3.4.8 Baud Rate Modification Command; Table 3.4.10 Version Management Information
TMP92CZ26A 92CZ26A-52 Table 3.4.8 Baud Rate Modification Command Baud Rate (bps) 9600 19200 38400 57600 115200 Modification Command 28H 18H 07H 06H 03H Note 1: If f OSCH (oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported. Note 2: If f OSCH (oscillation frequency) is 6.00, 8....
Page 56 - If the received baud rate data does not correspond to the
TMP92CZ26A 92CZ26A-53 the baud rate is not changed, the initial baud rate data (28H: 9600 bps) must be sent. Baud rate modification becomes effective after the echo back transmission is completed. 8. The 9th byte is used to echo back the received data to the PC when the data received in the 8th byte...
Page 60 - CTS
TMP92CZ26A 92CZ26A-57 (5) Others a) Handshake function Although the CTS pin is available in the TMP92CZ26A, the boot program does not use it for transfer control. b) RS-232C connector The RS-232C connector must not be connected or disconnected while the boot program is running. c) Software on the PC...
Page 61 - Downloading a User Program via USB; The boot program uses the following two transfer types.
TMP92CZ26A 92CZ26A-58 3.4.5 Downloading a User Program via USB (1) Connection example Figure 3.4.5 shows an example of connections for downloading a user program via USB (using a 16-bit NOR Flash memory device as program memory). Note 1: The value of pull-up and pull-down resistors are recommended v...
Page 62 - The following shows an overview of the USB communication flow.
TMP92CZ26A 92CZ26A-59 The following shows an overview of the USB communication flow. Figure 3.4.6 Overall Flowchart Host (PC) Connection Recognition Send GET_DISCRIPTOR Send DESCRIPTOR information Send the microcontroller information command Send microcontroller information data Check data Data Tran...
Page 63 - Table 3.4.16 Setup Command Data Structure; Field Name
TMP92CZ26A 92CZ26A-60 Table 3.4.15 Vendor Request Commands Command Name Value of bRequest Operation Notes Microcontroller information command 00H Send microcontroller information Microcontroller information data is sent by bulk IN transfer after the setup stage is completed. User program transfer st...
Page 64 - DeviceDescriptor
TMP92CZ26A 92CZ26A-61 Table 3.4.17 Standard Request Commands Standard Request Response Method GET_STATUS Automatic response by hardware CLEAR_FEATURE Automatic response by hardware SET_FEATURE Automatic response by hardware SET_ADDRESS Automatic response by hardware GET_DISCRIPTOR Automatic response...
Page 68 - transferred first does not have to be an address record.
TMP92CZ26A 92CZ26A-65 b. Notes on the user program format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for “:”) of the next record. If data other than 3AH is received between records, it is ignored. 2. Since the address pointer is initially set...
Page 71 - Figure 3.5.1 Interrupt processing Sequence
TMP92CZ26A 92CZ26A-68 Figure 3.5.1 Interrupt processing Sequence Interrupt processing Interrupt vector calue “V” read interrupt request F/F clear Interrupt specified by DMA start vector ? PUSH PC PUSH SR SR<IFF2:0> ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 PC ← (FFFF00H + V) Inte...
Page 75 - the micro DMA burst function in the following.
TMP92CZ26A 92CZ26A-72 3.5.2 Micro DMA processing In addition to general-purpose interrupt processing, the TMP92CZ26A also includes a micro DMA function and HDMA function. This section explains about Micro DMA function. For the HDMA function, please refer 3.23 DMA controller. Micro DMA processing for...
Page 76 - cleared by micro DMA that priority is highest); src; dst; Figure 3.5.2 Timing for micro DMA cycle
TMP92CZ26A 92CZ26A-73 If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 7 the lowest). Not...
Page 77 - Symbol; Transfer control registers
TMP92CZ26A 92CZ26A-74 (2) Soft start function The TMP92CZ26A can initiate micro DMA/HDMA either with an interrupt or by using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is initiated by a Write cycle which writes to the register DMAR. Writing “1” to each bit of DMAR register ...
Page 80 - Figure 3.5.3 Block Diagram of Interrupt Controller
TMP92CZ26A 92CZ26A-77 In terru p t requ e s t s ign al to C P U IF F ＝ 7 then 0 M ic ro D M A/ H D M A s tar t v e ct or s e tt in g re gi st er IN TT C4 /INT D M A 4 IN TT C5 /INT D M A 5 IN TT C6 IN TT C7 V = E0H V = E4H V = E8H V = ECH So ft sta rt Micro DM A /H D M A c o unt er 0 inte rru pt 6 I...
Page 81 - Interrupt priority setting registers
TMP92CZ26A 92CZ26A-78 (1) Interrupt priority setting registers Symbol Name Address 7 6 5 4 3 2 1 0 − INT0 − − − − I0C I0M2 I0M1 I0M0 R R/W R R/W INTE0 INT0 enable F0H Always write “0”. 0 0 0 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W INTE12 INT1 & INT2 enable D0H 0 0 0 0 0 0 0...
Page 82 - INTSPITX INTSPIRX
TMP92CZ26A 92CZ26A-79 Symbol Name Address 7 6 5 4 3 2 1 0 INTTB01 (TMRB0) INTTB00 (TMRB0) ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M2 ITB00M1 ITB00M0 R R/W R R/W INTETB0 INTTB00 & INTTB01 enable D8H 0 0 0 0 0 0 0 0 INTTB11 (TMRB1) INTTB10 (TMRB1) ITB11C ITB11M2 ITB11M1 ITB11M0 ITB10C ITB10M2 I...
Page 85 - External interrupt control
TMP92CZ26A 92CZ26A-82 (2) External interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE − W W W W W W R/W R/W 0 0 0 0 0 0 0 0 IIMC0 Interrupt input mode control 0 F6H (Prohibit RMW) INT5EDGE 0: Rising 1: Falling INT4EDGE 0: Rising 1: Falling INT3EDGE 0...
Page 88 - Micro DMA/HDMA select register
TMP92CZ26A 92CZ26A-85 Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start vector 100H DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 R/W 0 0 0 0 0 0 DMA1V DMA1 start vector 101H DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2...
Page 89 - Specification of a micro DMA burst
TMP92CZ26A 92CZ26A-86 (7) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches “0”. Setting any of the bits in the register DMAB which correspond to a micro DMA channel...
Page 92 - Diagram; CPU; LCD Controller
TMP92CZ26A 92CZ26A-89 3.6.1 Block Diagram Figure 3.6.1 shows an overall block diagram for the DMAC. Note: “n” denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5). Figure 3.6.1 Overall Block Diagram DMAnV DMAR → DMAC or micro DMA request source setting → ...
Page 93 - SFRs; HDMASn (DMA Transfer Source Address Setting Register); HDMASn Register
TMP92CZ26A 92CZ26A-90 3.6.2 SFRs The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit data bus. (1) HDMASn (DMA Transfer Source Address Setting Register) The HDMASn register is used to set the DMA transfer source address. When the source address is updated by DMA ex...
Page 100 - Bus arbitration
TMP92CZ26A 92CZ26A-97 ZZ12H 1234H 400001H 400000H 800000H D15 ∼ D0 SRLLB SRLUB SRWR RD A23 ∼ A0 1 CS busak busrq int_xx SDCLK DMAC/read DMAC/write CPU execution cycle Undefined after interrupt request is asserted until DMAC read cycle is started ZZ34H CPU execution cycle 2 CS (2) Bus arbitration The...
Page 101 - Transferring music data from internal RAM to I2S by DMA transfer; No Instruction
TMP92CZ26A 92CZ26A-98 3.6.4 Setting Example This section explains how to set the DMAC using an example. (1) Transferring music data from internal RAM to I2S by DMA transfer The 32 Kbytes of data stored in the internal RAM at addresses 2000H to 9FFFH shall be transferred to FIFO-RAM via I2S. Each tim...
Page 103 - Considerations for Using More Than One Bus Master; number of channels to be used.; Transfer count
TMP92CZ26A 92CZ26A-100 3.6.6 Considerations for Using More Than One Bus Master In the TMP92CZ26A, the LCD controller, SDRAM controller, and DMA controller may act as the bus master apart from the CPU. Therefore, care must be exercised to enable each of these functions to operate smoothly. To facilit...
Page 104 - Sample 1) Calculation example for CPU + HDMA; Calculation example:
TMP92CZ26A 92CZ26A-101 Sample 1) Calculation example for CPU + HDMA Conditions: CPU operation speed (f SYS ) : 60 MHz I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz) I2S data transfer bit length : 16 bits DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S Calculation example: ...
Page 106 - Calculation example 1:
TMP92CZ26A 92CZ26A-103 Sample2) Calculation examples for CPU + LDMA Conditions 1: CPU operation speed (f SYS ) : 60 MHz Display RAM : Internal RAM Display size : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy cycles) Calculation example...
Page 109 - LHSYNC
TMP92CZ26A 92CZ26A-106 (4) CPU + LDMA + ARDMA + HDMA This is a case in which all the bus masters are active at the same time. Since the LCD display function cannot work properly if the LCD controller cannot perform LDMA properly, the priorities among the four bus masters should be set in the order o...
Page 111 - HDMATR Register; HDMATR
TMP92CZ26A 92CZ26A-108 HDMATR Register 7 6 5 4 3 2 1 0 bit Symbol DMATE DMATR6 DMATR5 DMATR4 DMATR3 DMATR2 DMATR1 DMATR0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Timer operation 0: Disable 1: Enable Maximum bus occupancy time setting The value to be set in <DMATR6:0> should be obtai...
Page 113 - Function of ports
TMP92CZ26A 92CZ26A-110 3.7 Function of ports TMP92CZ26A has I/O port pins that are shown in Table 3.7.1 in addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.7.2 lists I/O registers and their specifications. Table 3.7.1 Port Func...
Page 124 - Each bit
TMP92CZ26A 92CZ26A-121 3.7.3 Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit can be set individually for function. Setting the AM1 and AM0 pins as shown below...
Page 126 - device initialize port 6 to the following function pins:
TMP92CZ26A 92CZ26A-123 3.7.4 Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs and function by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port6 can also function a...
Page 128 - NDRE; WRLL; NDWE
TMP92CZ26A 92CZ26A-125 3.7.5 Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76...
Page 129 - NDR; WAIT
TMP92CZ26A 92CZ26A-126 Figure 3.7.10 Port7 Read data P7 register S 1 0 Selector P7CR register P7FC register S 0 1 Selector P73 (EA24) P74 (EA25) EA24, EA25 Selector P7 register Port read data P7CR register P7FC register S 1 0 S 0 1 NDR/ B P75(R/W, B / NDR ) R/W Selector P76 ( WAIT ) P7 register P7CR...
Page 133 - Resetting resets the P9FC to “0”, and sets all bits to input ports.
TMP92CZ26A 92CZ26A-130 3.7.7 Port 9 (P90 to P92, P96, P97) P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets P90 to P92 to input port and all bits of output latch to”1”. P96 to P97 are 2-bit general-purpose input port. Writing “1” i...
Page 136 - generated. INTKEY interrupt can release all HALT mode.
TMP92CZ26A 92CZ26A-133 3.7.8 Port A (PA0 to PA7) Port A0 to A7 are 8-bit general-purpose input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, port A0 to A7 can also Key-on wake-up function as Keyboard interface. The various functions can each be enabled by writ...
Page 138 - it with IIMC register, which there is in interruption controller.
TMP92CZ26A 92CZ26A-135 3.7.9 Port C (PC0 to PC7) PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port C to an input port. It also sets all bits of the output latch register to “1”. In addition to functioning as a general-purpose I/O...
Page 142 - PF7 to be a SDCLK output port.
TMP92CZ26A 92CZ26A-139 3.7.10 Port F (PF0 to PF5, PF7) Port F0 to F5 are 6-bit general-purpose I/O ports. Resetting sets PF0 to PF5 to be input ports. It also sets all bits of the output latch register to “1”. In addition to functioning as general-purpose I/O port pins, PF0 to PF5 can also function ...
Page 144 - output port, PF7 can also function as the SDCLK output.
TMP92CZ26A 92CZ26A-141 (2) Port F7 (SDCLK), Port F7 is general-purpose output port. In addition to functioning as general-purpose output port, PF7 can also function as the SDCLK output. Figure 3.7.27 Port F7 SDCLK Selector A B S PF7(SDCLK) PF read Function control (on bit basis) PFFC write S Outpu...
Page 146 - PG2, PG3 can also be used as MX, MY pin for Touch screen interface.
TMP92CZ26A 92CZ26A-143 3.7.11 Port G (PG0 to PG5) PG0 to PG5 are 6-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. PG2, PG3 can also be used as MX, MY pin for Touch screen interface. (PG) register is ...
Page 148 - Port J also functions as output pins for SDRAM (; SDRAS; SDCAS; SRWR; and; SRLUB; and NDCLE). Above setting is used the function register PJFC.
TMP92CZ26A 92CZ26A-145 3.7.12 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as port, Port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDW...
Page 151 - Above setting is used the function register PKFC.
TMP92CZ26A 92CZ26A-148 3.7.13 Port K (PK0 to PK7) PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to PK7 pins output “0”. In addition to functioning as output port function, Port K also function as output pins for LCD controller (LCP0, LHSYNC, LLOAD, LFR, LVSYNC...
Page 153 - function register PLFC.
TMP92CZ26A 92CZ26A-150 3.7.14 Port L (PL0 to PL7) PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL7 pins output “0”. In addition to functioning as a general-purpose output port, Port L can also function as a data bus for LCD controller (LD0 to LD7). Above s...
Page 155 - Above setting is used the function register PMFC.; ALARM
TMP92CZ26A 92CZ26A-152 3.7.15 Port M (PM1, PM2, PM7) PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to “1”, and PM1, PM2 and PM7 pins output “1”. In addition to functioning as output ports, Port M also function as output pin for timers (TA1OUT), output pins for RTC alarm...
Page 160 - interruption controller.
TMP92CZ26A 92CZ26A-157 3.7.17 Port P (PP1 to PP7) Port P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port P1 to P5 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, P0 to P5 can als...
Page 177 - and function register PXFC.
TMP92CZ26A 92CZ26A-174 3.7.23 Port X (PX4, PX5 and PX7) Port X5 and X7 are 2-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port X5 and X7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PX5 and ...
Page 180 - is set to “0”, this port set to debug communication function.); Debug mode
TMP92CZ26A 92CZ26A-177 3.7.24 Port Z (PZ0 to PZ7) Port Z0 to Z7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port Z0 to Z7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port function, Port Z can a...
Page 184 - Control register and Operation after reset release; release and necessary settings.
TMP92CZ26A 92CZ26A-181 3.8.2 Control register and Operation after reset release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control Register The control registers of the memory controller are as follows and Table 3....
Page 187 - bus width of the control register in the block address area 2.
TMP92CZ26A 92CZ26A-184 (2) Operation after releasing reset The data bus width at starting is determined depending on state of AM1/AM0 pins after releasing reset. Then, the external memory access as follows; Note: A memory to be used to start after releasing reset is either NOR-Flash or Masked-ROM.NA...
Page 188 - Basic functions and register setting; of waits out of the memory controller’s functions are described.
TMP92CZ26A 92CZ26A-185 3.8.3 Basic functions and register setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address areas of CS0 to CS3 are s...
Page 191 - Table 3.8.3 Valid Area Sizes for Each CS Area; register combinations.
TMP92CZ26A 92CZ26A-188 Table 3.8.3 Valid Area Sizes for Each CS Area Size (Byte) CS area 256 512 32 K 64 K 128 K 256 K 512 K 1 M 2 M 4 M 8 M CS0 ○ ○ ○ ○ Δ Δ Δ Δ Δ CS1 ○ ○ ○ Δ Δ Δ Δ Δ Δ CS2 ○ ○ Δ Δ Δ Δ Δ Δ Δ CS3 ○ ○ Δ Δ Δ Δ Δ Δ Δ Note:“ Δ ” indicates areas that cannot be set by memory start address r...
Page 192 - Data Bus Width Specification
TMP92CZ26A 92CZ26A-189 (2) Connection Memory Specification Setting BnCSH<BnOM1:0> specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows; BnCSH<BnOM1:0> BnOM1 BnOM0 Function 0 0 SRAM/ROM (Default) 0 1 ...
Page 194 - Function; pin input mode
TMP92CZ26A 92CZ26A-191 (4) Wait control The external bus cycle completes for two states minimum(25 ns at f SYS = 80 MHz). Setting the BnCSL<BnWW3:0> specifies the number of waits in the write cycle, and BnCSL<BnWR3:0> specifies the number of waits in the read cycle. <BnWW3:0> is se...
Page 195 - Some memory have an AC specification about data hold time from; CE; or; OE; for read
TMP92CZ26A 92CZ26A-192 (5) Recovery (Data hold) cycle control Some memory have an AC specification about data hold time from CE or OE for read cycle and a data confliction problem may occur. To avoid this problem, 1-dummy cycle can be inserted after CSm-block access cycle by setting “1” to BmCSH<...
Page 197 - CSn; Tn; WRxx; TW
TMP92CZ26A 92CZ26A-194 RDTMGCR0/1<BnTCRS1:0> 00 TCRS = 0.5 × f SYS (Default) 01 TCRS = 1.5 × f SYS 10 TCRS = 2.5 × f SYS 11 TCRS = 3.5 × f SYS TCRS:The delay from (CSn) to (RD,SRxxB). Note: TW cycle is inserted by setting BnCSL register. If it is set to 0-Wait, TW cycle is not inserted. A23 to...
Page 198 - Basic bus timing
TMP92CZ26A 92CZ26A-195 (7) Basic bus timing (a) External read/write cycle (0 waits) (b) External read/write cycle (1 wait) CSn WRxx RD , SRxxB A23 to A0 Input Output Read Write SDCLK (60 MHz) D15 to D0 D15 to D0 T1 T2 SRWR , SRxxB CSn WRxx RD , SRxxB A23 to A0 Output SDCLK (60 MHz) D15 to D0 D15 to ...
Page 199 - External read bus cycle (1 wait; External write bus cycle (1 wait
TMP92CZ26A 92CZ26A-196 (c) External read bus cycle (1 wait + TAC: 1f SYS + TCRS: 1.5f SYS + TCRH: 1f SYS ) External write bus cycle (1 wait + TAC: 1f SYS + TCWS/H: 1.5f SYS ) (d) External read/write cycle (4 waits + WAIT pin input mode) Read T1 T6 Input Output Write T2 T3 T4 T5 TAC TAC TCRS TCRH TCW...
Page 200 - External read bus cycle (4 waits; External write bus cycle (4 waits
TMP92CZ26A 92CZ26A-197 (e) External read/write cycle (4 waits + WAIT pin input mode) (f) External read bus cycle (4 waits + WAIT pin input mode + TAC: 1f SYS + TCRS: 1.5f SYS + TCRH: 1f SYS ) External write bus cycle (4 waits + WAIT pin input mode + TAC: 1f SYS + TCWS/H: 1.5f SYS ) Sampling Read T1 ...
Page 201 - Connecting to external memory
TMP92CZ26A 92CZ26A-198 (8) Connecting to external memory Figure 3.8.4 shows an example of how to connect external 16-bit SRAM and 16-bit NOR flash to the TMP92CZ26A. Figure 3.8.4 Example of External 16-Bit SRAM and NOR Flash Connection TMP92CZ26A 16-bit SRAM RD SRLLB SRLUB SRWR 0 CS D [15:0] A0 A1 A...
Page 203 - Boot ROM memory map
TMP92CZ26A 92CZ26A-200 3.8.5 Internal Boot ROM Control This section describes about built-in boot ROM. For the specification of S/W in boot ROM, refer to the section 3.4 boot ROM. (1) BOOT mode BOOT mode is started by following AM1 and AM0 pins condition with reset. AM1 AM0 Start mode 0 0 Don’t use ...
Page 205 - Figure 3.8.6 Read Signal Delay Read Cycle
TMP92CZ26A 92CZ26A-202 3.8.6 Cautions (1) Note the timing between CS and RD If the load capacitance of the RD (Read signal) is greater than that of the CS (Chip select signal), it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may ca...
Page 211 - register
TMP92CZ26A 92CZ26A-208 3.9.2 Control register There are 24-registers for MMU. They are prepared for 8-purpose using (as Program, read-data, write-data and LCDC-display-data, source-data for odd/even number channel DMA, destination-data for odd/even number channel DMA), and 3-local area (LOCAL-X, Y a...
Page 213 - LCD display bank register
TMP92CZ26A 92CZ26A-210 3.9.2.2 LCD display bank register The bank page used as LCD display memory is set to these registers. Since the bank register for CPU and LCDC are prepared independently, the bank page for CPU (Program, Read-data, write-data) can change during LCD display on. LOCAL-X register ...
Page 221 - example; This is in case of using like following condition.
TMP92CZ26A 92CZ26A-218 3.9.3 Setting example This is in case of using like following condition. No. Used as Memory Setting MMU-area Logical address Physical address (a) Main Routine COMMON-Z C00000H to FFFFFFH (b) Character- ROM NOR-Flash (16MB, 1pcs) CSZA , 32bit, 1wait Bank0 in LOCAL-Z 800000H to ...
Page 224 - The SDRAMC has the following control registers.
TMP92CZ26A 92CZ26A-221 3.10.1 Control Registers The SDRAMC has the following control registers. SDRAM Access Control Register 7 6 5 4 3 2 1 0 Bit symbol SRDS – SMUXW1 SMUXW0 SPRE SMAC Read/Write R/W R/W After reset 1 0 0 0 0 0 Function Read data shift function 0: Disable 1: Enable Always write “0” A...
Page 232 - Read data shift function
TMP92CZ26A 92CZ26A-229 (4) Read data shift function If the AC specifications of the SDRAM cannot be satisfied when data is read from the SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in the next state. When this read data shift function is used, the read cyc...
Page 234 - Auto Refresh Cycle Timing; Auto; states
TMP92CZ26A 92CZ26A-231 (6) Refresh control The TMP92CZ26A supports two kinds of refresh commands: Auto Refresh and Self Refresh. (a) Auto Refresh When SDRCR<SRC> is set to “1”, the Auto Refresh command is automatically issued at intervals specified by SDRCR<SRS2:0>. The Auto Refresh inte...
Page 235 - SDWE
TMP92CZ26A 92CZ26A-232 (b) Self Refresh The Self Refresh Entry command is issued by setting SDCMM<SCMM2:0> to “101”. Figure3.10.7 shows the Self Refresh cycle timing. Once Self Refresh is started, the SDRAM is refreshed internally without the need to issue the Auto Refresh command. Note 1: Whe...
Page 236 - Gear down; Gear up
TMP92CZ26A 92CZ26A-233 The Self Refresh state can be exited by the Self Refresh Exit command. The Self Refresh Exit command is executed when SDCMM<SCMM2:0> is set to “110”. It is also executed automatically in synchronization with HALT mode release. In either of these two cases, Auto Refresh i...
Page 238 - Data Bus Width 16 bits
TMP92CZ26A 92CZ26A-235 (8) Connection example Figure3.10.10 shows an example of connections between the TMP92CZ26A and SDRAM. Table3.10.4 Pin Connections SDRAM Pin Name Data Bus Width 16 bits 92CZ26A Pin Name 16M 64M 128M 256M 512M A0 A0 A0 A0 A0 A0 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A3 A3 A3 A3 A3...
Page 239 - An Example of Calculating HDMA Transfer Time
TMP92CZ26A 92CZ26A-236 3.10.3 An Example of Calculating HDMA Transfer Time The following shows an example of calculating the HDMA transfer time when SDRAM is used as the transfer source. 1) Transfer from SDRAM to internal SRAM Conditions: System clock (f SYS ) : 60 MHz SDRAM read cycle : Full page (...
Page 240 - Considerations for Using the SDRAMC
TMP92CZ26A 92CZ26A-237 3.10.4 Considerations for Using the SDRAMC This section describes the points that must be taken into account when using the SDRAMC. Please carefully read the following to ensure proper use of the SDRAMC. 1) WAIT access When SDRAM is used, the following restriction applies to m...
Page 242 - Figure 3.11.1 Block Diagram for NAND Flash Controller; Internal Dat
TMP92CZ26A 92CZ26A-239 3.11.1 Block Diagram Figure 3.11.1 Block Diagram for NAND Flash Controller ND_CE* ND_RE * ND_ALE ND_CLE ND WE * ND_RB * DATA_IN[15:0] NAND Flash Controller Channel 0 (NDFC0) DATA_OUT[15:0] NDCLE, NDALE, NDRE , NDWE , D15~ D0 D15~D0, NDR/B CE 0 ND Internal Dat a Bus Reed-Solomo...
Page 243 - Description; pins must be controlled by software.
TMP92CZ26A 92CZ26A-240 3.11.2 Operation Description 3.11.2.1 Accessing NAND Flash Memory The NDFC accesses data on NAND Flash memory indirectly through its internal registers. This section explains the operations for accessing the NAND Flash. Since no dedicated sequencer is provided for generating c...
Page 245 - Control; Figure 3.11.4 Basic Flow of ECC Control; END
TMP92CZ26A 92CZ26A-242 3.11.3 ECC Control NAND Flash memory devices may inherently include error bits. It is therefore necessary to implement the error correction processing using ECC (Error Correction Code). Figure 3.11.4 shows a basic flowchart for ECC control. Figure 3.11.4 Basic Flow of ECC Cont...
Page 246 - Hamming Reed-Solomon
TMP92CZ26A 92CZ26A-243 3.11.3.1 Differences between Hamming Codes and Reed-Solomon Codes The NDFC includes an ECC generator supporting NAND Flash memory devices of SLC (or 2LC: two states) type and MLC (or 4LC: four states) type. The ECC calculation using Hamming codes (supporting SLC) generates 22 ...
Page 248 - several times to cover the entire page.
TMP92CZ26A 92CZ26A-245 Reed-Solomon ECC • The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated several times to cover the entire page. • Basically no ...
Page 249 - NAND Flash Control 0 Register; Figure 3.11.5 NAND Flash Mode Control 0 Register
TMP92CZ26A 92CZ26A-246 3.11.4 Description of Registers NAND Flash Control 0 Register 7 6 5 4 3 2 1 0 bit Symbol WE ALE CLE CE0 CE1 ECCE BUSY ECCRST Read/Write R/W R/W R/W R/W R/W R/W R W After reset 0 0 0 0 0 0 0 0 Function WE enable 0: Disable 1: Enable ALE control 0: “L” out 1: “H” out CLE control...
Page 250 - instructions or the like.; bit should be set to “0”.
TMP92CZ26A 92CZ26A-247 (c) <ECCE> The <ECCE> bit is used for both Hamming and Reed-Solomon codes. This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC generator (to set <ECCRST> to “1”), the ECC generator must be enabled (<ECCE> = “1”). (d) <...
Page 252 - NAND Flash Control 1 Register; bits). No other setting is required in the memory controller.
TMP92CZ26A 92CZ26A-249 NAND Flash Control 1 Register 7 6 5 4 3 2 1 0 bit Symbol INTERDY INTRSC BUSW ECCS SYSCKE Read/Write R/W R/W R/W R/W R/W After reset 0 0 0 0 0 Function Ready interrupt 0: Disable 1: Enable Reed- Solomon calculation end interrupt 0: Disable1: Enable Data bus width 0: 8-bit 1: 16...
Page 253 - error address and error bit position has ended.
TMP92CZ26A 92CZ26A-250 This bit is used to enable or disable the interrupt to be generated when the calculation of error address and error bit position has ended. The interrupt is enabled when this bit is set to “1” and disabled when “0”. (e) <INTRDY> The <INTRDY> bit is used for both Ha...
Page 255 - Table 3.11.3 How to Access the NAND Flash Data Register
TMP92CZ26A 92CZ26A-252 Table 3.11.3 How to Access the NAND Flash Data Register Write Access Data Size Example of instruction 8-bit NAND Flash 16-bit NAND Flash 1-byte access ld (0x1FF0),a Supported Not supported 2-byte access ld (0x1FF0),wa Supported Supported 4-byte access ld (0x1FF0),xwa Supported...
Page 257 - NAND Flash memory when using Reed-Solomon codes.
TMP92CZ26A 92CZ26A-254 The NAND Flash ECC register is used to read ECC generated by the ECC generator. After valid data has been written to or read from the NAND Flash, setting NDFMCR0<ECCE> to “0” causes the corresponding ECC to be set in this register. (The ECC in this register is updated wh...
Page 258 - NAND Flash Reed-Solomon Calculation Result Address Register
TMP92CZ26A 92CZ26A-255 NAND Flash Reed-Solomon Calculation Result Address Register 7 6 5 4 3 2 1 0 bit Symbol RS0A7 RS0A6 RS0A5 RS0A4 RS0A3 RS0A2 RS0A1 RS0A0 Read/Write R After reset 0 0 0 0 0 0 0 0 Function NAND Flash Reed-Solomon Calculation Result Address Register (7-0) 15 14 13 12 11 10 9 8 bit ...
Page 260 - An Example of Accessing NAND Flash of SLC Type
TMP92CZ26A 92CZ26A-257 3.11.5 An Example of Accessing NAND Flash of SLC Type 1. Initialization ; ; ***** Initialize NDFC ***** ; Conditions: 8-bit bus, CE0, SLC, 512 (528) bytes/page, Hamming codes ; ld (ndfmcr1),0001h ; 8-bit bus, Hamming ECC, SYSCK-ON ld (ndfmcr0),2000h ; SPLW1:0=0, SPHW1:0=2 2. W...
Page 266 - If error is found, the error processing routine is performed to
TMP92CZ26A 92CZ26A-263 3. Read (including ECC data read) Reading valid data ; ***** Read valid data***** ; ldw (ndfmcr0),5008h ; CE1 enable ldw (ndfmcr0),50A8h ; WE enable, CLE enable ldw (ndfdtr0),0000h ; Read command 1 ldw (ndfmcr0),50C8h ; ALE enable ldw (ndfdtr0),00xxh ; Address write (4 or 5 ti...
Page 268 - An Example of Connections with NAND Flash; Figure 3.11.10 An Example of Connections with NAND Flash
TMP92CZ26A 92CZ26A-265 3.11.7 An Example of Connections with NAND Flash Note 1: A reset sets the NDRE and NDWE pins as input ports, so pull-up resistors are needed. Note 2: The pull-up resistor value for the NDR/B pin must be set appropriately according to the NAND Flash memory to be used and the ca...
Page 274 - Table 3.12.2 Prescaler Output Clock Resolution
TMP92CZ26A 92CZ26A-271 3.12.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01.The clock φ T0 is selected using the prescaler clock selection register SYSCR0<PRCK>. The prescaler operation can be controlled using TA01RUN<TA0PRUN> in the timer ...
Page 275 - , only the register buffer 0 is written to.
TMP92CZ26A 92CZ26A-272 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the valu...
Page 290 - Figure 3.12.18 TMRA1 Count Up on Signal from TMRA0
TMP92CZ26A 92CZ26A-287 c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Figure 3.12.18 TMRA1 Count Up on Signal from TMRA0 (2) 16 bit timer mode Pairing the two 8-bit timers TMRA0 a...
Page 296 - Table 3.12.4 Timer Mode Setting Registers
TMP92CZ26A 92CZ26A-293 Table 3.12.3 PWM Cycle PWM cycle TAxxMOD<PWMx1:0> 2 6 (x64) 2 7 (x128) 2 8 (x256) TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> Clock gear selection SYSCR1 <GEAR2:0> Prescaler of clock gear SYSCR0 <PRCK> φ T1(x2) φ T4(x8) φ T16(x3...
Page 301 - be used after a reset, data should be written to it beforehand.
TMP92CZ26A 92CZ26A-298 (3) Timer registers (TB0RG0H/L, TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower...
Page 302 - The addresses of the timer registers are as follows:
TMP92CZ26A 92CZ26A-299 TB0RG0H/L and the register buffer 10 both have the same memory addresses (1188H and 1189H) allocated to them. If <TB0RDE> = “0”, the value is written to both the timer register and the register buffer 10. If <TB0RDE> = “1”, the value is written to the register buff...
Page 311 - interval time is set in the timer register TB0RG1H/L.
TMP92CZ26A 92CZ26A-308 3.13.4 Operation in Each Mode (1) 16 bit timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. 7 6 5 4 3 2 1 0 TB0RUN ← – 0 X X – – X 0 Sto...
Page 316 - measurement
TMP92CZ26A 92CZ26A-313 Figure 3.13.13 One-shot Pulse Output (without delay) 2. Frequency measurement The frequency of the external clock can be measured in this mode. The clock is input through the TB0IN0 pin, and its frequency is measured by the 8 bit timers TMRA01 and the 16 bit timer/event coun...
Page 320 - Clock Resolution; The baud rate generator selects between 4-clock inputs:
TMP92CZ26A 92CZ26A-317 3.14.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The prescaler can be run by selecting the baud rate generator as the serial transfer clock. Table 3.14.1 shows prescaler clock resolution into the baud rate generator. Tab...
Page 323 - Input Clock; Calculation method the frequency of TA0TRG
TMP92CZ26A 92CZ26A-320 Table 3.14.2 Transfer Rate Selection (When baud rate generator is used and BR0CR<BR0ADDE> = 0) f SYS [MHz] Input Clock Frequency Divider N φ T0 (f SYS /4) φ T2 ( f SYS /16) φ T8 (f SYS /64) φ T32 (f SYS /256) 7.3728 1 115.200 28.800 7.200 1.800 ↑ 3 38.400 9.600 2.400 0.6...
Page 325 - SIO interrupt mode is selectable by the register SIMC.; (7) Notes for Using Receive Interrupts
TMP92CZ26A 92CZ26A-322 (6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, t...
Page 335 - Operation in each mode; data to or receiving data from an external shift register.
TMP92CZ26A 92CZ26A-332 3.14.4 Operation in each mode (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK a...
Page 337 - Receiving; Bit
TMP92CZ26A 92CZ26A-334 b. Receiving In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data...
Page 340 - Master
TMP92CZ26A 92CZ26A-337 Main routine 7 6 5 4 3 2 1 0 P9CR ← X X X X X − 0 − Set P91 to function as the RXD0 pin. P9FC ← − − X X X − X − SC0MOD0 ← − − 1 − 1 0 0 1 Enable receiving in 8-bit UART mode. SC0CR ← − 0 1 − − − − − Add odd parity. BR0CR ← 0 0 0 1 1 0 0 0 Set the transfer rate to 9600 bps. INT...
Page 341 - Protocol; Select 9-Bit UART Mode on the master and slave controllers.
TMP92CZ26A 92CZ26A-338 Protocol 1. Select 9-Bit UART Mode on the master and slave controllers. 2. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. 3. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifi...
Page 342 - internal clock f; as the transfer clock.
TMP92CZ26A 92CZ26A-339 Setting example: To link two slave controllers serially with the master controller using the internal clock f IO as the transfer clock. • Setting the master controller • Setting the slave controller Main routine P9CR ← X X X X X − 0 1 P9FC ← − − X X X − X 1 P9FC2 ← X X X X X X...
Page 343 - (1) Modulation of the transmission data
TMP92CZ26A 92CZ26A-340 3.14.5 Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.14.8 shows the block diagram. Figure 3.14.18 Block Diagram (1) Modulation of the transmission data When the transmit data is 0, the modem outputs 1 to TXD0 pin wi...
Page 345 - Table 3.14.3 Baud rate and pulse width specifications; Baud Rate
TMP92CZ26A 92CZ26A-342 (5) Notes 1. Baud rate for IrDA When IrDA is operated, set 01 to SC0MOD0<SC1:0> to generate baud-rate. The setting except above (TA0TRG, f IO and SCLK0-input) cannot be used. 2. The pulse width for transmission The IrDA 1.0 specification is defined in Table 3.14.3. Table...
Page 348 - C Bus Mode; C bus mode
TMP92CZ26A 92CZ26A-345 3.15.2 Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. z Serial bus interface control register 0 (SBICR0) z Serial bus interface control register 1 (SBICR1) z Serial bus interface control...
Page 349 - C Bus Mode Control Register; Serial Bus Interface Control Register 0
TMP92CZ26A 92CZ26A-346 3.15.4 I 2 C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I 2 C bus mode. Serial Bus Interface Control Register 0 7 6 5 4 3 2 1 0 Bit symbol SBIEN − − − − − − − Read/Writ...
Page 350 - Serial Bus Interface Control Register 1
TMP92CZ26A 92CZ26A-347 Serial Bus Interface Control Register 1 7 6 5 4 3 2 1 0 Bit symbol BC2 BC1 BC0 ACK − SCK2 SCK1 SCK0/ SWRMON Read/Write R/W R/W R R/W R/W After Reset 0 0 0 0 1 0 0 0/1 (Note2) Function Number of transferred bits (Note 1) Acknowledge mode specification 0: Not generate 1: Generat...
Page 352 - Serial Bus Interface Status Register
TMP92CZ26A 92CZ26A-349 Serial Bus Interface Status Register 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN AL AAS AD0 LRB SBISR (1243H) Read/Write R After reset 0 0 0 1 0 0 0 0 Prohibit Read-modif y-write Function Master/ Slave status monitor 0:Slave 1:Master Transmitter/ Receiver status monitor 0:Receiv...
Page 354 - Acknowledge Mode Specification
TMP92CZ26A 92CZ26A-351 3.15.5 Control in I 2 C Bus Mode (1) Acknowledge Mode Specification When slave address is matched or detecting GENERAL CALL, and set the SBICR1<ACK> to “1”, TMP92CZ26A operates in the acknowledge mode. The TMP92CZ26A generates an additional clock pulse for an Acknowledge...
Page 356 - Figure 3.15.11 Stop condition generation
TMP92CZ26A 92CZ26A-353 (6) Transmitter/Receiver selection Set the SBICR2<TRX> to “1” for operating the TMP92CZ26A as a transmitter. Clear the <TRX> to “0” for operation as a receiver. In Slave Mode, z Data with an addressing format is transferred z A slave address with the same value tha...
Page 357 - Interrupt service requests and interrupt cancellation; LOW; Serial bus interface operation mode selection
TMP92CZ26A 92CZ26A-354 (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTSBI) occurs, the SBICR2 <PIN> is cleared to “0”. During the time that the SBICR2<PIN> is “0”, the SCL line is pulled down to the Low level. The <PIN> i...
Page 360 - Device initialization
TMP92CZ26A 92CZ26A-357 3.15.6 Data Transfer in I 2 C Bus Mode (1) Device initialization Set the SBICR1<ACK, SCK2:0>, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the SBICR1 to “0”. Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format) to the I2...
Page 365 - slave mode after losing arbitration.
TMP92CZ26A 92CZ26A-362 b. If <MST> = 0 (Slave Mode) In the slave mode the TMP92CZ26A operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBI interrupt request occurs when the TMP92CZ26A receives a slave address or a GENERAL CALL from the mas...
Page 367 - Stop condition generation
TMP92CZ26A 92CZ26A-364 (4) Stop condition generation When SBISR<BB> = “1”, the sequence for generating a stop condition start by writing “1” to SBICR2<MST, TRX, PIN> and “0” to SBICR2<BB>. Do not modify the contents of SBICR2<MST, TRX, PIN, BB> until a stop condition has been...
Page 369 - Controller
TMP92CZ26A 92CZ26A-366 3.16 USB Controller 3.16.1 Outline This USB controller (UDC) is designed for various serial links to construct USB system. The outline is as follows: (1) Compliant with USB rev1.1 (2) Full-speed: 12 Mbps (Not supported low-speed (1.5 Mbps)) (3) Auto bus enumeration with 384-by...
Page 370 - UDC
TMP92CZ26A 92CZ26A-367 3.16.1.1 System Configuration The USB controller (UDC) is consisted of following 3 blocks. 1. 900/H1 CPU I/F 2. UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM and 4 endpoint FIFO 3. USB transceiver About above “1.” is explained at 3.16.2, and “2.” ...
Page 372 - Address; SFR
TMP92CZ26A 92CZ26A-369 3.16.2 900/H1 CPU I/F The 900/H1 CPU I/F is a bridge between 900/H1 CPU and UDC and it mainly works following operations. • INTUSB (interrupt from UDC) generation • A bridge for SFR • USB clock control (48 MHz) 3.16.2.1 SFRs The 900/H1 CPU I/F have following SFRs to control UD...
Page 373 - When the remote-wakeup-function is needed, at first check the
TMP92CZ26A 92CZ26A-370 3.16.2.2 USBCR1 Register This register is used to set USB clock enables, transceiver enable etc. 7 6 5 4 3 2 1 0 bit Symbol TRNS_USE WAKEUP SPEED USBCLKE Read/Write R/W R/W R/W R/W After reset 0 0 1 0 Function • TRNS_USE (Bit7) 0: Disable USB transceiver 1: Enable USB transcei...
Page 382 - CORE
TMP92CZ26A 92CZ26A-379 3.16.3 UDC CORE 3.16.3.1 SFRs The UDC CORE has following SFRs to control UDC and USB transceiver. a) FIFO Endpoint 0 to 3 FIFO register b) Device request bmRequestType register bRequest register wValue_L register wValue_H register wIndex_L register wIndex_H register wLength_L ...
Page 386 - means the new device request has been received.
TMP92CZ26A 92CZ26A-383 3.16.3.2 EPx_FIFO Register (x: 0 to 3) This register is prepared for each endpoint independently. This is the window register from or to FIFO RAM. In the auto bus enumeration, the request controller in UDC set mode, which is defined at endpoint descriptor for each endpoint aut...
Page 389 - routine is recognized.
TMP92CZ26A 92CZ26A-386 3.16.3.8 Setup Received Register This register informs for the UDC that an application program recognized INT_SETUP interrupt. 7 6 5 4 3 2 1 0 bit Symbol D7 D6 D5 D4 D3 D2 D1 D0 Read/Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 If this register is accessed by an applicati...
Page 390 - CLASS
TMP92CZ26A 92CZ26A-387 3.16.3.10 Standard Request Register This register shows the standard request that is executing now. A bit which is set to “1” shows present executing request. 7 6 5 4 3 2 1 0 bit Symbol S_INTERFACE G_INTERFACE S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS Read/Writ...
Page 391 - FIFO has data or not.
TMP92CZ26A 92CZ26A-388 3.16.3.12 DATASET Register This register shows whether FIFO has data or not. The application program can be checked it by accessing this register that whether FIFO has data or not. In the receiving status, when valid data transfer from USB host finished, bit which correspond t...
Page 393 - This bit shows status of toggle sequence bit.
TMP92CZ26A 92CZ26A-390 3.16.3.13 EPx_STATUS Register (x: 0 to 7) These registers are status registers for each endpoint. The <SUSPEND> is common for all endpoint. 7 6 5 4 3 2 1 0 bit Symbol TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR Read/Write R R R R R R R After reset...
Page 402 - Hardware or control in software. Each bit mean kind of request.
TMP92CZ26A 92CZ26A-399 3.16.3.18 Port Status Register This register is used when a request of printer class is received. In case of request of GET_PORT_STATUS, the UDC operates automatically by using this data. 7 6 5 4 3 2 1 0 bit Symbol Reserved7 Reserved6 PaperError Select NotError Reserved2 Reser...
Page 403 - or control in software. Each bit mean kind of request.
TMP92CZ26A 92CZ26A-400 3.16.3.20 Request Mode Register This register set answer for Class Request either answer automatically in Hardware or control in software. Each bit mean kind of request. When this register is set applicable bit to “0”, answer is executed automatically by hardware. When this re...
Page 407 - Note1: Max packet size of Isochronous transfer type is 1023 bytes.
TMP92CZ26A 92CZ26A-404 3.16.3.24 EPx_MODE Register (x: 1 to 3) This register sets transfer mode of endpoint (EP1 to EP3). If transaction of SET_CONFIG and SET_INTERFACE are set to software control, this control must use appointed config or interface. When it is setting mode, access this register. 7 ...
Page 408 - This register set mode that access to FIFO in each endpoint.
TMP92CZ26A 92CZ26A-405 3.16.3.25 EPx_SINGLE Register This register sets mode of FIFO in each endpoint (SINGLE/DUAL). 7 6 5 4 3 2 1 0 bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_SINGLE EP2_SINGLE EP1_SINGLE Read/Write R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 Note: Endpoint 3 support only S...
Page 411 - RAM; and String descriptor must set to RAM by using following format.
TMP92CZ26A 92CZ26A-408 3.16.4 Descriptor RAM This area stores descriptor that is defined in USB. Device, Config, Interface, Endpoint and String descriptor must set to RAM by using following format. Note 1: If String Descriptor is supported, set StringxLength area to size0. No support String Dedcript...
Page 412 - Descriptor RAM setting example:
TMP92CZ26A 92CZ26A-409 Descriptor RAM setting example: Address Data Description Description Device Descriptor 500H 12H bLength 501H 01H bDescriptorType Device Descriptor 502H 00H bcdUSB (L) USB Spec 1.00 503H 01H bcdUSB (H) IFC’s specify own 504H 00H bDeviceClass 505H 00H bDeviceSubClass 506H 00H bD...
Page 415 - bmRequestType
TMP92CZ26A 92CZ26A-412 3.16.5 Device Request 3.16.5.1 Standard request UDC support automatically answer in standard request. ( 1) GET_STATUS Request This request returns status that is appointed of receive side, automatically. bmRequestType bRequest wValue wIndex wLength Data 10000000B 10000001B 100...
Page 420 - When INT_SETUP is received, judge contents of receiving request by
TMP92CZ26A 92CZ26A-417 3.16.5.2 Printer Class Request UDC does not support “Automatic answer” of printer class request. Transaction for Class request is the same as vendor request; answering to INT_SETUP interrupt. 3.16.5.3 Vendor request (Class request) UDC doesn’t support “Automatic answer” of Ven...
Page 423 - Transfer mode and Protocol Transaction
TMP92CZ26A 92CZ26A-420 3.16.6 Transfer mode and Protocol Transaction UDC perform automatically in hardware as follows; • Receive packet • Judge address endpoint transfer mode • Error process • Confirm toggle bit CRC of data receiving packet • Generate including toggle bit CRC of data transmitting pa...
Page 436 - Receive
TMP92CZ26A 92CZ26A-433 Stage change condition of control read transfer type 1. Receive SETUP token from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt to external. • Change data stage into the UDC. 2. Receive IN token from host • CPU rec...
Page 445 - Bus Interface and Access to FIFO; Sample: If you use endpoint 1 to dual packet of payload 64 bytes.
TMP92CZ26A 92CZ26A-442 3.16.7 Bus Interface and Access to FIFO (1) CPU bus interface UDC prepares two types of FIFO access, single packet and dual packet. In single packet mode, FIFO capacity that is implemented by hardware is used as big FIFO. In dual packet mode, FIFO capacity that is divided into...
Page 446 - Figure 3.16.15 Receiving Sequence in Single Packet Mode
TMP92CZ26A 92CZ26A-443 (a) Single packet mode This is data sequence of single packet mode when CPU bus interface is used. Figure 3.16.15 is receiving sequence. Figure 3.16.16 is transmitting sequence. Main of this chapter is access to FIFO. Data sequence with USB host refer to chapter 5. Endpoint 0 ...
Page 447 - Figure 3.16.16 Transmitting Sequence in Single Packet Mode
TMP92CZ26A 92CZ26A-444 Below is transmitting sequence in single packet mode. Figure 3.16.16 Transmitting Sequence in Single Packet Mode Transmitting number < payload • WR of transmitting number applicable endpoint • Total = 0 Wait transmitting rest data Wait transmission event IDLE Transmitting n...
Page 448 - Figure 3.16.17 Receiving Sequence in Dual Packet Mode
TMP92CZ26A 92CZ26A-445 (b) Dual packet mode In dual packet mode, FIFO is divided into A and B packet, it is controlled according to priority in hardware. It can be performed at once, transmitting and receiving data to USB host and exchanges to external of UDC. When it reads out data from FIFO for re...
Page 453 - Management; UDC switches to suspend condition by below process.
TMP92CZ26A 92CZ26A-450 3.16.9 Power Management USB controller (UDC) can be switched from optional resume condition (turn on the power supply condition) to suspend (Suspension) condition, and it can be returned from suspends condition to turn on the power supply condition. This function can be set to...
Page 454 - (4) Low power consumption by control of CLK input signal
TMP92CZ26A 92CZ26A-451 (4) Low power consumption by control of CLK input signal When UDC switches to suspend condition, it stops CLK and switches to low power consumption condition. But as system, this function enables besides low power consumption by stopping source of CLK that is supplied from ext...
Page 458 - Condition change
TMP92CZ26A 92CZ26A-455 (b) Condition change Initialization transaction Turn on power supply Waiting USB interrupt condition Request transaction condition Receive USB token Transmit Request error/ S Transaction error/ Transmit STALL Normal finish/No transaction
Page 459 - Device request and various request judgment; Standard request
TMP92CZ26A 92CZ26A-456 (c) Device request and various request judgment Start Get request data Judge Request End Standard request CLEAR_FEATURE SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE SYNCH_FRAME GET_DESCRIPTOR Class request * Error for not s...
Page 478 - 1 Points to Note and Restrictions; Limitation of writing to COMMAND register in special timing
TMP92CZ26A 92CZ26A-475 3.16.11 Points to Note and Restrictions 1. Limitation of writing to COMMAND register in special timing When “STALL” command is issued, ENDPOINT status might be shift to “INVALID”. To avoid this problem, keep the below routine. a. BULK (IN/OUT) In case issue STALL command to en...
Page 481 - SD Card
TMP92CZ26A 92CZ26A-478 3.17.1 Block diagram It shows block diagram and connection to SD card in Figure 3.17.1. Note1: SPCLK, SPCS , SPDO and SPDI pins are set to input port (Port PR3, PR2, PR1, PR0) by reset. These signals are needed pull-up resister to fix voltage level, could you adjust resistance...
Page 482 - SPIMD register is for operation mode or clock etc.
TMP92CZ26A 92CZ26A-479 3.17.2 SFR SFR of SPIC are as follows.These area connected to CPU with 16 bit data bus. (1) SPIMD(SPI Mode setting register) SPIMD register is for operation mode or clock etc. SPIMD Register 7 6 5 4 3 2 1 0 bit Symbol SWRST XEN CLKSEL2 CLKSEL1 CLKSEL0 Read/Write W R/W R/W Afte...
Page 484 - and settings are in under table.
TMP92CZ26A 92CZ26A-481 (h) <SWRST> This bit is for Software reset of transmit/receive FIFO pointer. Write SPICT<TXE> to “0” at <XEN>="1", and stop transmitting. After that, by writing <SWRST> to “1”, the read/write pointer of transmit/receive FIFO are initialized. Whe...
Page 485 - SPICT register is for data length or CRC etc.; Select CRC7 or CRC16 to calculate.
TMP92CZ26A 92CZ26A-482 (2) SPICT(SPI Control Register) SPICT register is for data length or CRC etc. SPICT Register 7 6 5 4 3 2 1 0 bit Symbol CEN SPCS_B UNIT16 TXMOD TXE FDPXE RXMOD RXE Read/Write R/W R/W R/W R/W R/W R/W After Reset 0 1 0 0 0 0 0 0 Function communication control 0: disable 1: enabl...
Page 488 - This SPI Controller supports 6 operations as below.
TMP92CZ26A 92CZ26A-485 (k) <RXE> In UNIT receive mode, receives only 1 UNIT data by writing “1”. When reading receive data register (SPIRD) with the condition “1”, receives one time additionally. In sequential mode, receiving is kept sequentially until FIFO becomes full by writing “1”. During ...
Page 494 - SPIIE register is for enable 4 interrupts.
TMP92CZ26A 92CZ26A-491 (3-2) SPIIE(SPI Interrupt Enable Register) SPIIE register is for enable 4 interrupts. SPIIE Register 7 6 5 4 3 2 1 0 bit Symbol TEMPIE RFULIE TENDIE RENDIE Read/Write R/W After Reset 0 0 0 0 Function TEMP interrupt 0:enable 1:disable RFUL interrupt 0:enable 1:disable TEND inte...
Page 495 - CRC result of Transmit/Receive data is set to SPICR register.; SPI slave
TMP92CZ26A 92CZ26A-492 (4) SPICR (SPI CRC Register) CRC result of Transmit/Receive data is set to SPICR register. SPICR Register 7 6 5 4 3 2 1 0 bit Symbol CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 Read/Write R After Reset 0 0 0 0 0 0 0 0 Function CRC result register [7:0] 15 14 13 12 11 10 9 ...
Page 497 - SPIRD0, SPIRD1 registers are for reading received data.
TMP92CZ26A 92CZ26A-494 (6) SPIRD (SPI Receive Data Register) SPIRD0, SPIRD1 registers are for reading received data. SPIRD0 Register 7 6 5 4 3 2 1 0 bit Symbol RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 Read/Write R After reset 0 0 0 0 0 0 0 0 Function Receive data register [7:0] 15 14 13 12 11 10 9 8 ...
Page 498 - Note of FIFO buffer; There are following notes in this SPIC.; CRC
TMP92CZ26A 92CZ26A-495 • Note of FIFO buffer There are following notes in this SPIC. 1) Transmit ・ Data is overwritten if write data with condition transmit FIFO buffer is FULL. Interrupt and transmission are not executed normally because write-pointer in FIFO becomes abnormal condition. Therefore...
Page 500 - The I
TMP92CZ26A 92CZ26A-497 3.18.1 Block Diagram The I 2 S unit contains two channels: channel 0 and channel 1. Each channel can be controlled and made to output independently. Figure 3.18.1 shows a block diagram for I 2 S channel 0. Figure 3.18.1 I 2 S Block Diagram f SYS I2SCKO Control I2S0CTL <EDGE...
Page 501 - S Channel 0 Control Registers
TMP92CZ26A 92CZ26A-498 3.18.2 SFRs The I 2 S unit is provided with the following registers. These registers are connected to the CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be accessed using 4-byte load instructions. I2S0 Control Register 7 6 5 4 3 2 1 0 bit Symbol T...
Page 502 - S Channel 1 Control Registers
TMP92CZ26A 92CZ26A-499 I2S1 Control Register 7 6 5 4 3 2 1 0 bit Symbol TXE1 *CNTE1 DIR1 BIT1 DTFMT11 DTFMT10 SYSCKE1 Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Function Transmission 0: Stop 1: Start Counter control 0: Clear 1: Start Transmission start bit 0: MSB 1: LSB Bit len...
Page 508 - Detailed Description of Operation; Operation procedure
TMP92CZ26A 92CZ26A-505 3.18.4 Detailed Description of Operation (1) Connection example Figure 3.18.5 shows an example of connections between the TMP92CZ26A and an external LSI (DA converter) using channel 0. Note: After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a ...
Page 509 - Overall Timing Diagram
TMP92CZ26A 92CZ26A-506 Figure 3.18.6 Timing Diagrams (I2S FMT/Stereo/16bit/MSB first) (3) Considerations for using the I 2 S unit 1) INTI2Sn generation timing Every 4bytes data trance from FIFO buffer to shift register per one time. An INTI2Sn interrupt is generated under two conditions. One is when...
Page 523 - LCP0 Setting Range Table; STN monochrome
TMP92CZ26A 92CZ26A-520 LCP0 Setting Range Table Conditions f SYS : 60 MHz Display size (color) : up to 320 × 320 Display size (monochrome/grayscale) : up to 640 × 480 Note: This table shows the range of LCP0 settings that can be made under the conditions shown above. If the CPU clock speed, display ...
Page 526 - Rate
TMP92CZ26A 92CZ26A-523 3.19.3.5 Refresh Rate The period of the horizontal synchronization signal LHSYNC is defined as the product of the value set in LCDHSP<LH15:0> and the LCP0 clock period. The value to be set in LCDHSP<LH15:0> is obtained as follows: TFT Segment size + number of dummy...
Page 527 - Insertion of dummy clocks
TMP92CZ26A 92CZ26A-524 • Insertion of dummy clocks The above is a conceptual diagram showing the data (LD23-0), shift clock (LCP0), horizontal synchronization signal (LHSYNC), and vertical synchronization signal (LVSYNC) on the LCD panel. The front porch and back porch as shown above should be taken...
Page 528 - Setting method
TMP92CZ26A 92CZ26A-525 • Setting method The front dummy LHSYNC (vertical front porch) not accompanied by valid data in the total of LHSYNC period in the LVSYNC period is defined by the value set in LCDPRVSP<PLV6:0>. Front dummy LHSYNC (vertical front porch) = <PLV6:0> The back dummy LHSY...
Page 536 - be set in a range of 0 to 1024 pulses of the LCP0 clock.; LLOAD
TMP92CZ26A 92CZ26A-533 The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can be set in a range of 0 to 1024 pulses of the LCP0 clock. The actual enable width is determined depending on the LCDLDDLY<PDT> setting, as shown below. Enable width = <LDW9:0> + 1 (...
Page 537 - inserted in the LLOAD signal.
TMP92CZ26A 92CZ26A-534 As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be inserted in the LLOAD signal. Delay time = <LDD6:0> Note: The delay time for the LLOAD signal is controlled based on LCDLDDLY<PDT>=1. Therefore, even if the delay time is set to”0...
Page 542 - Note
TMP92CZ26A 92CZ26A-539 When LCDCTL0<FRMON>=1 and LCDCTL0<DLS>=1, frame output is inverted at intervals set in LCDDVM0<FML3:0> and the LFR signal is inverted at intervals of “LCP0 × M”. The “M” value is specified in LCDDVM0<FMP7:4>. When <DLS>="1" LFR signal sync...
Page 544 - Bus
TMP92CZ26A 92CZ26A-541 6. LD Bus The data to be transferred to the LCD driver is output via a dedicated bus (LD23 to LD0). The output format can be selected according to the input method of the LCD driver to be used. The LCDC reads data of the size corresponding to the specified LCD size from the di...
Page 546 - Display Memory
TMP92CZ26A 92CZ26A-543 STN 16-grayscale (1-pixel display data = 4-bit memory data) Display Memory LD Bus Output 8-bit type LD0 3-0 → 35-32 … LD1 7-4 → 39-36 … LD2 11-8 → 43-40 … LD3 15-12 → 47-44 … LD4 19-16 → 51-48 … LD5 23-20 → 55-52 … LD6 27-24 → 59-56 … LD7 31-28 → 63-60 … Figure 3.19.3 Memory M...
Page 563 - Method; How to calculate the point B address:; Display RAM Image (QVGA 320
TMP92CZ26A 92CZ26A-560 3. Setting Method The <LDC2:0> bits in the LCDMODE1 register are used to set the display data rotation function. LCDMODE1 Register 7 6 5 4 3 2 1 0 bit Symbol LDC2 LDC1 LDC0 LDINV AUTOINV INTMODE FREDGE SCPW2 Read/Write R/W R/W R/W R/W R/W R/W W W After reset 0 0 0 0 0 0 ...
Page 564 - Considerations for Using the LCDC
TMP92CZ26A 92CZ26A-561 3.19.5.3 Considerations for Using the LCDC 1 ． If the operation mode is changed while the LCDC is operating, a maximum of one frame may not be displayed properly. Although this degree of disturbance does not normally pose any problem (e.g. no response on LCD, display not visib...
Page 565 - STN
TMP92CZ26A 92CZ26A-562 3.19.6 Setting Example • STN C O M 0 0 1 C O M 2 4 0 SE G 0 0 1 S E G 240 2 4 0 C O M × 2 4 0 S E G L C D (M o n o c h ro m e P a n e l) O 2 4 0 O 0 0 1 O00 1 O240 L C P 0 L H S Y N C L F R L D 7 〜 L D 0 S C P L P F R /D S P O F LP FR E IO 1 E IO 2 o p e n DI R VD D S/ C V D D...
Page 571 - Figure 3.20.5 Calculation analog voltage
TMP92CZ26A 92CZ26A-568 3.20.4 X/Y position measuring procedure In the INT4 routine, execute an X/Y position measuring procedure like below. <X position measurement> At first, set both SPX, SMX-switches to ON, and set SPY, SMY-switches to OFF. By this setting, analog-voltage which shows the X-p...
Page 576 - Port setting
TMP92CZ26A 92CZ26A-573 3.20.6 Note 1. De-bounce circuit The system clock of CPU is used in de-bounce circuit. Therefore, de-bounce circuit is not operated when clock is not supplied to CPU (IDLE1, STOP mode or PCM mode). And, an interrupt which through the de-bounce circuit is not generated. When st...
Page 577 - Alarm interrupt generate; diagram; the system side when handle year column in the Christian era.
TMP92CZ26A 92CZ26A-574 3.21 Real time clock (RTC) 3.21.1 Function description for RTC 1) Clock function (hour, minute, second) 2) Calendar function (month and day, day of the week, and leap year) 3) 24 or 12-hour (AM/PM) clock function 4) +/- 30 second adjustment function (by software) 5) Alarm func...
Page 578 - registers
TMP92CZ26A 92CZ26A-575 3.21.3 Control registers Table 3.21.1 PAGE 0 (Timer function) registers Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read/Write SECR 1320H 40 sec 20 sec 10 sec 8 sec 4 sec 2 sec 1 sec Second column R/W MINR 1321H 40 min 20 min 10 min 8 min 4 min 2 min 1 min ...
Page 579 - Detailed explanation of control register; beginning of the program.
TMP92CZ26A 92CZ26A-576 3.21.4 Detailed explanation of control register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) 7 6 5 4 3 2 1 0 Bit symbol SE6 SE5 SE4 SE3 SE2 SE1 SE0 SECR (1320H) Read/W...
Page 582 - 日桁レジスタ
TMP92CZ26A 92CZ26A-579 (4) Day of the week column register (for PAGE0/1) 7 6 5 4 3 2 1 0 Bit symbol WE2 WE1 WE0 DAYR (1323H) Read/Write R/W After reset Undefined Function "0" is read. W2 W1 W0 0 0 0 Sunday 0 0 1 Monday 0 1 0 Tuesday 0 1 1 Wednesday 1 0 0 Thursday 1 0 1 Friday 1 1 0 Saturday ...
Page 586 - description; Figure 3.21.2 Flowchart of timer data read
TMP92CZ26A 92CZ26A-583 3.21.5 Operational description (1) Reading timer data There is the case, which reads wrong data when carry of the inside counter happens during the operation which clock data reads. Therefore please read two times with the following way for reading correct data. Figure 3.21.2 ...
Page 587 - Figure 3.21.3 Timing of INTRTC and Clock data
TMP92CZ26A 92CZ26A-584 (2) Timing of INTRTC and Clock data When time is read by interrupt, read clock data within 0.5s(s) after generating interrupt. This is because count up of clock data occurs by rising edge of 1Hz pulse cycle. Figure 3.21.3 Timing of INTRTC and Clock data 56 57 58 59 0 1 2 3 4 A...
Page 588 - Resetting a divider
TMP92CZ26A 92CZ26A-585 (3) Writing timer data When there is carry on the way of write operation, expecting data can not be wrote exactly. Therefore, in order to write in data exactly please follow the below way. 1. Resetting a divider In RTC inside, there are 15-stage dividers, which generates 1Hz c...
Page 590 - Explanation of the interrupt signal and alarm signal
TMP92CZ26A 92CZ26A-587 3.21.6 Explanation of the interrupt signal and alarm signal Can use alarm function by setting of register of PAGE1 and output either of three signals from ALARM pin as follows by write “1” to PAGER<PAGE>. INTRTC outputs 1shot pulse when the falling edge is detected. RTC ...
Page 591 - RTC outputs clock of 1Hz to; RTC outputs clock of 16Hz to
TMP92CZ26A 92CZ26A-588 (2) When output clock of 1Hz RTC outputs clock of 1Hz to ALARM pin by setting up PAGER<ENAALM>= “0”, RESTR<DIS1HZ>= “0”, <DIS16HZ>= “1”. And RTC generates INTRC interrupt by falling edge of the clock. (3) When output clock of 16Hz RTC outputs clock of 16Hz to...
Page 595 - generator; Scale Frequency
TMP92CZ26A 92CZ26A-592 3.22.3 Operational Description 3.22.3.1 Melody generator The Melody function generates signals of any frequency (4Hz-5461Hz) based on low-speed clock (32.768KHz) and outputs the signals from the MLDALM pin. By connecting a loud speaker outside, Melody tone can easily sound. (O...
Page 598 - comparator is still enable state.
TMP92CZ26A 92CZ26A-595 3.23 Analog-Digital Converter (ADC) This LSI has a 6-channel, multiplexed-input, 10-bit successive-approximation Analog-Digital converter (ADC). Figure 3.23.1 shows a block diagram of the AD converter. The 6-analog input channels (AN0-AN5) can be used as general-purpose inputs...
Page 599 - AD Mode Control Register 0 (Normal conversion control)
TMP92CZ26A 92CZ26A-596 3.23.1 Control register The AD converter has 6-mode control registers (ADMOD0, ADMOD1, ADMOD2, ADMOD3, ADMOD4 and ADMOD5) and 6-conversion result high/low register pairs (ADREG0H/L ∼ ADREG5H/L). The results of high-priority AD conversion are stored in the ADREGSPH/L. Figure 3....
Page 603 - AD Conversion Result Register 1 High
TMP92CZ26A 92CZ26A-600 AD Conversion Result Register 0 Low 7 6 5 4 3 2 1 0 bit Symbol ADR01 ADR00 OVR0 ADR0RF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of AN0 AD conversion result Overrun flag 0:No generate 1: Generate AD conversion result store flag 1: Stored AD Conversion Re...
Page 604 - AD Conversion Result Register 2 Low; AD Conversion Result Register 3 High
TMP92CZ26A 92CZ26A-601 AD Conversion Result Register 2 Low 7 6 5 4 3 2 1 0 bit Symbol ADR21 ADR20 OVR2 ADR2RF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of AN2 AD conversion result Overrun flag 0:No generate 1: Generate AD conversion result store flag 1: Stored AD Conversion Re...
Page 605 - AD Conversion Result Register 4 Low; AD Conversion Result Register 4 High; AD Conversion Result Register 5 High
TMP92CZ26A 92CZ26A-602 AD Conversion Result Register 4 Low 7 6 5 4 3 2 1 0 bit Symbol ADR41 ADR40 OVR4 ADR4RF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of AN4 AD conversion result Overrun flag 0:No generate 1: Generate AD conversion result store flag 1: Stored AD Conversion Re...
Page 606 - High-priority AD Conversion Result Register SP Low; High-priority AD Conversion Result Register SP High
TMP92CZ26A 92CZ26A-603 High-priority AD Conversion Result Register SP Low 7 6 5 4 3 2 1 0 bit Symbol ADRSP1 ADRSP0 OVSRP ADRSPRF Read/Write R R R After reset 0 0 0 0 Function Store Lower 2 bits of an AD conversion result Overrun flag 0:No generate 1: Generate AD conversion result store flag 1: Store...
Page 610 - Starting an AD Conversion; “1”. These flags are cleared to “0” by reading these flags only.
TMP92CZ26A 92CZ26A-607 3.23.2.3 Starting an AD Conversion The ADC supports two types of AD conversion: normal AD conversion and high-priority AD conversion. The ADC initiates a normal AD conversion by software when the ADMOD0<ADS> is set to “1”. It initiates a high-priority AD conversion by so...
Page 611 - AD Conversion Modes and AD Conversion-End Interrupts
TMP92CZ26A 92CZ26A-608 3.23.2.4 AD Conversion Modes and AD Conversion-End Interrupts The ADC supports the following four conversion modes. For a normal AD conversion, ADMOD0<1:0> select one of the four conversion modes. For a high-priority AD conversion, the ADC only supports Channel Fixed Sin...
Page 614 - conversion clock can be selected from 1/1 to 1/7 of f
TMP92CZ26A 92CZ26A-611 3.23.2.5 High-Priority Conversion Mode The ADC can perform a high-priority AD conversion while it is performing a normal AD conversion sequence. A high-priority AD conversion can be started at software by setting the ADMOD2<HADS> to “1”. It is also triggered by a hardwar...
Page 618 - Figure 3.24.1 Block Diagram of Watchdog Timer
TMP92CZ26A 92CZ26A-615 3.24 Watchdog Timer (Runaway detection timer) The TMP92CZ26A contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. Wh...
Page 620 - Disable control; Enable control
TMP92CZ26A 92CZ26A-617 3.24.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode registers (WDMOD) 1. Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchdog timer...
Page 624 - Detailed Description of Operation; Entering the Power Cut Mode
TMP92CZ26A 92CZ26A-621 3.25.2 Detailed Description of Operation This section explains the procedures for entering and exiting the Power Cut Mode. • Entering the Power Cut Mode When to enter the Power Cut Mode, the CPU needs to be operating in the internal RAM. Low frequency clock (XT) must be enable...
Page 626 - Exiting the Power Cut Mode; Source Symbol; “1” or “0” output
TMP92CZ26A 92CZ26A-623 • Exiting the Power Cut Mode The Power Cut Mode can be exited by external or internal interruption. (It inhibits to exit the Power Cut Mode by reset when DVCC1A is cut off. Reset must be asserted after supplying power to DVCC1A and waiting for its voltage to fully stabilize.) ...
Page 631 - Register
TMP92CZ26A 92CZ26A-628 3.26 Multiply and Accumulate Calculation Unit (MAC) The TMP92CZ26A includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit + 64-bit arithmetic operations at high speed. The MAC has the following features: ・ One-cycle execution for all MAC operations (excluding reg...
Page 636 - Mode
TMP92CZ26A 92CZ26A-633 3.27 Debug Mode The TMP92CZ26A includes a debug support unit (DSU) for enabling on-board debugging. The DSU has 9 debug pins for interfacing with an external emulator via a DSU connector to be mounted on the target board and a DSU connecting cable. For details about debugging,...
Page 640 - Boot function; PMC function
TMP92CZ26A 92CZ26A-637 3) Boot function In this LSI, we support boot function, however, this boot function is not available in debug mode. (It is inhibit to set DBGE =“0”, AM0 = “1” and AM1 = “1” at the same time.) 4) PMC function In debug mode, the PMC function for cutting off the power supply to i...
Page 643 - Characteristics; Maximum Ratings
TMP92CZ26A 92CZ26A-640 4. Electrical Characteristics (Tentative) 4.1 Maximum Ratings Symbol Contents Rating Unit DVCC3A DVCC3B -0.3 to 3.9 DVCC1A DVCC1B DVCC1C -0.3 to 3.0 AVCC Power Supply Voltage -0.3 to 3.9 V VIN Input Voltage -0.3 〜 DVCC3A/3B+0.3 (Note1) -0.3 to AVCC + 0.3 (Note2) V IOL Output C...
Page 644 - DC Electrical Characteristics
TMP92CZ26A 92CZ26A-641 4.2 DC Electrical Characteristics Symbol Parameter Min Typ. Max Unit Condition DVCC 3A General I/O Power Supply Voltage (DVCC=AVCC) (DVSSCOM=AVSS=0V) 3.0 3.3 3.6 V DVCC 1A Internal Power A DVCC 1B Internal Power B DVCC 1C High CLK oscillator and PLL Power 1.4 1.5 1.6 V X1=6 to...
Page 648 - Basic Bus Cycle; Read cycle; AC measuring condition
TMP92CZ26A 92CZ26A-645 4.3 AC Characteristics The Following all AC regulation is the measurement result in following condition, if unless otherwise noted. AC measuring condition • Clock of top column in above table shows system clock frequency, and “T” shows system clock period [ns]. • Output level:...
Page 653 - Page ROM Read Cycle; Variable; pin. The falling timing of
TMP92CZ26A 92CZ26A-650 4.3.2 Page ROM Read Cycle (1) 3-2-2-2 mode Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit 1 System clock period ( = T) t CYC 12.5 266.6 12.5 16.6 2 A0, A1 → D0 ~ D15 input t AD2 2.0T − 18 7 15.2 3 A2 ~ A23 → D0 ~ D15 input t AD3 3.0T − 18 19.5 31.8 4 RD falling → D0 ~ D1...
Page 654 - SDRAM controller AC Characteristics
TMP92CZ26A 92CZ26A-651 4.3.3 SDRAM controller AC Characteristics Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit <STRC[2:0]>=000 T 12.5 16.6 1 Ref/Active to ref/active command period <STRC[2:0]>=110 t RC 7T 87.5 116.2 <STRC[2:0]>=000 2T 12210 25.0 33.2 2 Active to precharge co...
Page 661 - NAND Flash Controller AC Characteristics
TMP92CZ26A 92CZ26A-658 4.3.4 NAND Flash Controller AC Characteristics Variable No. Symbol Parameter Min Max 80 MHz (n=3) (m=3) 60 MHz (n=3) (m=3) Unit 1 t NC Access cycle (2 + n + m ) T 100 132 2 t RP NDRE low level width (1.5 + n) T − 12 45 63 3 t REA NDRE data access time (1.5 + n) T − 15 41 60 4 ...
Page 662 - Serial channel timing
TMP92CZ26A 92CZ26A-659 4.3.5 Serial channel timing (1) SCLK input mode (I/O interface mode) Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit SCLK cycle t SCY 16T 200 266 Output data → SCLK rising/ falling t OSS t SCY /2 − 4T − 30 20 36.4 SCLK rising/ falling → Output data hold t OHS t SCY /2 + 2...
Page 665 - S Timing
TMP92CZ26A 92CZ26A-662 4.3.10 I 2 S Timing Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit I2SCKO clock period t CR tIC 100 100 I2SCKO high width t HB 0.5 t CR − 15 35 35 I2SCKO low width t LB 0.5 t CR − 15 35 35 I2SDO, I2SWS setup time t SD 0.5 t CR − 15 35 35 I2SDO, I2SWS hold time t HD 0.5 t...
Page 667 - AD Conversion Characteristics; Parameter Symbol Condition Min
TMP92CZ26A 92CZ26A-664 4.4 AD Conversion Characteristics Parameter Symbol Condition Min Typ. Max Unit Analog reference voltage ( + ) VREFH AVCC − 0.2 AVCC AVCC Analog reference voltage ( − ) VREFL DVSS DVSS DVSS + 0.2 AD converter power supply voltage AVCC DVCC3A/3B DVCC3A/3B DVCC3A/3B AD converter ...
Page 668 - Table of Special function registers (SFRs); Table layout
TMP92CZ26A 92CZ26A-665 5. Table of Special function registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 8-Kbyte address space from 000000H to 001FF0H. (1) I/O Port (13) Clock gear, PLL (2) Interrupt control (14) 8-bit timer (3) Memory controller (15) 16-...
Page 670 - Note: Do not access no allocated name address.
TMP92CZ26A 92CZ26A-667 [1] Port (2/2) Address Name Address Name Address Name Address Name 0080H 0090H PGDR 00A0H PT 00B0H PX 1H P1DR 1H 1H 1H 2H 2H 2H PTCR 2H PXCR 3H 3H PJDR 3H PTFC 3H PXFC 4H P4DR 4H PKDR 4H PU 4H 5H P5DR 5H PLDR 5H 5H 6H P6DR 6H PMDR 6H PUCR 6H 7H P7DR 7H PNDR 7H PUFC 7H 8H P8DR ...
Page 680 - S [23] MAC; Address Name
TMP92CZ26A 92CZ26A-677 [22] I 2 S [23] MAC Address Name Address Name Address Name Address Name 1800H I2S0BUF 1810H I2S1BUF 1BE0H MACMA 1BF0H 1H 1H 1H MACMA 1H 2H 2H 2H MACMA 2H 3H 3H 3H MACMA 3H 4H 4H 4H MACMB 4H 5H 5H 5H MACMB 5H 6H 6H 6H MACMB 6H 7H 7H 7H MACMB 7H 8H I2S0CTL 8H I2S1CTL 8H MACORL 8...
Page 681 - Symbol Name
TMP92CZ26A 92CZ26A-678 (1) I/O ports (1/11) Symbol Name Address 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W P1 PORT1 0004H Data from external port (Output latch register is cleared to “0”) P47 P46 P45 P44 P43 P42 P41 P40 R/W P4 PORT4 0010H 0 0 0 0 0 0 0 0 P57 P56 P55 P54 P53 P52 P51 P50 R/W ...
Page 748 - Stereo
TMP92CZ26A 92CZ26A-745 (22) I 2 S (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 TXE0 *CNTE0 DIR0 BIT0 DTFMT01 DTFMT00 SYSCKE0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 1808H Transmit 0: Stop 1: Start Counter control 0: Clear 1: Start Transmis sion start BIT 0:MSB 1:LSB Bit length 0: 8 bits 1:16 bits Out...
Toshiba 26C100U
User Manual
Toshiba 55SL412U
User Manual
Toshiba 50L5200U
User Manual
Toshiba 24V4210U
User Manual
Toshiba 40L3400U
User Manual
Toshiba 50L1350U
User Manual
Toshiba 24SLV411U
User Manual
Toshiba 50L2400U
User Manual
Toshiba 58L7350U
User Manual
Toshiba 50L1400U
User Manual