SMSC COM20020 - Manuals - manualsarea.com

Page 2 - TABLE OF CONTENTS

2 TABLE OF CONTENTS FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION ....................................................................................................................

Page 3 - PIN CONFIGURATION; Ordering Information:

3 controller optimized for use in industrial andautomotive applications. Using an ARCNETprotocol engine is the ideal solution for factoryautomation applications because it provides atoken-passing protocol, a highly reliable andproven networking scheme, and a data rate ofup to 2.5 Mbps when using the...

Page 4 - DESCRIPTION OF PIN FUNCTIONS

4 DESCRIPTION OF PIN FUNCTIONS DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION MICROCONTROLLER INTERFACE 1-3 1-3 Address0-2 A0/nMUX,A1,A2/ALE Input. On a non-multiplexed bus, thesesignals are directly connected to the low bitsof the host address bus. On a multiplexedaddress/data bus, A0/nMUX is tie...

Page 5 - prior to the

5 DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION 19 23 nReset in nRESET IN Input. This active low signal issued by themicrocontroller executes a hardware reset. It is used to activate the internal resetcircuitry within the COM20020. 20 24 nInterrupt nINTR Output. This active low signal is generate...

Page 6 - be left floating.; +5 Volt Power Supply pin.; Ground pin.

6 DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION instead, it must be connected to XTAL1 witha 390 Ω pull-up resistor, and XTAL2 should be left floating. 24 15,28 PowerSupply V DD +5 Volt Power Supply pin. 12 7,14,22 Ground V SS Ground pin.

Page 8 - PROTOCOL DESCRIPTION; NETWORK PROTOCOL; internal; DATA RATES; s. IDLE LINE Timeout for 156.2 Kbps is 82; NETWORK RECONFIGURATION

8 PROTOCOL DESCRIPTION NETWORK PROTOCOL Communication on the network is based on atoken passing protocol. Establishment of thenetwork configuration and management of thenetwork protocol are handled entirely by theCOM20020's internal microcoded sequencer. A processor or intelligent peripheral transmi...

Page 9 - BROADCAST MESSAGES; and bit 5 of the Setup; Response Time; S translates to a distance of about 4

9 When any COM20020 senses an idle line forgreater than 82 µ S, which occurs only when the token is lost, each COM20020 starts an internaltimeout equal to 146 µ s times the quantity 255 minus its own ID. The COM20020 starts network reconfiguration by sending an invitationto transmit first to itself ...

Page 12 - SYSTEM DESCRIPTION; MICROCONTROLLER INTERFACE; The signal on the A0

12 SYSTEM DESCRIPTION MICROCONTROLLER INTERFACE The top halves of Figures 2 and 3 illustratetypical COM20020 interfaces to themicrocontrollers. The interfaces consist of an 8-bit data bus, an address bus, and a control bus.In order to support a wide range ofmicrocontrollers without requiring glue lo...

Page 14 - FIGURE C

14 RXIN nPULSE1 nPULSE2 nTXEN GND Traditional Hybrid Configuration RXIN nPULSE1 nPULSE2 17, 19, 4, 13, 14 5.6K 1/2W5.6K1/2W 0.01 uF 1KV 12 11 -5V 0.47 uF 10 uF + 3 0.47 uF + +5V uF 10 6 FIGURE C D0-D7 nIRQ1 nRES nIOS R/nW A7 D0-D7 nCS nRESET IN nRD/nDS nWR/nDIR nINTR A0/nMUX A0 XTAL1 XTAL2 XTAL1 XTA...

Page 15 - TRANSMISSION MEDIA INTERFACE; The user; Traditional Hybrid Interface; termination, and node count for ARCNET nodes.; Backplane Configuration; configuration of the output driver)

15 TRANSMISSION MEDIA INTERFACE The bottom halves of Figures 2 and 3 illustratethe COM20020 interface to the transmissionmedia used to connect the node to the network. Table 1 lists different types of cable which aresuitable for ARCNET applications. 1 The user may interface to the cable of choice in...

Page 16 - RBIAS

16 FIGURE 5 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 20MHZ CLOCK(FOR REF. ONLY) nPULSE1 nPULSE2 DIPULSE RXIN 1 0 100ns 100ns 200ns 400ns 1 COM20020 COM20020 COM20020 +VCC RBIAS +VCC +VCC RBIAS RBIAS RT RT FIGURE 4 - COM20020 NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS 75176B or Equiv.

Page 17 - valid only for Backplane

17 In typical applications, the serial backplane isterminated at both ends and a bias is providedby the external pull-up resistor. The RXIN signal is directly connected to thecable via an internal Schmitt trigger. A negativepulse on this input indicates a logic "1". Lack ofpulse indicates a ...

Page 18 - FIGURE 6 - INTERNAL BLOCK DIAGRAM

18 MICRO- SEQUENCER AND WORKING REGISTERS STATUS/ COMMAND REGISTER RESET LOGIC RECONFIGURATION TIMER NODE ID LOGIC OSCILLATOR TX/RXLOGIC ADDITIONAL REGISTERS ADDRESS DECODINGCIRCUITRY 2K x 8 AD0-AD2, BUS ARBITRATION CIRCUITRY nPULSE1nPULSE2nTXEN XTAL1XTAL2 nINTR nRESET IN RAM A0/nMUX A1 A2/BALE nRD/...

Page 19 - , available from Standard Microsystems Corporation.; FUNCTIONAL DESCRIPTION

19 Table 1 - Typical Media CABLE TYPE NOMINAL IMPEDANCE ATTENUATION PER 1000 FT. AT 5MHZ RG-62 Belden #86262 93 Ω 5.5dB RG-59/U Belden #89108 75 Ω 7.0dB RG-11/U Belden #89108 75 Ω 5.5dB IBM Type 1* Belden #89688 150 Ω 7.0dB IBM Type 3* Telephone TwistedPair Belden #1155A 100 Ω 17.9dB COMCODE 26 AWG ...

Page 20 - Table 2 - Read Register Summary

20 REGISTER ADDRESS READ MSB LSB STATUS DIAG.STATUS ADDRESSPTR HIGH ADDRESSPTR LOW DATA RESERVED CONFIG-URATION TENTID NODEID SETUP NEXT ID 00 01 02 03 04 05 06 07 RI MY- RECON RDDATA A7 D7 X RESET TID7 NID7 P1MODE NXTID7 FOUR NAKS NXTID6 X DUPID AUTO- INC A6 D6 X CCHEN TID6 NID6 X RCVACT X A5 D5 X ...

Page 21 - Table 3 - Write Register Summary

21 REGISTER ADDRESS WRITE MSB LSB INTERRUPT COMMAND ADDRESSPTR HIGH ADDRESS PTR LOW DATA RESERVED CONFIG- URATION TENTID NODEID SETUP NEXT ID 00 01 02 03 04 05 06 07 RI RDDATA A7 D7 0 RESET TID7 NID7 0 0 0 D6 AUTO- INC A6 D6 0 CCHEN TID6 NID6 0 D5 0 A5 D5 0 TXEN TID5 NID5 0 0 D4 0 A4 D4 0 ET1 TID4 N...

Page 22 - In; Tentative ID Register

22 INTERNAL REGISTERS The COM20020 contains eight internal registers.Tables 2 and 3 illustrate the COM20020register map. Reserved locations should not beaccessed. All undefined bits are read asundefined and must be written as logic "0". Interrupt Mask Register (IMR) The COM20020 is capable o...

Page 23 - these bits exist in; Diagnostic Status Register; Writing to

23 Transmitter is disabled, the Receiver portion ofthe device is still functional and will provide theuser with useful information about the network. The Node ID Register defaults to the value 00000000 upon hardware reset only. Next ID Register The Next ID Register is an 8-bit, read-onlyregister, ac...

Page 24 - Configuration Register; SUBAD0 and SUBAD1; Setup Register

24 Configuration Register The Configuration Register is a read/writeregister which is used to configure the differentmodes of the COM20020. The ConfigurationRegister defaults to the value 0001 1000 uponhardware reset only. SUBAD0 and SUBAD1 point to selection in Register 7. Setup Register The Setup ...

Page 31 - FIGURE 7 - SEQUENTIAL ACCESS OPERATION

31 Address Pointer Register Low 2K x 8 RAM 11 Data Register 8 I/O Address 04H I/O Address 03H 11-Bit Counter Memory Address Bus Memory Data Bus D0-D7 High I/O Address 02H INTERNAL FIGURE 7 - SEQUENTIAL ACCESS OPERATION

Page 32 - Disable Interrupts

32 INTERNAL RAM The integration of the 2K x 8 RAM in theCOM20020 represents significant real estatesavings. The most obvious benefit is the 24-pinpackage in which the device is now placed (adirect result of the integration of RAM). Inaddition, the PC board is now free of thecumbersome external RAM, ...

Page 33 - Selecting RAM Page Size

33 • The pointer may now be read to determine how many transfers were completed. The software flow for controlling theConfiguration, Node ID, Tentative ID, and NextID registers is generally limited to theinitialization sequence and the maintenance ofthe network map. Additionally, it is necessary to ...

Page 34 - FIGURE 8 - RAM BUFFER PACKET CONFIGURATION

34 SID DID COUNT = 256-N NOT USED DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 DATA BYTE N NOT USED SID DID 0 COUNT = 512-N NOT USED DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 DATA BYTE N SHORT PACKET FORMAT LONG PACKET FORMAT ADDRESS ADDRESS 0 1 2 COUNT 255 511 N = DATA PACKET LENGTHSID = SOURCE IDDID = DESTIN...

Page 36 - Receive Sequence

36 The third possibility which may occur after aFREE BUFFER ENQUIRY is issued is if thedestination node does not respond at all. In thiscase, the TA bit is set to a logic "1", while theTMA bit remains at a logic "0". The user shoulddetermine whether the node should try toreissue the ...

Page 37 - The device is designed such that the interrupt; Transmit Command Chaining

37 T R I R I TA P O R T E S T R E C O N T M A T T A T M A T T A T R I M S B L S B FIGURE 9 - COMMAND CHAINING STATUS REGISTER QUEUE COMMAND CHAINING The Command Chaining operation allowsconsecutive transmissions and receptions tooccur without host microcontroller intervention.Through the use of a du...

Page 38 - Receive Command Chaining

38 In the Command Chaining Mode, at any timeafter the first command is issued, the processorcan issue a second "Enable Transmit from Pagefnn" command. The COM20020 stores the factthat the second transmit command was issued,along with the page number. After the first transmission is completed...

Page 40 - INITIALIZATION SEQUENCE; Bus Determination; IMPROVED DIAGNOSTICS

40 INITIALIZATION SEQUENCE Bus Determination Writing to and reading from an odd addresslocation from the COM20020's address spacecauses the COM20020 to determine theappropriate bus interface. When the COM20020 is powered on the internal registers may bewritten to. Since writing a non-zero value to t...

Page 42 - OSCILLATOR; pull-up resistor is required on

42 network. This feature is useful because itminimizes the need for human intervention.When a value placed in the Tentative IDRegister matches the Node ID of another nodeon the network, the TENTID bit is set, telling thesoftware that this NODE ID already exists on the network. The software should pe...

Page 43 - OPERATIONAL DESCRIPTION; TTL Levels

43 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range........................................................................................ 0 o C to +70 o C Storage Temperature Range .........................................................................................

Page 45 - Output and I/O pins capacitive load specified as follows:; pF

45 CAPACITANCE (T A = 25 ° C; f C = 1MHz; V DD = 0V) Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT Input Capacitance C IN 5.0 pF Output Capacitance 1 (All outputs except nPULSE1 in BackPlane Mode)Output Capacitance 2 (nPULSE1, inBackPlane Mode On...

Page 46 - TIMING DIAGRAMS

46 TIMING DIAGRAMS AD0-AD2, VALID nCS t1 t3 t8 T is the Arbitration Clock Period.T is identical to XTAL1 if SLOW ARB = 0, * T is twice XTAL1 period if SLOW ARB = 1 ALE VALID DATA t2, t6 t5 t4 t7 D3-D7 The Microcontroller typically accesses the COM20020 on every other cycle.Therefore, the cycle time ...

Page 57 - D I M; FIGURE 18 - 28-PIN PLCC PACKAGE DIMENSIONS

57 AA 1BB 1CDD 1D 2D 3EFG R . 1 6 0 - . 1 8 0. 0 9 0 - . 1 2 0. 0 1 3 - . 0 2 1. 0 2 6 - . 0 3 2. 0 2 0 - . 0 4 5. 4 8 5 - . 4 9 5. 4 5 0 - . 4 5 6. 3 9 0 - . 4 3 0. 3 0 0 R E F. 0 5 0 B S C. 0 4 2 - . 0 5 6. 0 4 2 - . 0 4 8 . 0 2 5 - . 0 4 5 D I M 2 8 L J . 0 0 0 - . 0 2 0 N O T E S : A l l d i m e...

Page 58 - DIM; FIGURE 18A - 24-PIN DIP PACKAGE DIMENSIONS

58 E1 E BasePlane SeatingPlane D S B1 e B A2 A A1 L Note: All dimensions are in inches. A e C B e DIM A A1A2 B B1 CD E E1 e eAeB L S 24L .090-.150.020-.065.145-.155.016-.021.060-.070.010-.014 1.245-1.265 .590-.630.530-.545 .100BSC .600REF .610-.670.120-.140.065-.085 FIGURE 18A - 24-PIN DIP PACKAGE D...