Samsung S3F80JB - Manuals

S3F80JB MICROCONTROLLER vii Table of Contents (Continued) Chapter 8 RESET Overview .................................................................................................................................................... 8-1 Reset Sources .....................................................

viii S3F80JB MICROCONTROLLER Table of Contents (Continued) Chapter 10 Basic Timer and Timer 0 Overview ....................................................................................................................................................10-1 Basic Timer (BT) ..............................

S3F80JB MICROCONTROLLER ix Table of Contents (Continued) Chapter 15 Embedded Flash Memory Interface Overview .................................................................................................................................................... 15-1 ISP TM (On-Board Programming) Sector ...

x S3F80JB MICROCONTROLLER List of Figures Figure Title Page Number Number 1-1 Block Diagram (32-pin) .............................................................................................1-3 1-2 Block Diagram (44-pin) ..............................................................................

S3F80JB MICROCONTROLLER xv List of Tables Table Title Page Number Number 1-1 Pin Descriptions of 32-SOP ...................................................................................... 1-7 1-2 Pin Descriptions of 44-QFP .............................................................................

S3F80JB MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2 Address Spaces Setting the Register Pointers ...................................................................................................................... 2-11 Using the RPs to Calculate the Sum of a Ser...

S3F80JB MICROCONTROLLER xix List of Register Descriptions Register Full Register Name Page Identifier Number BTCON Basic Timer Control Register.................................................................................... 4-5 CACON Counter A Control Register ......................................

S3F80JB MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with carry .......................................................................................................... 6-14 ADD Add....................................................

xxii S3F80JB MICROCONTROLLER List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Number NEXT Next ..........................................................................................................................6-60 NOP No Operation .......................

S3F80JB PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8/S3F8-SERIES MICROCONTROLLERS Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include: — Effic...

PRODUCT OVERVIEW S3F80JB 1-2 FEATURES CPU • SAM8 RC CPU core Memory • Program memory: - 64-Kbyte Internal Flash Memory - Sector size: 128Bytes - 10years data retention - Fast Programming Time : Sector Erase: 10ms Byte Program: 32us - Byte Programmable - User programmable by ‘LDC’ instruction - Secto...

S3F80JB PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM (32-PIN PACKAGE) 8-Bit Timer0 /Counter P0.0-0.3 (INT0-INT3) P2.0-2.3 (INT5-INT8) P2.4-2.7 (INT9) (CIN0-CIN3) P3.0/T0PW M/T0CAP/SDAT/T1CAP/T2CAP P3.1/REM/T0CK/SCLK TEST P0.4-P0.7(INT4) P1.0-1.7 Port0 Port1 Port2 LVD IPOR(note) MainOSC 8-Bit Basic Timer 16-Bi...

S3F80JB PRODUCT OVERVIEW 1-5 PIN ASSIGNMENTS S3F80JB (Top View) 32-SOP 12345678910111213141516 VDDP3.1/REM/T0CK/SCLKP3.0/T0PW M/T0CAP/T1CAP/T2CAP/SDATP2.4/INT9/CIN0P2.3/INT8P2.2/INT7P2.1/INT6P2.0/INT5P0.7/INT4P0.6/INT4P0.5/INT4P0.4/INT4P0.3/INT3P0.2/INT2P0.1/INT1P0.0/INT0 323130292827262524232221201...

PRODUCT OVERVIEW S3F80JB 1-8 Table 1-2. Pin Descriptions of 44-QFP Pin Names Pin Type Pin Description Circuit Type 44 Pin No. Shared Functions P0.0–P0.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be...

PRODUCT OVERVIEW S3F80JB 1-10 PIN CIRCUITS V DD Pull-upEnable V DD INPUT/OUTPUT Pull-UpResistor(55k Ω - typ) Data V SS External Interrupt Output Disable Noise Filter MUX P2CONx.x CMPSEL.0-.3 P2.4-P2.7 Only + - REF External REF (P2.7 only) Comparator Stop StopRelease Figure 1-5. Pin Circuit Type 1 (P...

S3F80JB ADDRESS SPACE 2-1 2 ADDRESS SPACE OVERVIEW The S3F80JB microcontroller has two types of address space: — Internal program memory (Flash memory) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between t...

S3F80JB ADDRESS SPACES 2-2 PROGRAM MEMORY Program memory (Flash memory) stores program code or table data. The S3F80JB has 64-Kbyte of internal programmable Flash memory. The program memory address range is therefore 0000H–FFFFH of Flash memory (See Figure 2-1). The first 256 bytes of the program me...

S3F80JB ADDRESS SPACES 2-3 SMART OPTION Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH)....

S3F80JB ADDRESS SPACES 2-4 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must c...

S3F80JB ADDRESS SPACES 2-5 REGISTER ARCHITECTURE In the S3F80JB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte ar...

S3F80JB ADDRESS SPACES 2-6 Bank1 D0H CFH E0H DFH C0H Bank 0 System and Peripheral Control Register (Register Addressing Mode) System Register (Register Addressing Mode) Working Register (Working Register Addressing only) FFH Set 1 FFH Set 2 C0H Page 0 General Purpose Data Register (Indirect Register...

S3F80JB ADDRESS SPACES 2-8 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used ...

S3F80JB ADDRESS SPACES 2-9 PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressi...

S3F80JB ADDRESS SPACES 2-10 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte regi...

S3F80JB ADDRESS SPACES 2-11 USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses ...

S3F80JB ADDRESS SPACES 2-13 REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the co...

S3F80JB ADDRESS SPACES 2-15 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called ...

S3F80JB ADDRESS SPACES 2-16 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Example 1: LD 0C2H,40H ; Invalid addressing mode! Use work...

S3F80JB ADDRESS SPACES 2-18 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B. This 4...

S3F80JB ADDRESS SPACES 2-20 SYSTEM AND USER STACKS S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3F80JB architecture supports stack operations in the internal regis...

S3F80JB ADDRESS SPACES 2-21 PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL ← FFH ; (Normally, the SPL is set to 0FFH by the initialization...

S3F80JB ADDRESSING MODES 3-1 3 ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location...

S3F80JB ADDRESSING MODES 3-3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to ...

ADDRESSING MODES S3F80JB 3-4 INDIRECT REGISTER ADDRESSING MODE (Continued) dst OPCODE Points to Register Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in instruction OPERAND Register Pair Program Memory 16-BitAddress...

S3F80JB ADDRESSING MODES 3-7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access locations in the internal regis...

S3F80JB ADDRESSING MODES 3-9 INDEXED ADDRESSING MODE (Continued) Register File OPERAND Program Memory or Data Memory Point to W orking Register Pair LSB Selects 16-Bitaddressadded tooffset RP0 or RP1 MSB Points to RP0 or RP1 SelectedRP pointsto start ofworkingregisterblock Sample Instructions: LDC R...

ADDRESSING MODES S3F80JB 3-10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL...

S3F80JB ADDRESSING MODES 3-11 DIRECT ADDRESS MODE (Continued) OPCODE Program Memory Lower Address Byte ProgramMemoryAddressUsed Upper Address Byte Sample Instructions: JP C,JOB1 ; W here JOB1 is a 16-bit immediate address CALL DISPLAY ; W here DISPLAY is a 16-bit immediate address Next OPCODE Figure...

S3F80JB CONTROL REGISTERS 4- 1 4 CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3F80JB control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important fe...

CONTROL REGISTERS S3F80JB 4-2 Table 4-1. Mapped Registers (Bank0, Set1) Register Name Mnemonic Decimal Hex R/W Timer 0 Counter T0CNT 208 D0H R (NOTE) Timer 0 Data Register T0DATA 209 D1H R/W Timer 0 Control Register T0CON 210 D2H R/W Basic Timer Control Register BTCON 211 D3H R/W Clock Control Regis...

CONTROL REGISTERS S3F80JB 4-4 FLAGS - System Flags Register Bit IdentifierReset ValueRead/Write R = Read-onlyW = W rite-onlyR/W = Read/write' - ' = Not used Bit number:MSB = Bit 7LSB = Bit 0 Addressing mode ormodes you can use tomodify register values Description of theeffect of specificbit settings...

S3F80JB CONTROL REGISTERS 4-5 BTCON — Basic Timer Control Register D3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .4 Watchdog Timer Function Enable Bits (for System Reset)...

CONTROL REGISTERS S3F80JB 4-6 CACON — Counter A Control Register F3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Counter A Input Clock Selection Bits 0 0 f OSC 0 1 f O...

S3F80JB CONTROL REGISTERS 4-7 CLKCON — System Clock Control Register D4H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .5 Not used for S3F80JB .4 and .3 CPU Clock (System Clo...

CONTROL REGISTERS S3F80JB 4-8 CMOD — Comparator Mode Register E9H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Comparator Enable Bit 0 Comparator operation disable 1 Comparato...

S3F80JB CONTROL REGISTERS 4-9 CMPSEL — Comparator Input Selection Register EBH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W Addressing Mode Register addressing mode only .7– .4 Not used for S3F80JB. .3 P2.7 Function Selection Bit 0 ...

CONTROL REGISTERS S3F80JB 4-10 EMT — External Memory Timing Register (NOTE) FEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 1 1 1 1 1 0 – Read/Write R/W R/W R/W R/W R/W R/W R/W – Addressing Mode Register addressing mode only .7 External WAIT Input Function Enable Bit 0 Disable WA...

S3F80JB CONTROL REGISTERS 4-11 FLAGS — System Flags Register D5H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .7 Carry Flag Bit (C) 0 Operation does not generate a carry or borrow ...

CONTROL REGISTERS S3F80JB 4-12 FMCON — Flash Memory Control Register EFH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 – – – 0 Read/Write R/W R/W R/W R/W – – – R/W Addressing Mode Register addressing mode only .7 – .4 Flash Memory Mode Selection Bits 0101 Programming mode 101...

S3F80JB CONTROL REGISTERS 4-13 FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .0 Flash Memory Sector Address (High...

CONTROL REGISTERS S3F80JB 4-14 IMR — Interrupt Mask Register DDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0....

S3F80JB CONTROL REGISTERS 4-15 IPH — Instruction Pointer (High Byte) DAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .1 Instruction Pointer Address (High Byte) The high-byt...

CONTROL REGISTERS S3F80JB 4-16 IPR — Interrupt Priority Register FFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, ...

S3F80JB CONTROL REGISTERS 4-17 IRQ — Interrupt Request Register DCH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4 0 Not pendin...

CONTROL REGISTERS S3F80JB 4-18 LVDCON — LVD Control Register E0H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – – – – – – 0 Read/Write – – – – – – – R/W Addressing Mode Register addressing mode only .7 – .1 Not used for S3F80JB. .0 LVD Flag (2.3V) Indicator Bit 0 V DD ≥ LVD_FLAG L...

S3F80JB CONTROL REGISTERS 4-19 P0CONH — Port 0 Control Register (High Byte) E8H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P0.7/INT4 Mode Selection Bits 0 0 C-MOS inp...

CONTROL REGISTERS S3F80JB 4-20 P0CONL — Port 0 Control Register (Low Byte) E9H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P0.3/INT3 Mode Selection Bits 0 0 C-MOS inpu...

S3F80JB CONTROL REGISTERS 4-21 P0INT — Port 0 External Interrupt Enable Register F1H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT4) Enable Bit 0 D...

CONTROL REGISTERS S3F80JB 4-22 P0PND — Port 0 External Interrupt Pending Register F2H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT4) Pending Flag ...

S3F80JB CONTROL REGISTERS 4-23 P0PUR — Port 0 Pull-up Resistor Enable Register E7H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 Pull-up Resistor Enable Bit 0 Disable pull...

CONTROL REGISTERS S3F80JB 4-24 P1CONH — Port 1 Control Register (High Byte) EAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P1.7 Mode Selection Bits 0 0 C-MOS input mo...

S3F80JB CONTROL REGISTERS 4-25 P1CONL — Port 1 Control Register (Low Byte) EBH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P1.3 Mode Selection Bits 0 0 C-MOS input mod...

CONTROL REGISTERS S3F80JB 4-26 P2CONH — Port 2 Control Register (High Byte) ECH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P2.7/INT9 Mode Selection Bits 0 0 C-MOS inp...

S3F80JB CONTROL REGISTERS 4-27 P2CONL — Port 2 Control Register (Low Byte) EDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 P2.3/INT8 Mode Selection Bits 0 0 C-MOS inpu...

CONTROL REGISTERS S3F80JB 4-28 P2INT — Port 2 External Interrupt Enable Register E5H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P2.7 External Interrupt (INT9) Enable Bit 0 D...

S3F80JB CONTROL REGISTERS 4-29 P2PND — Port 2 External Interrupt Pending Register E6H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P2.7 External Interrupt (INT9) Pending Flag ...

CONTROL REGISTERS S3F80JB 4-30 P2PUR — Port 2 Pull-up Resistor Enable Register EEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P2.7 Pull-up Resistor Enable Bit 0 Disable pull...

S3F80JB CONTROL REGISTERS 4-31 P3CON — Port 3 Control Register EFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Package Selection and Alternative Function Select Bits 0...

CONTROL REGISTERS S3F80JB 4-32 NOTES : 1. The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which correspond to the following Port 3 pin functions (bit 6 is not used for the S3F80JB: a. Port3, bit 7: carrier signal on (“1”) or off (“0”). b. Port3, bit 1,0: P3.1/RE...

CONTROL REGISTERS S3F80JB 4-34 P4CON — Port 4 Control Register F0H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P4.7 Mode Selection Bit 0 Open-drain output mode 1 Push-pull ou...

S3F80JB CONTROL REGISTERS 4-37 PP — Register Page Pointer DFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .4 Destination Register Page Selection Bits 0 0 0 0 Destination: p...

S3F80JB CONTROL REGISTERS 4-39 SPL — Stack Pointer (Low Byte) D9H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only. .7 – .0 Stack Pointer Address (Low Byte) The SP value is undefined...

CONTROL REGISTERS S3F80JB 4-40 SYM — System Mode Register DEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – x x x 0 0 Read/Write R/W – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Tri-State External Interface Control Bit (1) 0 Normal operation (disable...

S3F80JB CONTROL REGISTERS 4-41 T0CON — Timer 0 Control Register D2H Set 1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .6 Timer 0 Input Clock Selection Bits 0 0 f OSC /4096 0 1 f...

CONTROL REGISTERS S3F80JB 4-42 T1CON — Timer 1 Control Register FAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Timer 1 Input Clock Selection Bits 0 0 f OSC /4 0 1 f O...

S3F80JB CONTROL REGISTERS 4-43 T2CON — Timer 2 Control Register E8H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Timer 2 Input Clock Selection Bits 0 0 f OSC /4 0 1 f O...

S3F80JB INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8/S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more ...

INTERRUPT STRUCTURE S3F80JB 5-2 INTERRUPT TYPES The three components of the S3C8/S3F8-series interrupt structure described above — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are...

S3F80JB INTERRUPT STRUCTURE 5-5 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80JB interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH (See Figure 5-3). You can allocate unused locations in the vector address area as normal pro...

S3F80JB INTERRUPT STRUCTURE 5-7 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur, and according to the established priorities. NOTE: The system initialization routi...

INTERRUPT STRUCTURE S3F80JB 5-8 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by a specific interrupt level and source. The system-level control points in the interrupt structure are, therefore: — Global interrupt enable and disable (by...

S3F80JB INTERRUPT STRUCTURE 5-9 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (See Table 5-3). Table 5-3. Vectored Interrupt Source Control and Data Regi...

S3F80JB INTERRUPT STRUCTURE 5-11 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set 1, Bank0) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required se...

INTERRUPT STRUCTURE S3F80JB 5-12 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set 1, Bank 0), is used to set the relative priorities of the interrupt levels used in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must ...

S3F80JB INTERRUPT STRUCTURE 5-15 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine. P...

INTERRUPT STRUCTURE S3F80JB 5-16 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that ...

S3F80JB INTERRUPT STRUCTURE 5-17 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt ...

S3F80JB INSTRUCTION SET 6-1 6 INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set incl...

INSTRUCTION SET S3F80JB 6-2 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst, src Load LDB dst, src Load bit LDE dst, src Load external data memory LDC dst, src Load program memory LDED dst, src Load external data memory and decrement LDCD dst...

S3F80JB INSTRUCTION SET 6-7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specif...

INSTRUCTION SET S3F80JB 6-8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffe...

S3F80JB INSTRUCTION SET 6-9 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rb Bit (b) of working register Rn.b (n = 0–15, b = 0–7) r0 Bit 0 (LSB) of working regist...

INSTRUCTION SET S3F80JB 6-10 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC R1 INC IR1 SUB r...

INSTRUCTION SET S3F80JB 6-12 CONDITION CODES The op-code of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare op...

S3F80JB INSTRUCTION SET 6-13 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is i...

INSTRUCTION SET S3F80JB 6-14 ADC — Add with carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement additio...

S3F80JB INSTRUCTION SET 6-15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the...

INSTRUCTION SET S3F80JB 6-16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two ...

S3F80JB INSTRUCTION SET 6-17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in...

INSTRUCTION SET S3F80JB 6-18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffe...

S3F80JB INSTRUCTION SET 6-19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cle...

INSTRUCTION SET S3F80JB 6-20 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 0 2 4 7...

S3F80JB INSTRUCTION SET 6-21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 1 2 4 77 rb...

INSTRUCTION SET S3F80JB 6-22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in ...

S3F80JB INSTRUCTION SET 6-23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to th...

INSTRUCTION SET S3F80JB 6-24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the...

S3F80JB INSTRUCTION SET 6-25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored ...

INSTRUCTION SET S3F80JB 6-26 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instr...

S3F80JB INSTRUCTION SET 6-27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other fl...

INSTRUCTION SET S3F80JB 6-28 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R 4 B1 IR Examples: Given: Register 00H = 4FH, register 01H = 02H, and regist...

S3F80JB INSTRUCTION SET 6-29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: ...

INSTRUCTION SET S3F80JB 6-30 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" oc...

S3F80JB INSTRUCTION SET 6-31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the ...

INSTRUCTION SET S3F80JB 6-32 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added...

S3F80JB INSTRUCTION SET 6-33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (...

INSTRUCTION SET S3F80JB 6-34 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD R1,R0 ; C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH DA R1 ; R1 ← 3...

S3F80JB INSTRUCTION SET 6-35 DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow o...

INSTRUCTION SET S3F80JB 6-36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Unaffected. Z: Set if the r...

S3F80JB INSTRUCTION SET 6-37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU wil...

INSTRUCTION SET S3F80JB 6-38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bit...

S3F80JB INSTRUCTION SET 6-39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program ...

INSTRUCTION SET S3F80JB 6-40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while inte...

S3F80JB INSTRUCTION SET 6-41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the i...

INSTRUCTION SET S3F80JB 6-42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction po...

S3F80JB INSTRUCTION SET 6-43 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Cycles ...

INSTRUCTION SET S3F80JB 6-44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overfl...

S3F80JB INSTRUCTION SET 6-45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected. Z: Set if the result is ...

INSTRUCTION SET S3F80JB 6-46 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program cou...

S3F80JB INSTRUCTION SET 6-47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction fol...

INSTRUCTION SET S3F80JB 6-48 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; other...

S3F80JB INSTRUCTION SET 6-49 LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src dst | opc src 2 4 rC r IM 4 r8 r R src | opc dst ...

INSTRUCTION SET S3F80JB 6-50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0,#10H → R0 = 10H LD R0,01H → R0 = 20H, register 01H = 20H LD 01H,R0 → Register 01H = 01H, R0 = 01H LD R1,@R...

S3F80JB INSTRUCTION SET 6-51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the ...

INSTRUCTION SET S3F80JB 6-52 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or...

INSTRUCTION SET S3F80JB 6-54 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working ...

S3F80JB INSTRUCTION SET 6-55 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working ...

INSTRUCTION SET S3F80JB 6-56 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working reg...

S3F80JB INSTRUCTION SET 6-57 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working reg...

INSTRUCTION SET S3F80JB 6-58 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 8 C4 RR RR 8 C...

S3F80JB INSTRUCTION SET 6-59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination addres...

INSTRUCTION SET S3F80JB 6-60 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then increment...

S3F80JB INSTRUCTION SET 6-61 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) o...

INSTRUCTION SET S3F80JB 6-62 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored wheneve...

S3F80JB INSTRUCTION SET 6-63 POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Cycles Opcode (Hex) Addr Mode ...

INSTRUCTION SET S3F80JB 6-64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The...

S3F80JB INSTRUCTION SET 6-65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination...

INSTRUCTION SET S3F80JB 6-66 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top ...

S3F80JB INSTRUCTION SET 6-67 PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed...

INSTRUCTION SET S3F80JB 6-68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location ad...

S3F80JB INSTRUCTION SET 6-69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 CF Example: Given: C = "1" or "...

INSTRUCTION SET S3F80JB 6-70 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the ...

S3F80JB INSTRUCTION SET 6-71 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag....

INSTRUCTION SET S3F80JB 6-72 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial va...

S3F80JB INSTRUCTION SET 6-73 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n ) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C)....

INSTRUCTION SET S3F80JB 6-74 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the init...

S3F80JB INSTRUCTION SET 6-75 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: Bytes Cycles Opc...

INSTRUCTION SET S3F80JB 6-76 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some KS88-series microcontr...

S3F80JB INSTRUCTION SET 6-77 SBC — Subtract With Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Sub...

INSTRUCTION SET S3F80JB 6-78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to l...

S3F80JB INSTRUCTION SET 6-79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bi...

INSTRUCTION SET S3F80JB 6-80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7), RP0 (3) ← 0 RP1 (4–...

S3F80JB INSTRUCTION SET 6-81 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data regist...

INSTRUCTION SET S3F80JB 6-82 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the sour...

S3F80JB INSTRUCTION SET 6-83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 7 0 4 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit...

INSTRUCTION SET S3F80JB 6-84 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source o...

S3F80JB INSTRUCTION SET 6-85 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), whi...

INSTRUCTION SET S3F80JB 6-86 WFI — Wait For Interrupt WFI Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt . Flags: No flags a...

S3F80JB INSTRUCTION SET 6-87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the ...

S3F80JB CLOCK CIRCUITS 7-1 7 CLOCK CIRCUITS OVERVIEW The clock frequency for the S3F80JB can be generated by an external crystal or supplied by an external clock source. The clock frequency for the S3F80JB can range from 1MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON registe...

CLOCK CIRCUITS S3F80JB 7-2 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. When stop mode is released, the oscillator starts by a reset operation or by an external interrupt. To...

S3F80JB CLOCK CIRCUITS 7-3 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H, Set1, Bank0. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value The CLKCON.7 - .5 and CLKCON.2- .0 Bit are not use...

S3F80JB RESET 8-1 8 RESET OVERVIEW Resetting the MCU is the function to start processing by generating reset signal using several reset schemes. During reset, most control and status are forced to initial values and the program counter is loaded from the reset vector. In case of S3F80JB, reset vecto...

RESET S3F80JB 8-2 nRESET Watchdog Timer (smart option bit[7] @03FH) IPOR / LVD Contorl Bit '1' STOP (EI)external interrupt enable P0&P2 (INT0-INT9) STOP IPOR / LVD Contorl Bit '1' ( smart option bit[7] @03FH) LVD STOP IPOR IPOR / LVD Contorl Bit '1' ( smart option bit[7] @03FH) (smart option bit...

S3F80JB RESET 8-3 P0&P2 (INT0~INT9) Noise Filter External Interrupt Control Block P0& P2 STOP STOPCON IPOR / LVD Control Bit '1' smart option bit[7] @03FH Enabled INT0~INT9 SED&R Circuit P0& P2.4-P2.7 STOP STOPCON IPOR / LVD Control Bit '1' smart option bit[7] @03FH Noise Filter Rese...

RESET S3F80JB 8-4 RESET MECHANISM The interlocking work of reset pin and LVD circuit supplies two operating modes: back-up mode input, and system reset input. Back-up mode input automatically creates a chip stop state when the reset pin is set to low level or the voltage at V DD is lower than V LVD ...

S3F80JB RESET 8-5 NOTES 1. IPOR / LVD Control Bit is one of smart option bits assigned address 03FH. User can enable / disable LVD in the stop mode by manipulating this bit. When the value is ‘1’, LVD always operate in the normal and stop mode. When the value is ‘0’, LVD is disabled in the stop mode...

RESET S3F80JB 8-6 Voltage [V] Time Reset pulse Va Reset Pulse W idth V DD V IH = 0.85 V DD V IL = 0.4 V DD T VDD = 1ms (V DD Rising Time) V DD Figure 8-5. Timing Diagram for Internal Power-On Reset Circuit NOTE The system reset operation depends on the interlocking work of the reset pin, LVD circuit...

S3F80JB RESET 8-7 V LVD V DD 0.4V DD a. System reset is not occurred.b. System reset is occurred by internal POR circuit. If "Vreset > VIH", the operating status is in STOP mode and IPOR / LVD control bit of smartoption is '0', LVD circuit is disabled in the S3F80JB. Va b NOTE: Va is a sc...

S3F80JB RESET 8-9 POWER-DOWN MODES The power down mode of S3F80JB are described following that: — Idle mode — Back- up mode — Stop mode IDLE MODE Idle mode is invoked by the instruction IDLE (op-code 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During Idle mode...

RESET S3F80JB 8-10 BACK-UP MODE For reducing current consumption, S3F80JB goes into Back-up mode. If external reset pin is low state or a falling level of V DD is detected by LVD circuit on the point of V LVD , chip goes into the back-up mode. Because CPU and peripheral operation were stopped due to...

S3F80JB RESET 8-11 STOP MODE STOP mode is invoked by executing the instruction ‘STOP’, after setting the stop control register (STOPCON). In STOP mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the current consumption can be reduced. All s...

RESET S3F80JB 8-12 SOURCES TO RELEASE STOP MODE Stop mode is released when following sources go active: — System Reset by external reset pin (nRESET) — System Reset by Internal Power-On Reset (IPOR) — Low Voltage Detector (LVD) — External Interrupt (INT0-INT9) — SED & R circuit Using nRESET Pin ...

S3F80JB RESET 8-13 SED&R (Stop Error Detect and Recovery) The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0 and P2.4-P2.7. One is re...

RESET S3F80JB 8-14 SYSTEM RESET OPERATION System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal CPU and peripheral modules. This procedure brings the S3F80JB into a known operating status. To allow time for internal CPU clock oscillation ...

RESET S3F80JB 8-16 Table 8-3. Set 1, Bank 0 Register Values After Reset (Continued) Address Bit Values After Reset Register Name Mnemonic Dec Hex 7 6 5 4 3 2 1 0 Port 1 Control Register (High Byte) P1CONH 234 EAH 1 1 1 1 1 1 1 1 Port 1 Control Register (Low Byte) P1CONL 235 EBH 0 0 0 0 0 0 0 0 Port ...

RESET S3F80JB 8-18 Table 8-5. Reset Generation According to the Condition of Smart Option Smart option7th bit @3FH Mode Reset Source 1 0 Reset Pin O Reset O Reset Watch Dog Timer Enable O Reset O Reset IPOR X Continue X Continue LVD O Reset O Reset External Interrupt (EI) P0 and P2 X External ISR X ...

S3F80JB RESET 8-19 RECOMMENDATION FOR UNUSUED PINS To reduce overall power consumption, please configure unused pins according to the guideline description Table 8-6. Table 8-6. Guideline for Unused Pins to Reduced Power Consumption Pin Name Recommend Example Port 0 • Set Input mode • Enable Pull-up...

RESET S3F80JB 8-20 SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS For more understanding, please see the below description Table 8-7. Table 8-7. Summary of Each Mode Item/Mode Back-up Reset Status Stop Approach Condition • External nRESET pin is low level state or V DD is lower than V LV...

S3F80JB I/O PORTS 9-1 9 I/O PORTS OVERVIEW The S3F80JB microcontroller has two kinds of package and different I/O number relating to the package type: 44-QFP package has five bit-programmable I/O ports, P0–P3 and P4. Four ports, P0–P2 and P4, are 8-bit ports and P3 is a 6-bit port. This gives a tota...

I/O PORTS S3F80JB 9-2 Table 9-1. S3F80JB Port Configuration Overview (44-QFP) Port Configuration Options Port 0 8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enab...

S3F80JB I/O PORTS 9-3 Table 9-3. S3F80JB Port Configuration Overview (32-SOP) Port Configuration Options Port 0 8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enab...

I/O PORTS S3F80JB 9-4 PORT DATA REGISTERS Table 9-4 gives you an overview of the register locations of all four S3F80JB I/O port data registers. Data registers for ports 0,1,2 and 4 have the general format shown in Figure 9-1. NOTE The data register for port 3, P3, contains 6-bits for P3.0–P3.5, and...

S3F80JB I/O PORTS 9-5 PULL-UP RESISTOR ENABLE REGISTERS You can assign pull-up resistors to the pin circuits of individual pins in port0 and port2. To do this, you make the appropriate settings to the corresponding pull-up resistor enable registers; P0PUR and P2PUR. These registers are located in se...

S3F80JB BASIC TIMER and TIMER 0 10-1 10 BASIC TIMER and TIMER 0 OVERVIEW The S3F80JB has two default timers: the 8-bit basic timer and the 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0 . BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a ...

S3F80JB BASIC TIMER and TIMER 0 10-3 BASIC TIMER FUNCTION DESCRIPTION Watch-dog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than '1010B'. (The '1010B' value disables the watch-dog function.) A reset clears B...

BASIC TIMER and TIMER 0 S3F80JB 10-4 TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Select the timer 0 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 0 input clock frequency — Clear the timer 0 counter, T0CNT — Enable the timer 0 ove...

BASIC TIMER and TIMER 0 S3F80JB 10-6 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors FAH and FCH) The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture interrupt (T0INT). T0OVF is interrupt with level IRQ0 and vector FAH...

S3F80JB BASIC TIMER and TIMER 0 10-7 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to th...

BASIC TIMER and TIMER 0 S3F80JB 10-8 Capture Mode In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter value into the T0 data register. You can select rising or falling edges to trigger this operation. Timer 0 also gives you capture input source...

S3F80JB BASIC TIMER and TIMER 0 10-9 MUX MUX DIV R 8-Bit Up-Counter (T0CNT) 8-Bit Compatator Timer 0 Buffer Register Bits 5, 4 Bit 0 Bit 1 IRQ0 Clear Data Bus Bit 0 IRQ0 OVF 8-Bit Up Counter (BTCNT, Read-Only) DIV R X IN X IN OVF RESET Data Bus Clear W hen BTCNT.4 is set after releasing fromRESET or...

BASIC TIMER and TIMER 0 S3F80JB 10-10 PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications: ORG 0100H RESET DI ; Disable all interrupts LD BTCON,#0AAH ; Disable the watchdog timer LD CLKCON,#18H ; Non-divided clock CLR SYM ; Disab...

S3F80JB BASIC TIMER and TIMER 0 10-11 PROGRAMMING TIP — Programming Timer 0 This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows: — Timer 0 i...

BASIC TIMER and TIMER 0 S3F80JB 10-12 PROGRAMMING TIP — Programming Timer 0 (Continued) CP R0,#32H ; 50 × 4 = 200 ms JR ULT,NO_200MS_SET BITS R1.2 ; Bit setting (61.2H) NO_200MS_SET: LD T0CON,#42H ; Clear pending bit POP RP0 ; Restore register pointer 0 value T0OVER IRET ; Return from interrupt serv...

S3F80JB TIMER 1 11-1 11 TIMER 1 OVERVIEW The S3F80JB microcontroller has a 16-bit timer/counter called Timer 1 (T1). For universal remote controller applications, Timer 1 can be used to generate the envelope pattern for the remote controller signal. Timer 1 has the following components: — One contro...

TIMER 1 S3F80JB 11-2 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the 16-bit up counter. When you set the Timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is generated each time the 16-...

S3F80JB TIMER 1 11-3 TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match condition is detected by the 16-bit co...

S3F80JB COUNTER A 12-1 12 COUNTER A OVERVIEW The S3F80JB microcontroller has one 8-bit counter called counter A. Counter A, which can be used to generate the carrier frequency, has the following components (See Figure 12-1): — Counter A control register, CACON — 8-bit down counter with auto-reload f...

S3F80JB COUNTER A 12-3 COUNTER A CONTROL REGISTER (CACON) The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON contains control settings for the following functions (See Figure 12-2): — Counter A clock source selection — Counter A interrupt en...

COUNTER A S3F80JB 12-4 COUNTER A PULSE WIDTH CALCULATIONS t LOW t HIGH t LOW To generate the above repeated waveform consisted of low period time , t LOW , and high period time, t HIGH. When CAOF = 0, t LOW = (CADATAL + 2) × 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock. t HIGH = (C...

S3F80JB COUNTER A 12-5 High High Counter A Clock 0H CAOF = '0'CADATAL = 01-FFHCADATAH = 00H CAOF = '0'CADATAL = 00HCADATAH = 01-FFH CAOF = '0'CADATAL = 00HCADATAH = 00H CAOF = '1'CADATAL = 00HCADATAH = 00H Low Low Counter A Clock 0H CAOF = '1'CADATAL = DEHCADATAH = 1EH CAOF = '0'CADATAL = DEHCADATAH...

COUNTER A S3F80JB 12-6 PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1 This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are: 17....

S3F80JB COUNTER A 12-7 PROGRAMMING TIP — To generate a one-pulse signal through P3.1 This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40 µ s width pulse. The program parameters are: 40 us — Counter A is ...

TIMER 2 S3F80JB 13-2 TIMER 2 OVERFLOW INTERRUPT Timer 2 can be programmed to generate an overflow interrupt (IRQ3, F0H) whenever an overflow occurs in the 16-bit up counter. When you set the timer 2 overflow interrupt enable bit, T2CON.2, to “1”, the overflow interrupt is generated each time the 16-...

S3F80JB TIMER 2 13-3 TIMER 2 MATCH INTERRUPT Timer 2 can also be used to generate a match interrupt (IRQ3, vector F2H) whenever the 16-bit counter value matches the value that is written to the timer 2 reference data registers, T2DATAH and T2DATAL. When a match condition is detected by the 16-bit co...

S3F80JB COMPARATOR 14-1 14 COMPARATOR OVERVIEW P2.4, P2.5, P2.6 and P2.7 can be used as analog input pins for a comparator. The reference voltage for the 4-channel comparator can be supplied either internally or externally at P2.7. When an internal reference voltage is used, four channels (P2.4–P2.7...

COMPARATOR S3F80JB 14-2 MUX V DD Comparison Result Register (CMPREG) MUX MUX MUX CMPSEL_3 Ref (Internal) SCAN signal Ref (External) R R + - 1/2R Internal BUS NOTES: 1. INT occurs only for digital input selecting. If an analog input, any INT doesn't occur.2. The comparison results of CIN0,CIN1,CIN2 a...

S3F80JB COMPARATOR 14-3 COMPARATOR OPERATION The comparator compares input analog voltage at CIN0–CIN3 with an external or internal reference voltage (V REF ) that is selected by the CMOD register. The result is written to the comparison result register CMPREG at address EAH, Set1, Bank1. The compar...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-1 15 EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80JB has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in ...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-3 ISP TM (ON-BOARD PROGRAMMING) SECTOR ISP TM sectors located in program memory area can store On Board Program Software (Boot program code for upgrading application code by interfacing with I/O port pin). The ISP TM sectors can’t be erased or programmed by...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-5 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) i...

EMBEDDED FLASH MEMORY INTERFACE S3F80JB 15-6 FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) FLASH MEMORY CONTROL REGISTER (FMCON) FMCON register is available only in user program mode to select the flash memory operation mode; sector erase, byte programming, and to make the flash memory into a h...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-7 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Address Se...

EMBEDDED FLASH MEMORY INTERFACE S3F80JB 15-8 SECTOR ERASE User can erase a flash memory partially by using sector erase function only in user program mode. The only unit of flash memory to be erased in the user program mode is a sector. The program memory of S3F80JB, 64Kbytes flash memory, is divide...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-9 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 2. Set Flash Memory Sector Address Register (FMSECH and FMSECL). 3. Set Flash Memory Control Register (FMCON) to “10100001B”. 4. S...

EMBEDDED FLASH MEMORY INTERFACE S3F80JB 15-10 PROGRAMMING TIP — Sector Erase Case1. Erase one sector • • ERASE_ONESECTOR: SB1 LD FMUSR,#0A5H ; User program mode enable LD FMSECH,#40H ; Set sector address 4000H,sector 128, LD FMSECL,#00H ; among sector 0~511 LD FMCON,#10100001B ; Select erase mode en...

EMBEDDED FLASH MEMORY INTERFACE S3F80JB 15-12 PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by ‘LDC’ instruction. The program procedure in user program mode 1. Must erase target sectors before programming. 2. Set Flash Memory ...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-13 SB1 Start ; Select Bank1 ; User Program Mode Enable ; Set Secotr Base Address ; Write data at flash ; User Program Mode Disable FMSECH High Address of Sector FMSECL Low Address of Sector R(n) High Address to W rite R(n+1) Low Address to W rite R(data) 8-...

EMBEDDED FLASH MEMORY INTERFACE S3F80JB 15-14 SB1 Start ; Select Bank1 ; User Program Mode Enable ; Set Secotr Base Address ; Write data at flash ; User Program Mode Disable FMSECH High Address of Sector FMSECL Low Address of Sector R(n) High Address to W rite R(n+1) Low Address to W rite R(data) 8-...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-15 PROGRAMMING TIP — Programming Case1. 1-Byte Programming • • WR_BYTE: ; Write data “AAH” to destination address 4010H SB1 LD FMUSR,#0A5H ; User program mode enable LD FMCON,#01010000B ; Selection programming mode LD FMSECH, #40H ; Set the base address of ...

S3F80JB EMBEDDED FLASH MEMORY INTERFACE 15-17 READING The read operation starts by ‘LDC’ instruction. The program procedure in user program mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working...

EMBEDDED FLASH MEMORY INTERFACE S3F80JB 15-18 HARD LOCK PROTECTION User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area. This pr...

S3F80JB LOW VOLTAGE DETECTOR 16-1 16 LOW VOLTAGE DETECTOR OVERVIEW The S3F80JB micro-controller has a built-in Low Voltage Detector (LVD) circuit, which allows LVD and LVD_FLAG detection of power voltage. The S3F80JB has two options in LVD and LVD_FLAG voltage level according to the operating freque...

LOW VOLTAGE DETECTOR S3F80JB 16-2 NOTES 1. When smart option bit is set “1”, operating frequency is selected 8MHz and LVD voltage level is 2.3V. On the other hand, when smart option bit is set “0”, operating frequency is selected 4MHz and LVD voltage level is 2.15V. 2. When smart option bit is set “...

S3F80JB LOW VOLTAGE DETECTOR 16-3 LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON) LVDCON.0 is used flag bit to indicate low battery in IR application or others. When LVD circuit detects LVD_FLAG, LVDCON.0 flag bit is set automatically. The reset value of LVDCON is #00H. Low Voltage Detect Control Reg...

S3F80JB ELECTRICAL DATA (4MHz) 17-1 17 ELECTRICAL DATA – 4MHz OVERVIEW In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute Maximum Ratings — D.C. Electrical Characteristics — Characteristics of Low Vol...

ELECTRICAL DATA (4MHz) S3F80JB 17-8 Execution of STOP Instrction ~ ~ V DDDR ~ ~ Stop Mode Idle Mode (Basic Timer Active) Data Retention Mode t WAIT EXT INT V DD Normal Operating Mode 0.2V DD 0.8V DD Figure 17-7. Stop Mode Release Timing When Initiated by an External Interrupt V DD ~ ~ NormalOperatin...

S3F80JB ELECTRICAL DATA (4MHz) 17-13 Minimun Instruction Clock 1kHz f OSC (Main Oscillator Frequency) 1 2 3 4 5 Supply Voltage (V) Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16)A: 1.7 V, 4 MHz 250 kHz 1MHz 1.5MHz 2 MHz 8 MHz 6 MHz 4 MHz 400 kHz 6 7 500 kHz A 1 MHz 2 MHz...

S3F80JB ELECTRICAL DATA (8MHz) 18-1 18 ELECTRICAL DATA – 8MHZ OVERVIEW In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute Maximum Ratings — D.C. Electrical Characteristics — Characteristics of Low Vol...

ELECTRICAL DATA (8MHz) S3F80JB 18-8 Execution of STOP Instrction ~ ~ V DDDR ~ ~ Stop Mode Idle Mode (Basic Timer Active) Data Retention Mode t WAIT EXT INT V DD Normal Operating Mode 0.2V DD 0.8V DD Figure 18-7. Stop Mode Release Timing When Initiated by an External Interrupt V DD ~ ~ NormalOperatin...

S3F80JB ELECTRICAL DATA (8MHz) 18-13 Minimun Instruction Clock 1kHz f OSC (Main Oscillator Frequency) 1 2 3 4 5 Supply Voltage (V) Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16)A: 1.95 V, 8 MHz 250 kHz 1MHz 1.5MHz 2 MHz 8 MHz 6 MHz 4 MHz 400 kHz 6 7 500 kHz A 1 MHz 2 MH...

S3F80JB MECHANICAL DATA 19-1 19 MECHANICAL DATA OVERVIEW The S3F80JB microcontroller is currently available in a 32-pin SOP and 44-pin QFP package. 32-SOP-450A 20.30 MAX 19.90 ± 0.20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.4 3 8 .34 ± 0.20 0.9 0 ± 0. 2 0 0. 05 MI N 2.00 ± 0.10 2.20 MAX 0.10 MAX 1.27 NOTE:...

S3F80JB DEVELOPMENT TOOLS DATA 20-1 20 DEVELOPMENT TOOLS DATA OVERVIEW Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard com...

DEVELOPMENT TOOLS DATA S3F80JB 20-2 TB80JB TARGET BOARD The TB80JB target board is used for the S3F80JB microcontrollers. It is supported by OPENice-i500 (In-Circuit Emulator). TB80JB Rev1 100 -P in C o n nec to r 25 1 To User_Vcc Off On 144 QFP S3E80JB EVA Chip 74HC11 U2 SMDS2 SMDS2+ RESET + IDLE S...

S3F80JB DEVELOPMENT TOOLS DATA 20-3 Table 20-1. Components Consisting of S3F80JB Target Board Block Symbols OPEN-i500 Connector J1A Connection debugging signals between emulator and 80JB EVA target board. TEST Board Connector J2 Connection between target board and remocon application board. RESET Bl...

DEVELOPMENT TOOLS DATA S3F80JB 20-6 SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit emulator solution covers a wide range of capab...

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C8 SERIES MASK ROM ORDER FORM Product description: Device Number: S3C80JB S3F80JB S3C8__________- _...

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3F8 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information: Company Name: _____________...

FLASH APPLICATION NOTES S3F80JB Programming By Tool

S3F80JB 1 TOOL PROGRAMMING OF S3F80JB To read/write/erase by OTP/MTP writer, the following six pins are used. Table 1. Descriptions of Pins Used to Read/Write/Erase the Flash in Tool Program Mode During Programming Normal Chip Pin Name Pin Name Pin No. I/O Function P3.0 SDAT 3[30] I/O Serial data pi...

Important Note Subject : Toggling phenomenon when serial writing programming on the S3F80JB.

Important Note S3F80JB 1 1. ANALYSIS RESULT When serial writing programming on S3F80JB, only port1.4,1.5,1.6,1.7 are affected by SDAT signal. This phenomenon is only port1.4,1.5,1.6,1.7 issues and in normal operating mode it never be occurred. 2. ANALYSIS OF PHENOMENON 2.1 FOR SERIAL PROGRAMMING MOD...

S3F80JB Important Note 2 2.2 FOR NORMAL OPERATING MODE The S3F80JB/9 is needed to nRESET pin = “1(VDD)” & TEST pin = “0(GND)” P1.4~1.7 When nRESET pin = “1(VDD)” & TEST pin = “0(GND)” In the Figure 2, because TEST signal is low(Logic level 0), “outdis” and “data” signal is same to MUX “0” si...