Excalibur Electronics A-MNL-NIOSPROG-01.1 - Manuals

Altera Corporation 1 Over vi e w 1 Overview Introduction The Nios TM embedded processor is a soft core CPU optimized for programmable logic and system-on-a-programmable chip (SOPC) integration. It is a configurable, general-purpose RISC processor that can be combined with user logic and programmed i...

2 Altera Corporation Overview The Nios CPU ships with the GNUPro compiler and debugger from Cygnus, an industry-standard open-source C/C++ compiler, linker and debugger toolkit. The GNUPro toolkit includes a C/C++ compiler, macro- assembler, linker, debugger, binary utilities, and libraries. Instruc...

16 Altera Corporation Overview Exceptions The topics in this section include a description of the following: ■ Exception vector table ■ How external hardware interrupts, internal exceptions, register window underflow, register window overflow and TRAP instructions are handled ■ Direct software excep...

Altera Corporation 33 2 3 2 -B it Inst ru ction Set This section provides a detailed description of the 32-bit Nios CPU instructions. The descriptions are arranged in alphabetical order according to instruction mnemonic. Each instruction page includes the following information: ■ Instruction mnemoni...

34 Altera Corporation 32-Bit Instruction Set ABS Absolute Value Operation: RA ← |RA| Assembler Syntax: ABS %rA Example: ABS %r6 Description: Calculate the absolute value of RA; store the result in RA. Condition Codes: Flags: Unaffected Instruction Format: Rw Instruction Fields: A = Register index of...

Altera Corporation 35 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set ADD Add Without Carry Operation: RA ← RA + RB Assembler Syntax: ADD %rA,%rB Example: ADD %L3,%g0 ; ADD %g0 to %L3 Description: Adds the contents of register A to register B and stores the result in register A. Condit...

36 Altera Corporation 32-Bit Instruction Set ADDI Add Immediate Operation: RA ← RA + (0x00.00 : K : IMM5) Assembler Syntax: ADDI %rA,IMM5 Example: Not preceded by PFX: ADDI %L5,6 ; add 6 to %L5 Preceded by PFX: PFX %hi(1000) ADDI %g3,%lo(1000) ; ADD 1000 to %g3 Description: Not preceded by PFX: Adds...

Altera Corporation 37 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set AND Bitwise Logical AND Operation: Not preceded by PFX: RA ← RA & RB Preceded by PFX: RA ← RA & (0x00.00 : K : IMM5) Assembler Syntax: Not preceded by PFX: AND %rA,%rB Preceded by PFX: PFX %hi(const) AND %rA,...

38 Altera Corporation 32-Bit Instruction Set ANDN Bitwise Logical AND NOT Operation: Not preceded by PFX: RA ← RA & ~RB Preceded by PFX: RA ← RA & ~(0x00.00 : K : IMM5) Assembler Syntax: Not preceded by PFX: ANDN %rA,%rB Preceded by PFX: PFX %hi(const) ANDN %rA,%lo(const) Example: Not preced...

Altera Corporation 39 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set ASR Arithmetic Shift Right Operation: RA ← (RA >> RB[4..0]), fill from left with RA[31] Assembler Syntax: ASR %rA,%rB Example: ASR %L3,%g0 ; shift %L3 right by %g0 bits Description: Arithmetically shift right t...

40 Altera Corporation 32-Bit Instruction Set ASRI Arithmetic Shift Right Immediate Operation: RA ← (RA >> IMM5), fill from left with RA[31] Assembler Syntax: ASRI %rA,IMM5 Example: ASRI %i5,6 ; shift %i5 right 6 bits Description: Arithmetically shift right the contents of RA by IMM5 bits. If I...

Altera Corporation 41 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set BGEN Bit Generate Operation: RA ← 2 IMM5 Assembler Syntax: BGEN %rA,IMM5 Example: BGEN %g7,6 ; set %g7 to 64 Description: Sets RA to an integer power-of-two with the exponent given by IMM5. This is equivalent to sett...

42 Altera Corporation 32-Bit Instruction Set BR Branch Operation: PC ← PC + (( σ (IMM11) + 1) << 1) Assembler Syntax: BR addr Example: BR MainLoop NOP ; (delay slot) Description: The offset given by IMM11 is interpreted as a signed number of half-words (instructions) relative to the instructio...

Altera Corporation 43 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set BSR Branch To Subroutine Operation: %o7 ← ((PC + 4) >> 1) PC ← PC + (( σ (IMM11) + 1) << 1) Assembler Syntax: BSR addr Example: BSR SendCharacter NOP ; (delay slot) Description: The offset given by IMM11 ...

44 Altera Corporation 32-Bit Instruction Set CALL Call Subroutine Operation: %o7 ← ((PC + 4) >> 1) PC ← (RA << 1) Assembler Syntax: CALL %rA Example: CALL %g0 NOP ; (delay slot) Description: The value of RA is shifted left by one and transferred into PC. RA contains the address of the ca...

Altera Corporation 45 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set CMP Compare Operation: ∅ ← RA − RB Assembler Syntax: CMP %rA,%rB Example: CMP %g0,%g1 ; set flags by %g0 - %g1 Description: Subtract the contents of RB from RA, and discard the result. Set the condition codes accordi...

46 Altera Corporation 32-Bit Instruction Set CMPI Compare Immediate Operation: ∅ ← RA – (0x00.00 : K : IMM5) Assembler Syntax: CMPI & %rA,IMM5 Example: Not preceded by PFX: CMPI %i3,24 ; compare %i3 to 24 Preceded by PFX: PFX %hi(1000) CMPI %i4,%lo(1000) Description: Not preceded by PFX: Subtrac...

Altera Corporation 55 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set IFRnz Equivalent to SKPRz Instruction Operation: if (RA = = 0)then begin if (Mem16[PC + 2] is PFX)then PC ← PC + 6 else PC ← PC + 4 end Assembler Syntax: IFRnz %rA Example: IFRnz %o3 BSR SendIt ; only call if %o3 is ...

56 Altera Corporation 32-Bit Instruction Set IFRz Equivalent to SKPRnz Instruction Operation: if (RA ! = 0)then begin if (Mem16[PC + 2] is PFX)then PC ← PC + 6 else PC ← PC + 4 end Assembler Syntax: IFRz %rA Example: IFRz %g3 BSR SendIt ; only call if %g3 is zero NOP ; (delay slot) executed in eithe...

Altera Corporation 57 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set IFS Conditionally Execute Next Instruction Operation: if (condition IMM4 is false)then begin if (Mem16[PC + 2] is PFX)then PC ← PC + 6 else PC ← PC + 4 end Assembler Syntax: IFS cc_IMM4 Example: IFS cc_ne BSR SendIt ...

58 Altera Corporation 32-Bit Instruction Set JMP Computed Jump Operation: PC ← (RA << 1) Assembler Syntax: JMP %rA Example: JMP %o7 ; return NOP ; (delay slot) Description: Jump to the target-address given by (RA << 1 ). Note that the target address will always be half-word aligned for a...

Altera Corporation 59 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set LD Load 32-bit Data From Memory Operation: Not preceded by PFX: RA ← Mem32[align32(RB)] Preceded by PFX: RA ← Mem32[align32(RB + σ (K) × 4))] Assembler Syntax: LD %rA,[%rB] Example: Not preceded by PFX: LD %g0,[%i3] ...

60 Altera Corporation 32-Bit Instruction Set LDP Load 32-bit Data From Memory (Pointer Addressing Mode) Operation: Not preceded by PFX: RA ← Mem32[align32(RP + (IMM5 × 4))] Preceded by PFX: RA ← Mem32[align32(RP + ( σ (K : IMM5) × 4))] Assembler Syntax: LDP %rA,[%rP,IMM5] Example: Not preceded by PF...

Altera Corporation 61 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set LDS Load 32-bit Data From Memory (Stack Addressing Mode) Operation: RA ← Mem32[align32(%sp + (IMM8 × 4))] Assembler Syntax: LDS %rA,[%sp,IMM8] Example: LDS %o1,[%sp,3] ; load %o1 from stack + 12 ; second register can...

62 Altera Corporation 32-Bit Instruction Set LRET Equivalent to JMP %o7 Operation: PC ← (%o7 << 1) Assembler Syntax: LRET Example: LRET ; return NOP ; (delay slot) Description: Jump to the target-address given by (%o7 << 1 ). Note that the target address will always be half-word aligned ...

Altera Corporation 63 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set LSL Logical Shift Left Operation: RA ← (RA << RB[4..0]), zero-fill from right Assembler Syntax: LSL %rA,%rB Example: LSL %L3,%g0 ; Shift %L3 left by %g0 bits Description: The value in RA is shifted-left by the ...

64 Altera Corporation 32-Bit Instruction Set LSLI Logical Shift Left Immediate Operation: RA ← (RA << IMM5), zero-fill from right Assembler Syntax: LSLI %rA,IMM5 Example: LSLI %i1,6 ; Shift %i1 left by 6 bits Description: The value in RA is shifted-left by the number of bits indicated by IMM5....

Altera Corporation 65 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set LSR Logical Shift Right Operation: RA ← (RA >> RB[4..0]), zero-fill from left Assembler Syntax: LSR %rA,%rB Example: LSR %L3,%g0 ; Shift %L3 right by %g0 bits Description: The value in RA is shifted-right by th...

66 Altera Corporation 32-Bit Instruction Set LSRI Logical Shift Right Immediate Operation: RA ← (RA >> IMM5), zero-fill from left Assembler Syntax: LSRI %rA,IMM5 Example: LSRI %g1,6 ; Right-shift %g1 by 6 bits Description: The value in RA is shifted-right by the number of bits indicated by IMM...

Altera Corporation 67 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set MOV Register-to-Register Move Operation: RA ← RB Assembler Syntax: MOV %rA,%rB Example: MOV %o0,%L3 ; copy %L3 into %o0 Description: Copy the contents of RB to RA. Condition Codes: Flags: Unaffected Instruction Forma...

68 Altera Corporation 32-Bit Instruction Set MOVHI Move Immediate Into High Half-Word Operation: h1 RA ← (K : IMM5), h0 RA unaffected Assembler Syntax: MOVHI %rA,IMM5 Example: Not preceded by PFX: MOVHI %g3,23 ; upper 16 bits of %g3 get 23 Preceded by PFX: PFX %hi(100) MOVHI %g3,%lo(100) ; upper 16 ...

Altera Corporation 69 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set MOVI Move Immediate Operation: RA ← (0x00.00 : K : IMM5) Assembler Syntax: MOVI %rA,IMM5 Example: Not preceded by PFX: MOVI %o3,7 ; load %o3 with 7 Preceded by PFX: PFX %hi(301) MOVI %o3,%lo(301) ; load %o3 with 301 ...

70 Altera Corporation 32-Bit Instruction Set MSTEP Multiply-Step Operation: If (R0[31] = = 1) then R0 ← (R0 << 1) + RA else R0 ← (R0 << 1) Assembler Syntax: MSTEP %rA Example: MSTEP %g1 ; accumulate partial-product Description: Implements a single step of an unsigned multiply. The multip...

Altera Corporation 71 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set MUL Multiply Operation: R0 ← (R0 & 0x0000.ffff) x (RA & 0x0000.ffff) Assembler Syntax: MUL %rA Example: MUL %i5 Description: Multiply the low half-words of %r0 and %rA together, and put the 32 bit result into...

72 Altera Corporation 32-Bit Instruction Set NEG Arithmetic Negation Operation: RA ← 0 – RA Assembler Syntax: NEG %rA Example: NEG %o4 Description: Negate the value of RA. Perform two’s complement negation of RA. Condition Codes: Flags: Unaffected Instruction Format: Rw Instruction Fields: A = Regis...

Altera Corporation 73 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set NOP Equivalent to MOV %g0, %g0 Operation: None Assembler Syntax: NOP Example: NOP ; do nothing Description: No operation. Condition Codes: Flags: Unaffected Instruction Format: RR Instruction Fields: None 15 14 13 12...

74 Altera Corporation 32-Bit Instruction Set NOT Logical Not Operation: RA ← ~RA Assembler Syntax: NOT %rA Example: NOT %o4 Description: Bitwise-invert the value of RA. Condition Codes: Flags: Unaffected Instruction Format: Rw Instruction Fields: A = Register index of operand RA 15 14 13 12 11 10 9 ...

Altera Corporation 75 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set OR Bitwise Logical OR Operation: Not preceded by PFX: RA ← RA | RB Preceded by PFX: RA ← RA | (0x00.00 : K : IMM5) Assembler Syntax: Not preceded by PFX: OR %rA,%rB Preceded by PFX: PFX %hi(const) OR %ra,%lo(const) E...

76 Altera Corporation 32-Bit Instruction Set PFX Prefix Operation: K ← IMM11 (K set to zero by all other instructions) Assembler Syntax: PFX IMM11 Example: PFX 3 ; affects next instruction Description: Loads the 11-bit constant value IMM11 into the K-register. The value in the K-register may affect ...

Altera Corporation 77 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set RDCTL Read Control Register Operation: RA ← CTLk Assembler Syntax: RDCTL %rA Example: Not preceded by PFX: RDCTL %g7 ; Loads %g7 from STATUS reg (%ctl0) Preceded by PFX: PFX 2 RDCTL %g7 ; Loads %g7 from WVALID reg (%...

78 Altera Corporation 32-Bit Instruction Set RESTORE Restore Caller’s Register Window Operation: CWP ← CWP + 1 if (old-CWP = = HI_LIMIT) then TRAP #2 Assembler Syntax: RESTORE Example: RESTORE ; bump up the register window Description: Moves CWP up by one position in the register file. If CWP is equ...

Altera Corporation 79 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set RET Equivalent to JMP %i7 Operation: PC ← (%i7 << 1) Assembler Syntax: RET Example: RET ; return RESTORE ; (restores caller’s register window) Description: Jump to the target-address given by (%i7 << 1 )....

80 Altera Corporation 32-Bit Instruction Set RLC Rotate Left Through Carry Operation: C ← RA[31] RA ← (RA << 1) : C Assembler Syntax: RLC %rA Example: RLC %i4 ; rotate %i4 left one bit Description: Rotates the bits of RA left by one position through the carry flag. Condition Codes: Flags: C: B...

Altera Corporation 81 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set RRC Rotate Right Through Carry Operation: C ← RA[0] RA ← C : (RA >> 1) Assembler Syntax: RRC %rA Example: RRC %i4 ; rotate %i4 right one bit Description: Rotates the bits of RA right by one position through the...

82 Altera Corporation 32-Bit Instruction Set SAVE Save Caller’s Register Window Operation: CWP ← CWP – 1 %sp ← %fp – (IMM8 × 4) If (old-CWP = = LO_LIMIT) then TRAP #1 Assembler Syntax: SAVE %sp,-IMM8 Example: SAVE %sp,-23 ; start subroutine with new regs ; first operand can only be %sp Description: ...

Altera Corporation 87 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set SKPRnz Skip If Register Not Equal To 0 Operation: if (RA ! = 0)then begin if (Mem16[PC + 2] is PFX)then PC ← PC + 6 else PC ← PC + 4 end Assembler Syntax: SKPRnz %rA Example: SKPRnz %g3 BSR SendIt ; only call if %g3 ...

88 Altera Corporation 32-Bit Instruction Set SKPRz Skip If Register Equals 0 Operation: if (RA = = 0)then begin if (Mem16[PC + 2] is PFX)then PC ← PC + 6 else PC ← PC + 4 end Assembler Syntax: SKPRz %rA Example: SKPRz %o3 BSR SendIt ; only call if %o3 is not 0 NOP ; (delay slot) executed in either c...

Altera Corporation 89 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set SKPS Skip On Condition Code Operation: if (condition IMM4 is true)then begin if (Mem16[PC + 2] is PFX)then PC ← PC + 6 else PC ← PC + 4 end Assembler Syntax: SKPS cc_IMM4 Example: SKPS cc_ne BSR SendIt ; only call if...

90 Altera Corporation 32-Bit Instruction Set ST Store 32-bit Data To Memory Operation: Not preceded by PFX: Mem32[align32(RB)] ← RA Preceded by PFX: Mem32[align32(RB + ( σ (K) × 4))] ← RA Assembler Syntax: ST [%rB],%rA Example: Not preceded by PFX: ST [%g0],%i3 ; %g0 is pointer, %i3 stored Preceded ...

Altera Corporation 95 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set STP Store 32-bit Data To Memory (Pointer Addressing Mode) Operation: Not preceded by PFX: Mem32[align32(RP + (IMM5 × 4))] ← RA Preceded by PFX: Mem32[align32(RP + ( σ (K : IMM5) × 4))] ← RA Assembler Syntax: STP [%rP...

96 Altera Corporation 32-Bit Instruction Set STS Store 32-bit Data To Memory (Stack Addressing Mode) Operation: Mem32[align32(%sp + (IMM8 × 4))] ← RA Assembler Syntax: STS [%sp,IMM8],%rA Example: STS [%sp,17],%i5 ; store %i5 at stack + 68 ; first register can only be %sp Description: Stores the 32-b...

Altera Corporation 99 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set SUB Subtract Operation: RA ← RA − RB Assembler Syntax: SUB %rA,%rB Example: SUB %i3,%g0 ; SUB %g0 from %i3 Description: Subtracts the contents of RB from RA, stores result in RA. Condition Codes: Flags: N: Result bit...

100 Altera Corporation 32-Bit Instruction Set SUBI Subtract Immediate Operation: RA ← RA − (0x00.00 : K : IMM5) Assembler Syntax: subi %rB,IMM5 Example: Not preceded by PFX: SUBI %L5,6 ; subtract 6 from %L5 Preceded by PFX: PFX %hi(1000) SUBI %o3,%lo(1000) ; subtract 1000 from %o3 Description: Not p...

Altera Corporation 101 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set SWAP Swap Register Half-Words Operation: RA ← h0 RA : h1 RA Assembler Syntax: SWAP %rA Example: SWAP %g3 ; Exchange two half-words in %g3 Description: Swaps (exchanges positions) of the two 16-bit half-word values i...

102 Altera Corporation 32-Bit Instruction Set TRAP Unconditional Trap Operation: ISTATUS ← STATUS IE ← 0 CWP ← CWP − 1 IPRI ← IMM6 %o7 ← ((PC + 2) >> 1) PC ← Mem32[VECBASE + (IMM6 × 4)] << 1 Assembler Syntax: TRAP IMM6 Example: TRAP 0 ; reset the board Description: CWP is decremented by ...

Altera Corporation 103 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set TRET Trap Return Operation: PC ← (RA << 1) STATUS ← ISTATUS Assembler Syntax: TRET %ra Example: TRET %o7 ; return from TRAP Description: Execution is transferred to the address given by (RA << 1). The va...

104 Altera Corporation 32-Bit Instruction Set WRCTL Write Control Register Operation: CTLk ← RA Assembler Syntax: WRCTL %rA Example: Not preceded by PFX: WRCTL %g7 ; writes %g7 to STATUS reg NOP ; required Preceded by PFX: PFX 1 WRCTL %g7 ; writes %g7 to ISTATUS reg Description: Not preceded by PFX:...

Altera Corporation 105 32323232 32-Bit Instruction Set 2 3 2 -B it Inst ru ction Set XOR Bitwise Logical Exclusive OR Operation: Not preceded by PFX: RA ← RA ⊕ RB Preceded by PFX: RA ← RA ⊕ (0x00.00 : K : IMM5) Assembler Syntax: Not preceded by PFX: XOR %rA,%rB Preceded by PFX: PFX %hi(const) XOR %r...

Altera Corporation 107 In dex 3 Numerics 5/16-bit Immediate Value 10 A About This Manual iiiABS instruction 34Absolute Value 34Absolute-Jump Instructions 15Add Immediate 36ADD instruction 35Add Without Carry 35ADDI instruction 36Addressing Modes 10AND instruction 37ANDN instruction 38Arithmetic Nega...