Page 3 - Contents
Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 3 Specification Update Contents Contents .............................................................................................................................3 Revision History .............
Page 4 - Revision History
4 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Revision History Revision Description Date -001 • Initial release of the Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 Sequence Spec...
Page 6 - Preface; Affected Documents
Preface 6 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a comp...
Page 7 - Nomenclature; QDF Number
Preface Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 7 Specification Update Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache s...
Page 8 - Summary Tables of Changes; Codes Used in Summary Table
Summary Tables of Changes 8 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, ...
Page 9 - Item Numbering
Summary Tables of Changes Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 9 Specification Update Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that...
Page 17 - Identification Information; CoreTM2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB; INTEL® CORETM2 DUO; INTEL® CORETM2 DUO
Identification Information Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 17 Specification Update Identification Information Figure 1. Intel ® Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB ATPO S/N INTEL ©'05 E4500 INTEL® CORE™...
Page 18 - CoreTM2 Duo Desktop Processor 4M SKU Package with 1066 MHz FSB; CoreTM2 Duo Desktop Processor 4M SKU Package with 1333 MHz FSB
Identification Information 18 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Figure 3. Intel ® Core™2 Duo Desktop Processor 4M SKU Package with 1066 MHz FSB ATPO S/N INTEL ©'05 INTEL® CORE™2 DUO 6700 SLxxx [COO] 2.66GHZ/4...
Page 19 - CoreTM2 Extreme Processor Package; INTEL® CORETM2 EXTREME
Identification Information Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 19 Specification Update Figure 5. Intel ® Core™2 Extreme Processor Package ATPO S/N INTEL ©'05 INTEL® CORE™2 EXTREME 6800 SLxxx [COO] 2.93GHZ/4M/1066/05B [FPO] M e 4 §
Page 20 - Component Identification; Conroe and Woodcrest Processor Family BIOS Writer’s Guide (BWG)
Component Identification Information 20 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Component Identification Information The Intel ® Core ™ 2 Extreme processor and Intel ® Core ™ 2 Duo desktop processor can be identifi...
Page 21 - CoreTM2 Duo Desktop Processor 2M SKU Identification Information; CoreTM2 Duo Desktop Processor 4M SKU Identification Information
Component Identification Information Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 21 Specification Update Table 1. Intel ® Core™2 Duo Desktop Processor 2M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor S...
Page 23 - Errata; Writing the Local Vector Table (LVT) when an Interrupt is Pending; be taken on the new interrupt vector even if the mask bit is set.; LOCK# Asserted During a Special Cycle Shutdown Transaction May; For the steppings affected, see the Summary Tables of Changes.; L2 ECC Errors May be Incorrect; address reported may be incorrect.
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 23 Specification Update Errata AI1. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LV...
Page 24 - DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Errata 24 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI4. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the ...
Page 25 - General Protection Fault (#GP) for Instructions Greater than 15
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 25 Specification Update Workaround: Use the IRET instruction to return from a system call, if RF flag has to be set after the return. Status: For the steppings affected, see the Summary Ta...
Page 26 - Mishandled; A Write to an APIC Register Sometimes May Appear to Have Not
Errata 26 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI10. Single Step Interrupts with Floating Point Exception Pending May Be Mishandled Problem: In certain circumstances, when a floating point exception (#MF) is pen...
Page 27 - Count Value for Performance-Monitoring Counter PMH_PAGE_WALK; Performance Monitoring Events for Retired Instructions (C0H) May
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 27 Specification Update Status: For the steppings affected, see the Summary Tables of Changes. AI13. Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May be Incorrect Problem: ...
Page 29 - Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 29 Specification Update ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boun...
Page 30 - Global Pages in the Data Translation Look-Aside Buffer (DTLB) May; The Resume from System Management Mode (RSM) instruction does not; Sequential Code Fetch to Non-canonical Address May have Non-
Errata 30 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Note that even if this combination of instructions is encountered, there is also a dependency on the internal pipelining and execution state of both instructions in...
Page 31 - VMCALL to Activate Dual-monitor Treatment of SMIs and SMM
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 31 Specification Update Workaround: If the last page of the positive canonical address space is not allocated for code (4K page at 00007ffffffff000 or 2M page at 00007fffffe00000) then the...
Page 32 - management related events for local core-specificity:; Invocation; memory load before getting the DNA exception.; Segment Limit Violation above 4-G Limit
Errata 32 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update The following Bus Performance Monitoring events will not count power management related events for local core-specificity: • BUS_TRANS_ IO (Event: 6CH) – Will not c...
Page 33 - EIP May be Incorrect after Shutdown in IA-32e Mode
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 33 Specification Update Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the 4G limit (0ffffffffh). Status: For the steppings affected, see the Sum...
Page 35 - Intel Architecture Software; Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 35 Specification Update Implication: In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the In...
Page 36 - REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
Errata 36 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Due to this erratum, a logical processor may not resume execution until the next targeted interrupt event or O/S timer tick following a locked store that spans acro...
Page 38 - Concurrent Multi-processor Writes to Non-dirty Page May Result in; Shutdown Condition May Disable Non-Bootstrap Processors
Errata 38 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI43. Concurrent Multi-processor Writes to Non-dirty Page May Re...
Page 39 - SYSCALL Immediately after Changing EFLAGS.TF May Not Behave
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 39 Specification Update Implication: Non-bootstrap logical processors in the package that have not observed the error condition may be disabled and may not respond to INIT#, SMI#, NMI#, SI...
Page 40 - IA32_FMASK is Reset during an INIT; Architecture Software Developer’s
Errata 40 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Implication: When the OS recovers from the second fault handler, the processor will no longer be in VM86 mode. Normally, operating systems should prevent interrupt ...
Page 41 - Last Branch Records (LBR) Updates May be Incorrect after a Task
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 41 Specification Update AI52. Last Branch Records (LBR) Updates May be Incorrect after a Task Switch Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value ...
Page 42 - Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Errata 42 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI55. Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior Problem: Memory type aliasing occurs when a single physical page is mapp...
Page 44 - Debug Register May Contain Incorrect Information on a MOVSS or
Errata 44 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to execute a MOV on debug registers in V86 mode, a debug exception will ...
Page 45 - LBR, BTS, BTM May Report a Wrong Address when an
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 45 Specification Update Implication: This scenario may only occur on a multiprocessor platform running an operating system that performs “lazy” TLB shootdowns. The memory image of the EFLA...
Page 46 - is Invalid
Errata 46 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI65. A Thermal Interrupt is Not Generated when the Current Temperature is Invalid Problem: When the DTS (Digital Thermal Sensor) crosses one of its programmed thre...
Page 47 - Performance Monitoring Event FP_ASSIST May Not be Accurate; CPL-Qualified BTS May Report Incorrect Branch-From Instruction
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 47 Specification Update AI68. Performance Monitoring Event FP_ASSIST May Not be Accurate Problem: Performance monitoring event FP_ASSIST (11H) may be inaccurate as assist events will be co...
Page 48 - PMI May Be Delayed to Next PEBS Event; An Asynchronous MCE During a Far Transfer May Corrupt ESP
Errata 48 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI71. PMI May Be Delayed to Next PEBS Event Problem: After a PEBS (Precise Event-Based Sampling) event, the PEBS index is compared with the PEBS threshold, and the ...
Page 49 - In Single-Stepping on Branches Mode, the BS Bit in the Pending-; B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 49 Specification Update Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a triple fault will occur due to the corrupted stack pointer, resul...
Page 52 - Frame
Errata 52 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update inaccurately also count certain other types of instructions resulting in higher than expected values. Implication: Performance Monitoring counter SIMD_INST_RETIRED ...
Page 53 - Microcode Updates Performed During VMX Non-root Operation Could; Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 53 Specification Update Implication: When this erratum occurs, the processor may live lock causing a system hang. Workaround: Do not perform unaligned accesses on paging structure entries....
Page 54 - Shootdown May Cause Unexpected Processor Behavior; Propagation of Page; Invalid Instructions May Lead to Unexpected Behavior
Errata 54 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Implication: When this erratum occurs, a non-accessed page which is present in memory and follows a page that contains the code segment limit may be tagged as acces...
Page 55 - Performance Monitoring Counter MACRO_INSTS.DECODED May Not; Optimizing the Front End; The Stack Size May be Incorrect as a Result of VIP/VIF Check on; Counted Incorrectly for PMULUDQ Instruction
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 55 Specification Update Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI94. Performance Monitoring Counter MACRO_INSTS.DECODED May Not...
Page 56 - Storage of PEBS Record Delayed Following Execution of MOV SS or; May Result in Improper Handling of Code #PF
Errata 56 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update undercount depends on actual occurrences of PMULUDQ instructions, while the counter is active. Workaround: None identified. Status: For the steppings affected, see ...
Page 57 - (E)CX May Get Incorrectly Updated When Performing Fast String REP
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 57 Specification Update • One of the following simultaneous exception conditions is present following the code transition o Code #DB and code #PF o Code Segment Limit Violation #GP and cod...
Page 58 - Performance Monitoring Event BR_INST_RETIRED May Count CPUID
Errata 58 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit address size. Implication: (E)CX may contain an incorrect count which may cause some of the...
Page 60 - VMCALL failure due to corrupt MSEG location may cause VM Exit to
Errata 60 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update the occurrence of a hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e. before the hardware PMI request). Implication: Following a PM...
Page 61 - VTPR Write Access During Event Delivery May Cause an APIC-Access
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 61 Specification Update AI110. VTPR Write Access During Event Delivery May Cause an APIC-Access VM Exit Problem: VTPR write accesses should not cause APIC-access VM exits but instead shoul...
Page 62 - When One Core Executes SEXIT the Other Core's Last Branch
Errata 62 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Status: For the steppings affected, see the Summary Tables of Changes. AI113. When One Core Executes SEXIT the Other Core's Last Branch Recording May be Incorrect P...
Page 63 - Use of Memory Aliasing with Inconsistent Memory Type may Cause a
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 63 Specification Update Status: For the steppings affected, see the Summary Tables of Changes. AI116. Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Mach...
Page 64 - VM Exit with Exit Reason “TPR Below Threshold” Can Cause the; Using Memory Type Aliasing with Cacheable and WC Memory Types
Errata 64 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI118. VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-Stat...
Page 65 - VM Exit due to Virtual APIC-Access May Clear RF
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 65 Specification Update AI120. VM Exit due to Virtual APIC-Access May Clear RF Problem: RF (Resume Flag), bit 16 of the EFLAGS/RFLAGS register, is used to restart instruction execution wit...
Page 66 - RSM Instruction Execution under Certain Conditions May Cause; Benign Exception after a Double Fault May Not Cause a Triple Fault
Errata 66 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit. Implication: IA32_MC1_STATUS MSR bit [60] may not reflect...
Page 67 - A VM Exit Due to a Fault While Delivering a Software Interrupt May
Errata Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 67 Specification Update Contributory Exceptions and Page Faults will cause a triple fault shutdown, whereas a benign exception may not. Implication: If a benign exception occurs while atte...
Page 68 - address-space size” VM-exit control is 1 in the executive VMCS.; A 64-bit Register IP-relative Instruction May Return Unexpected; register IP-relative instruction
Errata 68 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update exit. If this guideline is followed, that value will be 1 only if the “host address-space size” VM-exit control is 1 in the executive VMCS. Status: For the stepping...
Page 69 - Specification Changes
Specification Changes Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 69 Specification Update Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel ® Core™2 Extreme Processor X6800 and...
Page 70 - Specification Clarifications; Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS); of the
Specification Clarifications 70 Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel ® Core™2 Extrem...
Page 71 - Documentation Changes
Documentation Changes Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 71 Specification Update Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel ® Core™2 Extreme Processor X6800 and...
Asus 1001P-MU17-WT
User Manual
Asus 1 E1309
User Manual
Asus 1015E
User Manual
Asus 1064E - PIKE Storage Controller SAS
User Manual
Asus 136-480A
User Manual
Asus 1225 Series
User Manual
Asus 13VH192C
Manual
Asus 1U
User Manual
Asus 1U Rackmount Barebone Server RS160-E3/PS4
User Manual
Asus 200/266 MHZ FSB AGP 4X
User Manual
Asus 1U Rackmount Chassis Kit R10-A2P4
User Manual
Asus 24T1E
User Manual
Asus 22T1E
User Manual