Asus INTEL CUW(E)-FX- User Manual

P.7 /64 G0 G0 - - Global Working State Global Working State G1 G1 - - Global Sleeping State Global Sleeping State S1 : No system context is lost Î the STPCLK# signal goes active to the processor. Î CPU performs a Stop-Grant cycle. Î Cache coherency is maintained. S2 : Cache context is lost Î Not sup...

P.8 /64 MB MB Bootup Bootup South Bridge (ICH, PIIX4) ASUS ASIC (97127,99127) ATX Power Supply Wake On LANWake On RingWake by PS/2 KB Wake By RTCWake On USBAC Power Loss Restart PowerButton +3V ± 5V ± 12V

P.9 /64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3.3V * 3.3V * COM 5V COM 5V COM PW-OK 5VSB 12V 3.3V * -12V COM PS-ON COM COM COM -5V 5V 5V * optional South Bridge (ICH, PIIX4) ASUS ASIC (97127,99127) ATX Power Supply Wake Up EventsWOL,WOR, Wake by KB, AC Power Loss Restart PowerButton +3V...

P.11 /64 Motherboard in G3 Mechanical Off State Motherboard in G3 Mechanical Off State When the motherboard is not connected to When the motherboard is not connected to ATX power, there is only BATT(battery) ATX power, there is only BATT(battery) power on board. power on board. ‹ ACPI G3 mechanical ...

P.12 /64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3.3V * 3.3V * COM 5V COM 5V COM PW-OK 5VSB 12V 3.3V * -12V COM PS-ON COM COM COM -5V 5V 5V * optional ATX PWR A M R Socket 370 820 MCH LPC ICH FWH AC97 CODEC IDE FDD DIMM MTH AGPPRO SLOT ISA SLOT PCI-ISA Bridge ICH PCI SLOTS AUX ASUSASIC BA...

P.15 /64 CPU CPU Vcore Vcore Klamath PII Later Klamath PII Later ‹ 5 pins on the CPU to inform the motherboard what sort of core voltage it needs. ‹ VID0 ‹ VID1 ‹ VID2 ‹ VID3 ‹ VID4 The VID pins on the CPU are The VID pins on the CPU are not output signals : not output signals : ‹ Internally connect...

P.16 /64 CPU Core Frequency CPU Core Frequency PLL PLL ‹ Phase Lock Loop f f out out = N * f = N * f in in f f in in = FSB frequency = FSB frequency N N = Frequency multiplier setting = Frequency multiplier setting f f out out = CPU Internal frequency = CPU Internal frequency = N * f = N * f in in P...

P.17 /64 CPU FSB Frequency CPU FSB Frequency f f in in = FSB (Front Side Bus) frequency = FSB (Front Side Bus) frequency N N = Frequency Multiplier setting = Frequency Multiplier setting f f out out = CPU Internal Core Frequency = CPU Internal Core Frequency = N * f = N * f in in C P U PLL FSB CPU C...

P.18 /64 CPU Frequency Multiplier CPU Frequency Multiplier Klamath PII Klamath PII ‹ Freq. Multiple can be configured by jumpers. Deschute Deschute PII , PIII, and PII , PIII, and Mendocino Celeron Mendocino Celeron ‹ Freq. Multiple setting is internally locked. Engineering Sample Engineering Sample...

P.22 /64 Functions in G3 state being maintained on Functions in G3 state being maintained on board by the BATT power are : board by the BATT power are : ‹ CMOS SRAM (in ICH) ‹ RTC ( Real Time Clock ) (in ICH) ‹ AC Power Loss Restart (in ICH) ‹ New CPU Detection (On board) ‹ Chassis Intrusion (On boa...

P.23 /64 CMOS CMOS Motorola 146818 RTC chip Motorola 146818 RTC chip ‹ 256-Byte CMOS Memory (SRAM) powered by BATT ‹ PIIX4 allows the short-ckt of BATT to clear CMOS. ‹ ICH prefers the RTCRST# to clear CMOS CMOS CMOS ‹ POST = P ower O n S elf T est ICH CMOS M146818 +3VSBLithiumBattery BATT BATT CLRT...

P.24 /64 CPU Presence Detection CPU Presence Detection Slot Slot - - 1 CPU 1 CPU ‹ SLOTOCC# = Slot Occupation S370 CPU S370 CPU ‹ CPUPRES# = CPU Presence This function is powered by Lithium battery This function is powered by Lithium battery ‹ BATT ‹ Still working in G3 state Any action of removing ...

P.29 /64 POWER UP CONTROL POWER UP CONTROL BIOS Setup BIOS Setup \ \ Power Power \ \ Power Up Control Power Up Control ‹ AC Power Loss Restart ‹ PWR Up On external Modem Act ‹ Wake On LAN or PCI Modem card ‹ Wake On PS/2 KB / PS2 Mouse ‹ Wake Up By Keyboard ‹ Wake On USB Device ‹ Automatic Power Up ...

P.31 /64 The ICH directly supports different sleep states (S1 The ICH directly supports different sleep states (S1 - - S5), which S5), which are entered by setting the SLP_EN bit, or due to a Power are entered by setting the SLP_EN bit, or due to a Power Button Override. Button Override. Sleep state...

P.35 /64 AC Power Loss Restart AC Power Loss Restart AC Power Loss AC Power Loss 1. The AC power cord was unplugged from the ATX power supply2. The AC power was lost AC Power Loss Restart AC Power Loss Restart ‹ the AC Power is back ‹ +5V standby and the resulting standby power is back ‹ determine i...

P.36 /64 ICH : AfterG3_En bit ICH : AfterG3_En bit ON ON ‹ Return to S0 OFF OFF ‹ Remain in S5 ON ON → → OFF OFF ‹ CPU is turned on for a while to configure the wake-up circuits of WOL, WOR, etc. WOL WOR State of AC Power Loss BIOS setting Disable Disable S5 ( Soft Off ) Disable Disable S0 (Working)...

P.37 /64 WOR WOR WOR WOR ‹ Wake On Ring ‹ RI# : Ring-Indicate signal is generated by modem to inform the system an incoming call. Modem Modem 1. External Modem2. Internal Modem Card

P.38 /64 Wake On Ring Wake On Ring Internal Modem card Internal Modem card PCI / ISA Bus RI#

P.39 /64 WOR WOR External Modem External Modem RS-232 UART Super I/O +12V, -12V CMOS +5V RRI1# (COM1)RRI2# (COM2)

P.40 /64 WOR WOR Internal Internal Modem Modem Wired ASIC Level Shift RRI1#RRI2# (Before RS232 Transceiver) WOR Connector RI# RIIN 3V Level +3VAux WORRI# RS-232 IC External External Modem Modem ICH ASUS ASIC ( 99127 ) ATX Power Supply PowerButton +3V ± 5V ± 12V SLP_S3#SLP_S5# PS-ON#

P.42 /64 WOL WOL +3VAux WOL# PME +5VSB GND 1 2 3 WOL Connector

P.43 /64 WOL WOL How Wake on LAN works? How Wake on LAN works? System1 w/L101 System2 TP_HUB Sends a wake-up frame is based on Magic Packet to the system1 System1 : 1. Remote network management s/w for client (Intel’s LANDesk s/w) 2. Enable System BIOS WOL3. Receives & analyzes media access cont...

P.46 /64 Wake Up By PS/2 KB Wake Up By PS/2 KB ICH ASUS ASIC ( 99127 ) ATX Power Supply PowerButton +3V ± 5V ± 12V SLP_S3#SLP_S5# IOPWRBTN# LPC ( Super I/O ) +5VSB GPIO 8 KBDATA KBCLK PS2PWR 123 +5V PS2PWR +5VSB Fuse 1 (Poly Switch) Female (to mouse or KB) 1 2 3 4 5 6 PS-ON# +3VAux

P.47 /64 Wake On USB Wake On USB Wake On USB Wake On USB ‹ +5VSB (ATX Srandby Power) is supplied to USB ports by jumper setting CUC2000 CUC2000 USBPWR 123 +5V USBPWR +5VSB Fuse 2(Poly Switch) 1 USB : at least 500mA4 USB : at least 2A

P.49 /64 PME# and 3.3V V PME# and 3.3V V AUX AUX of PCI 2.2 of PCI 2.2 PCI 2.2 adds two more pin definitions: PCI 2.2 adds two more pin definitions: ‹ PME# (pinA19 ) ‹ 3.3V V AUX (pin A14) PME = Power Management Event PME = Power Management Event ‹ active low, open-drain, shared V V AUX AUX = Auxili...

P.51 /64 Power On Self Test Power On Self Test POST POST ‹ P ower O n S elf T est When Power is ON, the CPU will be When Power is ON, the CPU will be RESETed RESETed . And . And the first step of CPU is to read the BIOS and to run the first step of CPU is to read the BIOS and to run the code. the co...

P.52 /64 POST Controller POST Controller POST POST ‹ P ower O n S elf T est After the BIOS code has been completely After the BIOS code has been completely executed, the BIOS will load the first sector executed, the BIOS will load the first sector of mass of mass - - storage device. storage device. ...