Page 2 - Exclusive Remedies
2 How to reach us....................................................................................................................... 4 Product Warranty.................................................................................................................... 5 Limitation of warranty ......
Page 4 - How to reach us; For Technical Support:
4 How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-2738 On the web http://www.futureplus.com For Sales and Marketing Support: FuturePlus Systems Corporation TEL: 719-278-3540 FAX: 719-278-9586 On the web http:/...
Page 5 - Product Warranty; Limitation of warranty
5 Product Warranty Due to wide variety of possible customer target implementations, the FS2334 DDR2 DIMM probe has a 30 day acceptance period by the customer from the date of receipt. If the customer does not contact FuturePlus Systems within 30 days of the receipt of the product it will be said tha...
Page 6 - Software License Agreement; Please; read; this license agreement carefully before opening the media; License Agreement
6 Software License Agreement IMPORTANT - Please read this license agreement carefully before opening the media envelope. Rights in the software are offered only on the condition that the customer agrees to all terms and conditions of the license agreement. Opening the media envelope indicates your a...
Page 7 - Introduction; Definitions; Logic Analyzer Modules
7 Introduction Thank you for purchasing the FuturePlus Systems FS2334 DDR2 DIMM Interposer Logic Analyzer Probe. We think you will find the FS2334, along with your Agilent Technologies Logic Analyzer, a valuable tool for helping to characterize and debug your DDR2-based systems. This Users Guide wil...
Page 8 - or
8 FS2334 Probe Description The FS2334 DDR2 Probe allows you to perform timing analysis measurements on DDR2 DIMM busses. It also provides a Protocol Decoder with the capability of providing State analysis of both Read and Write activity is provided by using the dual sample mode feature available on ...
Page 9 - and
9 Signal Assignments on Probe Pods The overlap in the bit ranges (for DQxx) signals between pods occurs because the bits are assigned to pods in the order that they appear physically on the DDR2 DIMM connector, which is not strictly in logical bit order. This allows the Probe layout to better match ...
Page 10 - Test Points; There are several test point on the board.
10 FS2334 Frontside layout FS2334 Backside layout Test Points There are several test point on the board. The first set of test points are used to select which signals go to the Clk input and the D15 input of Header 2. The shipping configuration for the FS2334 is to have S0 wired to the Clk input, wh...
Page 11 - Connecting to your Target System; Install the DDR2 probe/DIMM into the target system.; Signal Isolation on the Probe
11 Connecting to your Target System To connect the probe to the DDR2 bus, select an available DDR2 slot. Remove the DDR2 DIMM module, if present. Install the DDR2 DIMM module into the 240 pin connector on the top of the FS2334 probe. Install the DDR2 probe/DIMM into the target system. Connect the su...
Page 12 - Write; Read state analysis only
12 Recommended Logic Analyzer Card Requirements and Configuration files 169xx Analyzer Type Timing Analysis State Analysis 667MT/s or slower 16753/4/5/6, 16950 FS234_2 3 cards configured as one module, one timing machine FS234_5 4 cards configured as one logic analyzer state machine. Uses FS1117 800...
Page 14 - Software Requirements; Setting up the 169xx Analyzer; Please note that you are licensing 3 products, both the FS1136 and; . The software can only be
14 Software Requirements Setting up the 169xx Analyzer A CD containing the 16900 software is included in the FS1136 package. The CD contains a setup file that will automatically install the configuration files and protocol decoder onto a PC containing the 16900 operating system or onto a 16900 analy...
Page 15 - Offline Analysis
15 Offline Analysis Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up the analyzer for another person to use the analyzer to capture data. If you have already used the license that was included with your package on a 1680/90/900 analyzer and would like to ha...
Page 17 - TimingZoom Analysis; Decoding DDR Commands
17 TimingZoom Analysis The TimingZoom feature of the 1690x logic analyzer allows for efficient timing analysis of all the signals on the DDR2 DIMM bus. Please refer to the “Setting up the 16900 Analyzer” section of this manual on the use of the general purpose probe feature to determine how to attac...
Page 18 - State Analysis; Overview; State Analysis Operation – Read and Writes above 667MT/s; State mode capture of Reads; Writes at data rates above 667MT/s requires
18 State Analysis Overview There are several choices for State mode analysis using the FS2334 DDR2 probe depending on the speed of the data bus being probed and the number of logic analyzer cards available to the user. At data speeds of up to 667MT/s the logic analyzer can be triggered on BOTH edges...
Page 19 - and one for; Write only
19 State Analysis Operation – Read and Write at 667MT/s or slower State mode capture is performed by using both edges of CK0. This double probing of each signal is handled internally by the Agilent Logic Analyzer using the Dual Sample mode feature. State analysis within these parameters only require...
Page 20 - The process for setting sampling positions at speeds of 800MT/s:
20 The process for setting sampling positions at speeds of 800MT/s: This procedure requires the probe user to capture TimingZoom traces and use the markers to determine the correct sampling positions. This is an iterative, trial and error procedure where adjustments to Data signal sampling positions...
Page 21 - State analysis calibration procedure
21 State analysis calibration procedure This process is in large part the same for both use in the 7 card Read and Write configuration at 800MT/s and for the 4 card configurations. Differences are noted. 1) Start a memory test program that creates a good mixture of reads and writes in a single Timin...
Page 23 - after; a valid State Clock edge.
23 label to be set to the same value. Then you can drag the blue sample position bar back to the right to place it in the position you measured in step 5. The sample position is indicated on the scale at the top of the display as well as on the side under the “Sampling Position” column. The figure a...
Page 24 - Adjusting the sampling positions with controlled stimulus; : You have to have the target system running at 667MT/s for this
24 Adjusting the sampling positions with controlled stimulus This is a special case requiring special stimulus of the DDR2 DIMM bus. This may involve the use of a special memory test card from Ultra-X that can create this special stimulus • The Auto Sample Position Setup and Auto Threshold functions...
Page 26 - State Display
26 State Display The following figure shows a typical DDR2 screen display. Because the analyzer may sample data on both edges of the clock (FS1117) there are going to be some states that have no commands or data associated with them. The Protocol Decoder contains a filter that will allow post filter...
Page 27 - DDR2 Protocol Checking and Performance Tool (FS1140); FS1140 Installation and Licensing
27 DDR2 Protocol Checking and Performance Tool (FS1140) The FS1140 DDR2 Protocol Checking and Performance Tool is a separate VBA-based application that provides a detailed analysis of a 16900 format logic analyzer trace file, captured with an FS2334 DDR2 Interposer probe. The FS1140 is provided as a...
Page 30 - Timing Analysis; Export
30 Export This function takes the data captured and exports it in .csv format to a location the user selects. Repetitive Run This function allows the user to set-up the tool to trigger the logic analyzer a predefined number of times and capture data incrementally on each run. Please note this functi...
Page 32 - Appendix; FS2334 Signal to Logic Analyzer Connector and Channel Mapping
32 Appendix FS2334 Signal to Logic Analyzer Connector and Channel Mapping The following table shows how the FS2334 DDR2 Probe connects DDR2 DIMM signals to the logic analyzer pods and channels. Header 1 - Command Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channe...
Page 42 - Header 14 – ECC bits only this header is not in any config file
42 Header 14 – ECC bits only this header is not in any config file Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 8 D0 CB1 20K ohm to Ground 9 10 Ground Ground 11 12 D1...
Page 44 - Header 6 – Write
44 Header 6 – Write Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 8 D0 DQ36 20K ohm to Ground 9 10 Ground Ground 11 12 D1 DQ32 20K ohm to Ground 13 14 Ground Ground 15...
Page 50 - Header 12 – Read – Duplicates - only data signals
50 Header 12 – Read – Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 8 D0 DQ4 20K ohm to Ground 9 10 Ground Ground 11 12 D1 DQ0 20K ohm t...
Page 52 - Header 10 - Read Duplicates - only data signals
52 Header 10 - Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 8 D0 No connection 20K ohm to Ground 9 10 Ground Ground 11 12 D1 No co...
Page 54 - Header 11 – Read Duplicates - only data signals
54 Header 11 – Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 8 D0 DQ19 20K ohm to Ground 9 10 Ground Ground 11 12 D1 DQ28 20K ohm t...
Page 56 - Header 9 – Read Duplicates - only data signals
56 Header 9 – Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 8 D0 DQ36 20K ohm to Ground 9 10 Ground Ground 11 12 D1 DQ32 20K ohm to...
Page 58 - Header 13 – Read Duplicates - only data signals
58 Header 13 – Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 8 D0 DQ59 20K ohm to Ground 9 10 Ground Ground 11 12 D1 DQ46 20K ohm t...
