Agilent FS2331 - Manual

7 J1 E5385A adapter cables (FS1015) are used to connect to the following logic analyzer cards: 1671X, 16750/1/2/3 E5378A adapter cables (FS1014) are used to connect to the following logic analyzer cards: 1676X, 16754/5/6 FS2331 100 pin Connector to Pod Diagram J2 J3 J4 Four 100 pin SAMTEC connectors...

11 Probe Pod Assignment The FS2331 DDR Probe uses 8 pods. Two are used to capture traffic on the DDR Command bus, and 6 are used for the Data bus, strobes, check bits, masks, and Serial Presence Detect signals. The signals are mapped to pods as follows: Pod Clock Domain (Clock Rate) SIGNAL GROUP 1 O...

12 Probe Switch Settings A switch bank of 6 independent SPST switches is provided on the FS2331 for user selection of a number of probe features. These are detailed below. Switch # Default (factory position) Function 1 Open Not available 2 Open Not available 3 Open Not available 4 CS_Gate_CK0 Open W...

13 Logic Analyzer Signal Threshold Voltage Settings Threshold voltage settings are set at SSTL-2 levels (1.25 V) for all pods in the format specification of the analyzer. The user may have to adjust this setting for optimal performance for their specific target. Eye Finder and/or EyeScan may have to...

14 Card Requirements for PC2700 Systems In order to insure that the FS2331 and the logic analyzer work properly with PC2700 systems it is recommended that the 16753/4/5/6 cards be used when probing at DDR rates of 333Mhz or greater. This recommendation is based on several factors. First, the setup a...

15 Logic Analyzer Card Requirements DDR Bus Speed 16700 Analyzer Type Timing Analysis State Analysis 16717/8/9 2 cards configured as one module with one timing machine 3 cards: • 1 card module with one 167Mhz state machine for Commands • 2 card module with one 333Mhz state machine for Data 200MHz (P...

16 Software Requirements System Software The FS2331 Probe requires version A.02.70.00 (or later) of the 16700 System Operating Software. You can check to see if you already have the correct version by opening the “System Administration” dialog and selecting the “Show Version” button. If you do not h...

17 Note: In the above picture under Logic analyzer pods, the first pod goes to the Odd pod and the second goes to the Even pod of the termination adapter (e.g. Pod B1 goes to odd termination adapter pod and B2 goes to the even termination adapter pod). Configuration Files 167xx Analyzer 169xx Analyz...

18 analyzer cards together to create multi-card modules. You may use modules that are already configured with more than two cards, but only two of the cards (8 pods) will be used for each DDR bus. Remaining pods may be used for any purpose. Assuming your analyzer cards are installed in slots C and D...

19 Load the system config file “DR230_2” for 3 card state. This file will cause all three cards to be configured for state analysis operation. The card in slot C will be setup to capture DDR Commands at the CK0 rate. The full triggering capabilities of the analyzer are available if it is operating i...

20 Connecting to your Target System – Chip Select Many DDR333 systems qualify Command activity using the Chip Select lines, S0:3. This is either because they utilize “2T Timing” in which their control lines (RAS, CAS, WE) may not fully transition to a valid state within one command clock, or because...

21 Chip Select Jumper locations 2) Dedicating a DIMM slot to the FS2331 This approach offers the highest signal integrity. It involves dedicating a DIMM slot to the FS2331, isolating the Chip Select signals on that DIMM connector from the target’s DDR bus and then wiring active Chip Select signals f...

22 § Sleeve the Pin Slide a short length of insulation over the exposed connector pin to fully protect it from contacting the barrel of the hole. Insulation from 30 AWG wire is a good fit.

24 Offline Analysis Data that is saved on a 167xx analyzer in fast binary format, or 16900 analyzer data saved as a *.ala file, can be imported into the 1680/90/900 environment for analysis. You can do offline analysis on a PC if you have the 1680/90/900 operating system installed on the PC, if you ...

25 After clicking “next” you must browse for the fast binary data file you want to import. Once you have located the file and clicked start import, the data should appear in the listing. After the data has been imported you must load the protocol decoder before you will see any decoding. To load the...

26 Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR Commands No Inverse Assembler is used for timing analysis. However, symbols are pre-defined for the DDR Command bus. These decode the RAS, CAS, and WE lines to display the DDR Command as “Read”, “Write”, “Precharge”, etc., s...

27 3. Trigger the analyzer on any burst. 4. Open a new All Waves waveform window that displays measurement results from both the Command and Data analyzers. This can be done from the Workspace window by dragging a waveform display tool onto the Workspace and connecting the output of each Data and Co...

28 Command and Data analyzers. It can take up to 100ns for the intermodule arm signal to make it from the Command analyzer to the Data analyzer. For this reason it is not possible to guarantee a trigger on a burst at a given address which also has a given data pattern. In general the trigger from th...

29 Using Eye Finder with the FS2331 DDR Probe The explanation of the procedure for calibrating the probe for optimal read and write state acquisition provides a description of some useful ways you can interpret Eye Finder results. Eye Finder can be very useful in helping characterize DDR busses. You...

30 Using EyeScan with the FS2331 Probe EyeScan is a feature available on Agilent 16760 and 16753/4/5/6 logic analyzer cards. It provides the ability to perform eye measurements on multiple channels simultaneously. For more detailed information on the use of the feature refer to the Help files for ei...

31 Using the FS2331 DDR Probe with an Interposer (FS1024/25) An interposer with the FS2331 is recommended if the user wants to see the activity in a specific DIMM slot or with a specific DIMM module. An interposer also provides the advantage of providing valid S0:3 signals to the FS2331, which makes...

34 Notice in this display the data valid windows for DATA31-0 and DATA64-32 are reduced in size. This is because the measured windows represent the intersection of the read and write windows. Notice also that there is almost no data valid window for the strobes. This is unavoidable since the timing ...

40 The correct logic analyzer sample position for the data valid windows is just to the left of (before) the analyzer clock. This ensures that the data being sent by the controller prior to issuing the strobe is the data sampled by the analyzer. Before moving on to step 3 the sample positions for al...

41 After these adjustments you should see an Eye Finder display like the above: At this point you should make a note of the sampling position for the data lines. In the diagram above it is indicated as -2.45ns average for all data lines. This number will be used later when choosing the proper adjust...

42 indicating its nominal delay value in 100ps units. Thus a 1700ps delay line will be marked “1705” and a 1200ps delay line will be marked “1205”. The delay lines are accurate to within +/- 50ps) To measure the read burst data valid position, start the stimulus on the DDR bus . If the stimulus cont...

43 • The read strobes straddle the data, as they should for read cycles. • The read data valid windows are about the same size as the write ones were. In many systems however you should not be surprised to find the read windows appreciably smaller than the write windows. This is due to the physics o...

45 Step 4 – Adjust the delay line value to maximize R/W overlap You can use the following formula to calculate the proper value for the read delay line that will maximize overlap between read and write data valid windows: New U18 Delay Line Value = Current U18 Delay Line Value + (Avg. Read Position ...

47 General Information This chapter provides additional reference information including the characteristics and signal connections for the FS2331 DDR Analysis Probe. The following operating characteristics are not specifications, but are typical operating characteristics for the HyperTransport Analy...

48 Signal Connections J1 Data Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground NC 3 4 NC Ground 5 6 Ground DQ0 Odd D0 7 8 Even D0 DQ4 Ground 9 10 Ground DQ1 Odd D1 11 12 E...

50 J2 Data and Command Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground NC 3 4 NC Ground 5 6 Ground CB3 Odd D0 7 8 Even D0 A0 Ground 9 10 Ground CB2 Odd D1 11 12 Even D1 A...

52 J3 Command and Data Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground NC 3 4 NC Ground 5 6 Ground RESETn Odd D0 7 8 Even D0 CB6 Ground 9 10 Ground FETEN Odd D1 11 12 Eve...

54 J4 Data Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground NC 3 4 NC Ground 5 6 Ground SDA Odd D0 7 8 Even D0 SCL Ground 9 10 Ground DQ40 Odd D1 11 12 Even D1 DQ44 Ground...