Agilent FS2101 - Manual

Introduction The PCI Active Analysis Probe module provides a complete interface between any PCI add-in slot and Agilent Logic Analyzers. The Analysis Probe interface buffers and in state mode latches and decodes all PCI cycle types and transactions. The PCI Active Analysis Probe is a passive bus mon...

POD 9 Header 9 16554/5/6/7 expander 2 card POD 1 16550 expander card Pod 3 POD 10 Header 10 16554/5/6/7 expander card POD 2 16550 expander card Pod 4 POD 11 Header 11 16554/5/6/7 expander card POD 3 16550 expander card Pod 5 USER PINS PCI Active Analysis Probe Header 4 contains 8 User Defined pins. ...

1655x,1670/71 P32D_55 5 32 bit Demultiplexed - Analysis Probe PODS 1-6 connect to PODS 1-4 on the Master card and 1-2 on the Slave card 1-2 respectively (PODS 1-6 on the 1670/71) 1655x,1670 P64M_55 5 64-bit Multiplexed - Analysis Probe PODS 1- 4,7,8,11 connect to Logic Analyzer PODS 1-4 on the Maste...

The STAT variable The STAT variable is used by the PCI inverse assembler to decode PCI bus transactions. It should not be changed or deleted from the format menu. The signals that make up the STAT variable are listed in the following table. The STAT variable can be useful to set up SYMBOLS since it ...

RESRVD 0100 RESRVD 0101 MEM_RD 0110 MEM_WR 0111 RESRVD 1000 RESRVD 1001 CON_RD 1010 CON_WR 1011 MEMRDM 1100 DAC_CY 1101 MEMRDL 1110 MEMWRI 1111 I/O_XACTIONS 001X MEM_XACTIONS 011X CONFIG_XACTIONS 101X Theory of Operation The PCI Active Analysis Probe is a universal PCI short card that attaches to Ag...

The Latching Buffers The latching buffers are used only for state mode. The entire PCI bus (except the clock) is latched in these buffers on the rising edge of the PCI clock. The input to the latching buffers is output port 1 from the input buffers. The latching buffers are IDT 162511 latching buffe...

State Analysis This chapter explains how to configure the PCI Active Analysis Probe to perform state analysis on the PCI Local Bus. The configuration software on the flexible diskette sets up the format specification menu of the logic analyzer for compatibility with the PCI Local Bus. The next chapt...

The following error messages are reported by the PCI inverse assembler. Error Messages ERROR-NO DEVICE SELECTED This error is displayed during a non special cycle data phase when IRDY and TRDY are asserted and DEVSEL is not asserted. ERROR DEVSEL ASSERTED This error is displayed during a special cyc...

Timing Analysis Installation Quick Reference The following procedure describes the major steps required to perform timing analysis measurements with the PCI Active Analysis Probe module. 1. Set the State/Timing switch to TIMING. The State LED will be doused. See page 10 of this manual for details on...

General Information This chapter provides additional reference information including the characteristics and signal connections for the PCI Active Analysis Probe module. Characteristics The following operating characteristics are not specifications, but are typical operating characteristics for the ...

Minimum Clock Period (State) 0 to 33Mhz PCI clock for State mode and 0-100Mhz for Timing Mode. Signal loading The PCI Active Analysis Probe logic analyzer interface presents only one electrical load on each PCI bus signal. However, the extender card connector is an additional 4 inches beyond the max...

The PCI Active Analysis Probe module monitors signals for both state and timing analysis. The below figure displays how the cable headers are numbered. Signal Connections 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 The following tabl...